| blob | 7bffb70b9fe25cd71750428578ba961561412ee6 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 *
11 * This file contains low-level assembler routines for managing
12 * the PowerPC MMU hash table. (PPC 8xx processors don't use a
13 * hash table, so this file is not used on them.)
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <asm/reg.h>
23 #include <asm/page.h>
24 #include <asm/pgtable.h>
25 #include <asm/cputable.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/thread_info.h>
28 #include <asm/asm-offsets.h>
30 #ifdef CONFIG_SMP
31 .section .bss
32 .align 2
33 .globl mmu_hash_lock
34 mmu_hash_lock:
35 .space 4
36 #endif /* CONFIG_SMP */
38 /*
39 * Sync CPUs with hash_page taking & releasing the hash
40 * table lock
41 */
42 #ifdef CONFIG_SMP
43 .text
44 _GLOBAL(hash_page_sync)
45 mfmsr r10
46 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
47 mtmsr r0
48 lis r8,mmu_hash_lock@h
49 ori r8,r8,mmu_hash_lock@l
50 lis r0,0x0fff
51 b 10f
52 11: lwz r6,0(r8)
53 cmpwi 0,r6,0
54 bne 11b
55 10: lwarx r6,0,r8
56 cmpwi 0,r6,0
57 bne- 11b
58 stwcx. r0,0,r8
59 bne- 10b
60 isync
61 eieio
62 li r0,0
63 stw r0,0(r8)
64 mtmsr r10
65 blr
66 #endif /* CONFIG_SMP */
68 /*
69 * Load a PTE into the hash table, if possible.
70 * The address is in r4, and r3 contains an access flag:
71 * _PAGE_RW (0x400) if a write.
72 * r9 contains the SRR1 value, from which we use the MSR_PR bit.
73 * SPRG3 contains the physical address of the current task's thread.
74 *
75 * Returns to the caller if the access is illegal or there is no
76 * mapping for the address. Otherwise it places an appropriate PTE
77 * in the hash table and returns from the exception.
78 * Uses r0, r3 - r8, r10, ctr, lr.
79 */
80 .text
81 _GLOBAL(hash_page)
82 tophys(r7,0) /* gets -KERNELBASE into r7 */
83 #ifdef CONFIG_SMP
84 addis r8,r7,mmu_hash_lock@h
85 ori r8,r8,mmu_hash_lock@l
86 lis r0,0x0fff
87 b 10f
88 11: lwz r6,0(r8)
89 cmpwi 0,r6,0
90 bne 11b
91 10: lwarx r6,0,r8
92 cmpwi 0,r6,0
93 bne- 11b
94 stwcx. r0,0,r8
95 bne- 10b
96 isync
97 #endif
98 /* Get PTE (linux-style) and check access */
99 lis r0,KERNELBASE@h /* check if kernel address */
100 cmplw 0,r4,r0
101 mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */
102 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
103 lwz r5,PGDIR(r8) /* virt page-table root */
104 blt+ 112f /* assume user more likely */
105 lis r5,swapper_pg_dir@ha /* if kernel address, use */
106 addi r5,r5,swapper_pg_dir@l /* kernel page table */
107 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
108 112: add r5,r5,r7 /* convert to phys addr */
109 #ifndef CONFIG_PTE_64BIT
110 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
111 lwz r8,0(r5) /* get pmd entry */
112 rlwinm. r8,r8,0,0,19 /* extract address of pte page */
113 #else
114 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */
115 lwzx r8,r8,r5 /* Get L1 entry */
116 rlwinm. r8,r8,0,0,20 /* extract pt base address */
117 #endif
118 #ifdef CONFIG_SMP
119 beq- hash_page_out /* return if no mapping */
120 #else
121 /* XXX it seems like the 601 will give a machine fault on the
122 rfi if its alignment is wrong (bottom 4 bits of address are
123 8 or 0xc) and we have had a not-taken conditional branch
124 to the address following the rfi. */
125 beqlr-
126 #endif
127 #ifndef CONFIG_PTE_64BIT
128 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
129 #else
130 rlwimi r8,r4,23,20,28 /* compute pte address */
131 #endif
132 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
133 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
135 /*
136 * Update the linux PTE atomically. We do the lwarx up-front
137 * because almost always, there won't be a permission violation
138 * and there won't already be an HPTE, and thus we will have
139 * to update the PTE to set _PAGE_HASHPTE. -- paulus.
140 *
141 * If PTE_64BIT is set, the low word is the flags word; use that
142 * word for locking since it contains all the interesting bits.
143 */
144 #if (PTE_FLAGS_OFFSET != 0)
145 addi r8,r8,PTE_FLAGS_OFFSET
146 #endif
147 retry:
148 lwarx r6,0,r8 /* get linux-style pte, flag word */
149 andc. r5,r3,r6 /* check access & ~permission */
150 #ifdef CONFIG_SMP
151 bne- hash_page_out /* return if access not permitted */
152 #else
153 bnelr-
154 #endif
155 or r5,r0,r6 /* set accessed/dirty bits */
156 #ifdef CONFIG_PTE_64BIT
157 #ifdef CONFIG_SMP
158 subf r10,r6,r8 /* create false data dependency */
159 subi r10,r10,PTE_FLAGS_OFFSET
160 lwzx r10,r6,r10 /* Get upper PTE word */
161 #else
162 lwz r10,-PTE_FLAGS_OFFSET(r8)
163 #endif /* CONFIG_SMP */
164 #endif /* CONFIG_PTE_64BIT */
165 stwcx. r5,0,r8 /* attempt to update PTE */
166 bne- retry /* retry if someone got there first */
168 mfsrin r3,r4 /* get segment reg for segment */
169 mfctr r0
170 stw r0,_CTR(r11)
171 bl create_hpte /* add the hash table entry */
173 #ifdef CONFIG_SMP
174 eieio
175 addis r8,r7,mmu_hash_lock@ha
176 li r0,0
177 stw r0,mmu_hash_lock@l(r8)
178 #endif
180 /* Return from the exception */
181 lwz r5,_CTR(r11)
182 mtctr r5
183 lwz r0,GPR0(r11)
184 lwz r7,GPR7(r11)
185 lwz r8,GPR8(r11)
186 b fast_exception_return
188 #ifdef CONFIG_SMP
189 hash_page_out:
190 eieio
191 addis r8,r7,mmu_hash_lock@ha
192 li r0,0
193 stw r0,mmu_hash_lock@l(r8)
194 blr
195 #endif /* CONFIG_SMP */
197 /*
198 * Add an entry for a particular page to the hash table.
199 *
200 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
201 *
202 * We assume any necessary modifications to the pte (e.g. setting
203 * the accessed bit) have already been done and that there is actually
204 * a hash table in use (i.e. we're not on a 603).
205 */
206 _GLOBAL(add_hash_page)
207 mflr r0
208 stw r0,4(r1)
210 /* Convert context and va to VSID */
211 mulli r3,r3,897*16 /* multiply context by context skew */
212 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
213 mulli r0,r0,0x111 /* multiply by ESID skew */
214 add r3,r3,r0 /* note create_hpte trims to 24 bits */
216 #ifdef CONFIG_SMP
217 rlwinm r8,r1,0,0,(31-THREAD_SHIFT) /* use cpu number to make tag */
218 lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */
219 oris r8,r8,12
220 #endif /* CONFIG_SMP */
222 /*
223 * We disable interrupts here, even on UP, because we don't
224 * want to race with hash_page, and because we want the
225 * _PAGE_HASHPTE bit to be a reliable indication of whether
226 * the HPTE exists (or at least whether one did once).
227 * We also turn off the MMU for data accesses so that we
228 * we can't take a hash table miss (assuming the code is
229 * covered by a BAT). -- paulus
230 */
231 mfmsr r9
232 SYNC
233 rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */
234 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
235 mtmsr r0
236 SYNC_601
237 isync
239 tophys(r7,0)
241 #ifdef CONFIG_SMP
242 addis r6,r7,mmu_hash_lock@ha
243 addi r6,r6,mmu_hash_lock@l
244 10: lwarx r0,0,r6 /* take the mmu_hash_lock */
245 cmpi 0,r0,0
246 bne- 11f
247 stwcx. r8,0,r6
248 beq+ 12f
249 11: lwz r0,0(r6)
250 cmpi 0,r0,0
251 beq 10b
252 b 11b
253 12: isync
254 #endif
256 /*
257 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
258 * If _PAGE_HASHPTE was already set, we don't replace the existing
259 * HPTE, so we just unlock and return.
260 */
261 mr r8,r5
262 #ifndef CONFIG_PTE_64BIT
263 rlwimi r8,r4,22,20,29
264 #else
265 rlwimi r8,r4,23,20,28
266 addi r8,r8,PTE_FLAGS_OFFSET
267 #endif
268 1: lwarx r6,0,r8
269 andi. r0,r6,_PAGE_HASHPTE
270 bne 9f /* if HASHPTE already set, done */
271 #ifdef CONFIG_PTE_64BIT
272 #ifdef CONFIG_SMP
273 subf r10,r6,r8 /* create false data dependency */
274 subi r10,r10,PTE_FLAGS_OFFSET
275 lwzx r10,r6,r10 /* Get upper PTE word */
276 #else
277 lwz r10,-PTE_FLAGS_OFFSET(r8)
278 #endif /* CONFIG_SMP */
279 #endif /* CONFIG_PTE_64BIT */
280 ori r5,r6,_PAGE_HASHPTE
281 stwcx. r5,0,r8
282 bne- 1b
284 bl create_hpte
286 9:
287 #ifdef CONFIG_SMP
288 addis r6,r7,mmu_hash_lock@ha
289 addi r6,r6,mmu_hash_lock@l
290 eieio
291 li r0,0
292 stw r0,0(r6) /* clear mmu_hash_lock */
293 #endif
295 /* reenable interrupts and DR */
296 mtmsr r9
297 SYNC_601
298 isync
300 lwz r0,4(r1)
301 mtlr r0
302 blr
304 /*
305 * This routine adds a hardware PTE to the hash table.
306 * It is designed to be called with the MMU either on or off.
307 * r3 contains the VSID, r4 contains the virtual address,
308 * r5 contains the linux PTE, r6 contains the old value of the
309 * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
310 * offset to be added to addresses (0 if the MMU is on,
311 * -KERNELBASE if it is off). r10 contains the upper half of
312 * the PTE if CONFIG_PTE_64BIT.
313 * On SMP, the caller should have the mmu_hash_lock held.
314 * We assume that the caller has (or will) set the _PAGE_HASHPTE
315 * bit in the linux PTE in memory. The value passed in r6 should
316 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
317 * this routine will skip the search for an existing HPTE.
318 * This procedure modifies r0, r3 - r6, r8, cr0.
319 * -- paulus.
320 *
321 * For speed, 4 of the instructions get patched once the size and
322 * physical address of the hash table are known. These definitions
323 * of Hash_base and Hash_bits below are just an example.
324 */
325 Hash_base = 0xc0180000
326 Hash_bits = 12 /* e.g. 256kB hash table */
327 Hash_msk = (((1 << Hash_bits) - 1) * 64)
329 /* defines for the PTE format for 32-bit PPCs */
330 #define HPTE_SIZE 8
331 #define PTEG_SIZE 64
332 #define LG_PTEG_SIZE 6
333 #define LDPTEu lwzu
334 #define LDPTE lwz
335 #define STPTE stw
336 #define CMPPTE cmpw
337 #define PTE_H 0x40
338 #define PTE_V 0x80000000
339 #define TST_V(r) rlwinm. r,r,0,0,0
340 #define SET_V(r) oris r,r,PTE_V@h
341 #define CLR_V(r,t) rlwinm r,r,0,1,31
343 #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
344 #define HASH_RIGHT 31-LG_PTEG_SIZE
346 _GLOBAL(create_hpte)
347 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
348 rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */
349 rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
350 and r8,r8,r0 /* writable if _RW & _DIRTY */
351 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
352 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
353 ori r8,r8,0xe14 /* clear out reserved bits and M */
354 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
355 BEGIN_FTR_SECTION
356 ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
357 END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
358 #ifdef CONFIG_PTE_64BIT
359 /* Put the XPN bits into the PTE */
360 rlwimi r8,r10,8,20,22
361 rlwimi r8,r10,2,29,29
362 #endif
364 /* Construct the high word of the PPC-style PTE (r5) */
365 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
366 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
367 SET_V(r5) /* set V (valid) bit */
369 /* Get the address of the primary PTE group in the hash table (r3) */
370 _GLOBAL(hash_page_patch_A)
371 addis r0,r7,Hash_base@h /* base address of hash table */
372 rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
373 rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
374 xor r3,r3,r0 /* make primary hash */
375 li r0,8 /* PTEs/group */
377 /*
378 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
379 * if it is clear, meaning that the HPTE isn't there already...
380 */
381 andi. r6,r6,_PAGE_HASHPTE
382 beq+ 10f /* no PTE: go look for an empty slot */
383 tlbie r4
385 addis r4,r7,htab_hash_searches@ha
386 lwz r6,htab_hash_searches@l(r4)
387 addi r6,r6,1 /* count how many searches we do */
388 stw r6,htab_hash_searches@l(r4)
390 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
391 mtctr r0
392 addi r4,r3,-HPTE_SIZE
393 1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
394 CMPPTE 0,r6,r5
395 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
396 beq+ found_slot
398 /* Search the secondary PTEG for a matching PTE */
399 ori r5,r5,PTE_H /* set H (secondary hash) bit */
400 _GLOBAL(hash_page_patch_B)
401 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
402 xori r4,r4,(-PTEG_SIZE & 0xffff)
403 addi r4,r4,-HPTE_SIZE
404 mtctr r0
405 2: LDPTEu r6,HPTE_SIZE(r4)
406 CMPPTE 0,r6,r5
407 bdnzf 2,2b
408 beq+ found_slot
409 xori r5,r5,PTE_H /* clear H bit again */
411 /* Search the primary PTEG for an empty slot */
412 10: mtctr r0
413 addi r4,r3,-HPTE_SIZE /* search primary PTEG */
414 1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
415 TST_V(r6) /* test valid bit */
416 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
417 beq+ found_empty
419 /* update counter of times that the primary PTEG is full */
420 addis r4,r7,primary_pteg_full@ha
421 lwz r6,primary_pteg_full@l(r4)
422 addi r6,r6,1
423 stw r6,primary_pteg_full@l(r4)
425 /* Search the secondary PTEG for an empty slot */
426 ori r5,r5,PTE_H /* set H (secondary hash) bit */
427 _GLOBAL(hash_page_patch_C)
428 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
429 xori r4,r4,(-PTEG_SIZE & 0xffff)
430 addi r4,r4,-HPTE_SIZE
431 mtctr r0
432 2: LDPTEu r6,HPTE_SIZE(r4)
433 TST_V(r6)
434 bdnzf 2,2b
435 beq+ found_empty
436 xori r5,r5,PTE_H /* clear H bit again */
438 /*
439 * Choose an arbitrary slot in the primary PTEG to overwrite.
440 * Since both the primary and secondary PTEGs are full, and we
441 * have no information that the PTEs in the primary PTEG are
442 * more important or useful than those in the secondary PTEG,
443 * and we know there is a definite (although small) speed
444 * advantage to putting the PTE in the primary PTEG, we always
445 * put the PTE in the primary PTEG.
446 *
447 * In addition, we skip any slot that is mapping kernel text in
448 * order to avoid a deadlock when not using BAT mappings if
449 * trying to hash in the kernel hash code itself after it has
450 * already taken the hash table lock. This works in conjunction
451 * with pre-faulting of the kernel text.
452 *
453 * If the hash table bucket is full of kernel text entries, we'll
454 * lockup here but that shouldn't happen
455 */
457 1: addis r4,r7,next_slot@ha /* get next evict slot */
458 lwz r6,next_slot@l(r4)
459 addi r6,r6,HPTE_SIZE /* search for candidate */
460 andi. r6,r6,7*HPTE_SIZE
461 stw r6,next_slot@l(r4)
462 add r4,r3,r6
463 LDPTE r0,HPTE_SIZE/2(r4) /* get PTE second word */
464 clrrwi r0,r0,12
465 lis r6,etext@h
466 ori r6,r6,etext@l /* get etext */
467 tophys(r6,r6)
468 cmpl cr0,r0,r6 /* compare and try again */
469 blt 1b
471 #ifndef CONFIG_SMP
472 /* Store PTE in PTEG */
473 found_empty:
474 STPTE r5,0(r4)
475 found_slot:
476 STPTE r8,HPTE_SIZE/2(r4)
478 #else /* CONFIG_SMP */
479 /*
480 * Between the tlbie above and updating the hash table entry below,
481 * another CPU could read the hash table entry and put it in its TLB.
482 * There are 3 cases:
483 * 1. using an empty slot
484 * 2. updating an earlier entry to change permissions (i.e. enable write)
485 * 3. taking over the PTE for an unrelated address
486 *
487 * In each case it doesn't really matter if the other CPUs have the old
488 * PTE in their TLB. So we don't need to bother with another tlbie here,
489 * which is convenient as we've overwritten the register that had the
490 * address. :-) The tlbie above is mainly to make sure that this CPU comes
491 * and gets the new PTE from the hash table.
492 *
493 * We do however have to make sure that the PTE is never in an invalid
494 * state with the V bit set.
495 */
496 found_empty:
497 found_slot:
498 CLR_V(r5,r0) /* clear V (valid) bit in PTE */
499 STPTE r5,0(r4)
500 sync
501 TLBSYNC
502 STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
503 sync
504 SET_V(r5)
505 STPTE r5,0(r4) /* finally set V bit in PTE */
506 #endif /* CONFIG_SMP */
508 sync /* make sure pte updates get to memory */
509 blr
511 .section .bss
512 .align 2
513 next_slot:
514 .space 4
515 primary_pteg_full:
516 .space 4
517 htab_hash_searches:
518 .space 4
519 .previous
521 /*
522 * Flush the entry for a particular page from the hash table.
523 *
524 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
525 * int count)
526 *
527 * We assume that there is a hash table in use (Hash != 0).
528 */
529 _GLOBAL(flush_hash_pages)
530 tophys(r7,0)
532 /*
533 * We disable interrupts here, even on UP, because we want
534 * the _PAGE_HASHPTE bit to be a reliable indication of
535 * whether the HPTE exists (or at least whether one did once).
536 * We also turn off the MMU for data accesses so that we
537 * we can't take a hash table miss (assuming the code is
538 * covered by a BAT). -- paulus
539 */
540 mfmsr r10
541 SYNC
542 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
543 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
544 mtmsr r0
545 SYNC_601
546 isync
548 /* First find a PTE in the range that has _PAGE_HASHPTE set */
549 #ifndef CONFIG_PTE_64BIT
550 rlwimi r5,r4,22,20,29
551 #else
552 rlwimi r5,r4,23,20,28
553 #endif
554 1: lwz r0,PTE_FLAGS_OFFSET(r5)
555 cmpwi cr1,r6,1
556 andi. r0,r0,_PAGE_HASHPTE
557 bne 2f
558 ble cr1,19f
559 addi r4,r4,0x1000
560 addi r5,r5,PTE_SIZE
561 addi r6,r6,-1
562 b 1b
564 /* Convert context and va to VSID */
565 2: mulli r3,r3,897*16 /* multiply context by context skew */
566 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
567 mulli r0,r0,0x111 /* multiply by ESID skew */
568 add r3,r3,r0 /* note code below trims to 24 bits */
570 /* Construct the high word of the PPC-style PTE (r11) */
571 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
572 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
573 SET_V(r11) /* set V (valid) bit */
575 #ifdef CONFIG_SMP
576 addis r9,r7,mmu_hash_lock@ha
577 addi r9,r9,mmu_hash_lock@l
578 rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
579 add r8,r8,r7
580 lwz r8,TI_CPU(r8)
581 oris r8,r8,9
582 10: lwarx r0,0,r9
583 cmpi 0,r0,0
584 bne- 11f
585 stwcx. r8,0,r9
586 beq+ 12f
587 11: lwz r0,0(r9)
588 cmpi 0,r0,0
589 beq 10b
590 b 11b
591 12: isync
592 #endif
594 /*
595 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is
596 * already clear, we're done (for this pte). If not,
597 * clear it (atomically) and proceed. -- paulus.
598 */
599 #if (PTE_FLAGS_OFFSET != 0)
600 addi r5,r5,PTE_FLAGS_OFFSET
601 #endif
602 33: lwarx r8,0,r5 /* fetch the pte flags word */
603 andi. r0,r8,_PAGE_HASHPTE
604 beq 8f /* done if HASHPTE is already clear */
605 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
606 stwcx. r8,0,r5 /* update the pte */
607 bne- 33b
609 /* Get the address of the primary PTE group in the hash table (r3) */
610 _GLOBAL(flush_hash_patch_A)
611 addis r8,r7,Hash_base@h /* base address of hash table */
612 rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
613 rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
614 xor r8,r0,r8 /* make primary hash */
616 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
617 li r0,8 /* PTEs/group */
618 mtctr r0
619 addi r12,r8,-HPTE_SIZE
620 1: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */
621 CMPPTE 0,r0,r11
622 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
623 beq+ 3f
625 /* Search the secondary PTEG for a matching PTE */
626 ori r11,r11,PTE_H /* set H (secondary hash) bit */
627 li r0,8 /* PTEs/group */
628 _GLOBAL(flush_hash_patch_B)
629 xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
630 xori r12,r12,(-PTEG_SIZE & 0xffff)
631 addi r12,r12,-HPTE_SIZE
632 mtctr r0
633 2: LDPTEu r0,HPTE_SIZE(r12)
634 CMPPTE 0,r0,r11
635 bdnzf 2,2b
636 xori r11,r11,PTE_H /* clear H again */
637 bne- 4f /* should rarely fail to find it */
639 3: li r0,0
640 STPTE r0,0(r12) /* invalidate entry */
641 4: sync
642 tlbie r4 /* in hw tlb too */
643 sync
645 8: ble cr1,9f /* if all ptes checked */
646 81: addi r6,r6,-1
647 addi r5,r5,PTE_SIZE
648 addi r4,r4,0x1000
649 lwz r0,0(r5) /* check next pte */
650 cmpwi cr1,r6,1
651 andi. r0,r0,_PAGE_HASHPTE
652 bne 33b
653 bgt cr1,81b
655 9:
656 #ifdef CONFIG_SMP
657 TLBSYNC
658 li r0,0
659 stw r0,0(r9) /* clear mmu_hash_lock */
660 #endif
662 19: mtmsr r10
663 SYNC_601
664 isync
665 blr