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Linux 2.6.28-rc5
[cris-mirror.git] / arch / powerpc / sysdev / mpic.c
blobf6299cca7814b8eda0434e94953db9fe6b38ba9e
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15 #undef DEBUG
16 #undef DEBUG_IPI
17 #undef DEBUG_IRQ
18 #undef DEBUG_LOW
19
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
32 #include <asm/io.h>
33 #include <asm/pgtable.h>
34 #include <asm/irq.h>
35 #include <asm/machdep.h>
36 #include <asm/mpic.h>
37 #include <asm/smp.h>
38
39 #include "mpic.h"
40
41 #ifdef DEBUG
42 #define DBG(fmt...) printk(fmt)
43 #else
44 #define DBG(fmt...)
45 #endif
46
47 static struct mpic *mpics;
48 static struct mpic *mpic_primary;
49 static DEFINE_SPINLOCK(mpic_lock);
50
51 #ifdef CONFIG_PPC32 /* XXX for now */
52 #ifdef CONFIG_IRQ_ALL_CPUS
53 #define distribute_irqs (1)
54 #else
55 #define distribute_irqs (0)
56 #endif
57 #endif
58
59 #ifdef CONFIG_MPIC_WEIRD
60 static u32 mpic_infos[][MPIC_IDX_END] = {
61 [0] = { /* Original OpenPIC compatible MPIC */
62 MPIC_GREG_BASE,
63 MPIC_GREG_FEATURE_0,
64 MPIC_GREG_GLOBAL_CONF_0,
65 MPIC_GREG_VENDOR_ID,
66 MPIC_GREG_IPI_VECTOR_PRI_0,
67 MPIC_GREG_IPI_STRIDE,
68 MPIC_GREG_SPURIOUS,
69 MPIC_GREG_TIMER_FREQ,
70
71 MPIC_TIMER_BASE,
72 MPIC_TIMER_STRIDE,
73 MPIC_TIMER_CURRENT_CNT,
74 MPIC_TIMER_BASE_CNT,
75 MPIC_TIMER_VECTOR_PRI,
76 MPIC_TIMER_DESTINATION,
77
78 MPIC_CPU_BASE,
79 MPIC_CPU_STRIDE,
80 MPIC_CPU_IPI_DISPATCH_0,
81 MPIC_CPU_IPI_DISPATCH_STRIDE,
82 MPIC_CPU_CURRENT_TASK_PRI,
83 MPIC_CPU_WHOAMI,
84 MPIC_CPU_INTACK,
85 MPIC_CPU_EOI,
86 MPIC_CPU_MCACK,
87
88 MPIC_IRQ_BASE,
89 MPIC_IRQ_STRIDE,
90 MPIC_IRQ_VECTOR_PRI,
91 MPIC_VECPRI_VECTOR_MASK,
92 MPIC_VECPRI_POLARITY_POSITIVE,
93 MPIC_VECPRI_POLARITY_NEGATIVE,
94 MPIC_VECPRI_SENSE_LEVEL,
95 MPIC_VECPRI_SENSE_EDGE,
96 MPIC_VECPRI_POLARITY_MASK,
97 MPIC_VECPRI_SENSE_MASK,
98 MPIC_IRQ_DESTINATION
99 },
100 [1] = { /* Tsi108/109 PIC */
101 TSI108_GREG_BASE,
102 TSI108_GREG_FEATURE_0,
103 TSI108_GREG_GLOBAL_CONF_0,
104 TSI108_GREG_VENDOR_ID,
105 TSI108_GREG_IPI_VECTOR_PRI_0,
106 TSI108_GREG_IPI_STRIDE,
107 TSI108_GREG_SPURIOUS,
108 TSI108_GREG_TIMER_FREQ,
109
110 TSI108_TIMER_BASE,
111 TSI108_TIMER_STRIDE,
112 TSI108_TIMER_CURRENT_CNT,
113 TSI108_TIMER_BASE_CNT,
114 TSI108_TIMER_VECTOR_PRI,
115 TSI108_TIMER_DESTINATION,
116
117 TSI108_CPU_BASE,
118 TSI108_CPU_STRIDE,
119 TSI108_CPU_IPI_DISPATCH_0,
120 TSI108_CPU_IPI_DISPATCH_STRIDE,
121 TSI108_CPU_CURRENT_TASK_PRI,
122 TSI108_CPU_WHOAMI,
123 TSI108_CPU_INTACK,
124 TSI108_CPU_EOI,
125 TSI108_CPU_MCACK,
126
127 TSI108_IRQ_BASE,
128 TSI108_IRQ_STRIDE,
129 TSI108_IRQ_VECTOR_PRI,
130 TSI108_VECPRI_VECTOR_MASK,
131 TSI108_VECPRI_POLARITY_POSITIVE,
132 TSI108_VECPRI_POLARITY_NEGATIVE,
133 TSI108_VECPRI_SENSE_LEVEL,
134 TSI108_VECPRI_SENSE_EDGE,
135 TSI108_VECPRI_POLARITY_MASK,
136 TSI108_VECPRI_SENSE_MASK,
137 TSI108_IRQ_DESTINATION
138 },
139 };
140
141 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
142
143 #else /* CONFIG_MPIC_WEIRD */
144
145 #define MPIC_INFO(name) MPIC_##name
146
147 #endif /* CONFIG_MPIC_WEIRD */
148
149 /*
150 * Register accessor functions
151 */
152
153
154 static inline u32 _mpic_read(enum mpic_reg_type type,
155 struct mpic_reg_bank *rb,
156 unsigned int reg)
157 {
158 switch(type) {
159 #ifdef CONFIG_PPC_DCR
160 case mpic_access_dcr:
161 return dcr_read(rb->dhost, reg);
162 #endif
163 case mpic_access_mmio_be:
164 return in_be32(rb->base + (reg >> 2));
165 case mpic_access_mmio_le:
166 default:
167 return in_le32(rb->base + (reg >> 2));
168 }
169 }
170
171 static inline void _mpic_write(enum mpic_reg_type type,
172 struct mpic_reg_bank *rb,
173 unsigned int reg, u32 value)
174 {
175 switch(type) {
176 #ifdef CONFIG_PPC_DCR
177 case mpic_access_dcr:
178 dcr_write(rb->dhost, reg, value);
179 break;
180 #endif
181 case mpic_access_mmio_be:
182 out_be32(rb->base + (reg >> 2), value);
183 break;
184 case mpic_access_mmio_le:
185 default:
186 out_le32(rb->base + (reg >> 2), value);
187 break;
188 }
189 }
190
191 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
192 {
193 enum mpic_reg_type type = mpic->reg_type;
194 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
195 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
196
197 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
198 type = mpic_access_mmio_be;
199 return _mpic_read(type, &mpic->gregs, offset);
200 }
201
202 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
203 {
204 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
205 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
206
207 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
208 }
209
210 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
211 {
212 unsigned int cpu = 0;
213
214 if (mpic->flags & MPIC_PRIMARY)
215 cpu = hard_smp_processor_id();
216 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
217 }
218
219 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
220 {
221 unsigned int cpu = 0;
222
223 if (mpic->flags & MPIC_PRIMARY)
224 cpu = hard_smp_processor_id();
225
226 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
227 }
228
229 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
230 {
231 unsigned int isu = src_no >> mpic->isu_shift;
232 unsigned int idx = src_no & mpic->isu_mask;
233
234 #ifdef CONFIG_MPIC_BROKEN_REGREAD
235 if (reg == 0)
236 return mpic->isu_reg0_shadow[idx];
237 else
238 #endif
239 return _mpic_read(mpic->reg_type, &mpic->isus[isu],
240 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
241 }
242
243 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
244 unsigned int reg, u32 value)
245 {
246 unsigned int isu = src_no >> mpic->isu_shift;
247 unsigned int idx = src_no & mpic->isu_mask;
248
249 _mpic_write(mpic->reg_type, &mpic->isus[isu],
250 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
251
252 #ifdef CONFIG_MPIC_BROKEN_REGREAD
253 if (reg == 0)
254 mpic->isu_reg0_shadow[idx] = value;
255 #endif
256 }
257
258 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
259 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
260 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
261 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
262 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
263 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
264 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
265 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
266
267
268 /*
269 * Low level utility functions
270 */
271
272
273 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
274 struct mpic_reg_bank *rb, unsigned int offset,
275 unsigned int size)
276 {
277 rb->base = ioremap(phys_addr + offset, size);
278 BUG_ON(rb->base == NULL);
279 }
280
281 #ifdef CONFIG_PPC_DCR
282 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
283 unsigned int offset, unsigned int size)
284 {
285 const u32 *dbasep;
286
287 dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL);
288
289 rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size);
290 BUG_ON(!DCR_MAP_OK(rb->dhost));
291 }
292
293 static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr,
294 struct mpic_reg_bank *rb, unsigned int offset,
295 unsigned int size)
296 {
297 if (mpic->flags & MPIC_USES_DCR)
298 _mpic_map_dcr(mpic, rb, offset, size);
299 else
300 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
301 }
302 #else /* CONFIG_PPC_DCR */
303 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
304 #endif /* !CONFIG_PPC_DCR */
305
306
307
308 /* Check if we have one of those nice broken MPICs with a flipped endian on
309 * reads from IPI registers
310 */
311 static void __init mpic_test_broken_ipi(struct mpic *mpic)
312 {
313 u32 r;
314
315 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
316 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
317
318 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
319 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
320 mpic->flags |= MPIC_BROKEN_IPI;
321 }
322 }
323
324 #ifdef CONFIG_MPIC_U3_HT_IRQS
325
326 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
327 * to force the edge setting on the MPIC and do the ack workaround.
328 */
329 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
330 {
331 if (source >= 128 || !mpic->fixups)
332 return 0;
333 return mpic->fixups[source].base != NULL;
334 }
335
336
337 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
338 {
339 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
340
341 if (fixup->applebase) {
342 unsigned int soff = (fixup->index >> 3) & ~3;
343 unsigned int mask = 1U << (fixup->index & 0x1f);
344 writel(mask, fixup->applebase + soff);
345 } else {
346 spin_lock(&mpic->fixup_lock);
347 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
348 writel(fixup->data, fixup->base + 4);
349 spin_unlock(&mpic->fixup_lock);
350 }
351 }
352
353 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
354 unsigned int irqflags)
355 {
356 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
357 unsigned long flags;
358 u32 tmp;
359
360 if (fixup->base == NULL)
361 return;
362
363 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
364 source, irqflags, fixup->index);
365 spin_lock_irqsave(&mpic->fixup_lock, flags);
366 /* Enable and configure */
367 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
368 tmp = readl(fixup->base + 4);
369 tmp &= ~(0x23U);
370 if (irqflags & IRQ_LEVEL)
371 tmp |= 0x22;
372 writel(tmp, fixup->base + 4);
373 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
374
375 #ifdef CONFIG_PM
376 /* use the lowest bit inverted to the actual HW,
377 * set if this fixup was enabled, clear otherwise */
378 mpic->save_data[source].fixup_data = tmp | 1;
379 #endif
380 }
381
382 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
383 unsigned int irqflags)
384 {
385 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
386 unsigned long flags;
387 u32 tmp;
388
389 if (fixup->base == NULL)
390 return;
391
392 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
393
394 /* Disable */
395 spin_lock_irqsave(&mpic->fixup_lock, flags);
396 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
397 tmp = readl(fixup->base + 4);
398 tmp |= 1;
399 writel(tmp, fixup->base + 4);
400 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
401
402 #ifdef CONFIG_PM
403 /* use the lowest bit inverted to the actual HW,
404 * set if this fixup was enabled, clear otherwise */
405 mpic->save_data[source].fixup_data = tmp & ~1;
406 #endif
407 }
408
409 #ifdef CONFIG_PCI_MSI
410 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
411 unsigned int devfn)
412 {
413 u8 __iomem *base;
414 u8 pos, flags;
415 u64 addr = 0;
416
417 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
418 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
419 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
420 if (id == PCI_CAP_ID_HT) {
421 id = readb(devbase + pos + 3);
422 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
423 break;
424 }
425 }
426
427 if (pos == 0)
428 return;
429
430 base = devbase + pos;
431
432 flags = readb(base + HT_MSI_FLAGS);
433 if (!(flags & HT_MSI_FLAGS_FIXED)) {
434 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
435 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
436 }
437
438 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
439 PCI_SLOT(devfn), PCI_FUNC(devfn),
440 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
441
442 if (!(flags & HT_MSI_FLAGS_ENABLE))
443 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
444 }
445 #else
446 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
447 unsigned int devfn)
448 {
449 return;
450 }
451 #endif
452
453 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
454 unsigned int devfn, u32 vdid)
455 {
456 int i, irq, n;
457 u8 __iomem *base;
458 u32 tmp;
459 u8 pos;
460
461 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
462 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
463 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
464 if (id == PCI_CAP_ID_HT) {
465 id = readb(devbase + pos + 3);
466 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
467 break;
468 }
469 }
470 if (pos == 0)
471 return;
472
473 base = devbase + pos;
474 writeb(0x01, base + 2);
475 n = (readl(base + 4) >> 16) & 0xff;
476
477 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
478 " has %d irqs\n",
479 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
480
481 for (i = 0; i <= n; i++) {
482 writeb(0x10 + 2 * i, base + 2);
483 tmp = readl(base + 4);
484 irq = (tmp >> 16) & 0xff;
485 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
486 /* mask it , will be unmasked later */
487 tmp |= 0x1;
488 writel(tmp, base + 4);
489 mpic->fixups[irq].index = i;
490 mpic->fixups[irq].base = base;
491 /* Apple HT PIC has a non-standard way of doing EOIs */
492 if ((vdid & 0xffff) == 0x106b)
493 mpic->fixups[irq].applebase = devbase + 0x60;
494 else
495 mpic->fixups[irq].applebase = NULL;
496 writeb(0x11 + 2 * i, base + 2);
497 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
498 }
499 }
500
501
502 static void __init mpic_scan_ht_pics(struct mpic *mpic)
503 {
504 unsigned int devfn;
505 u8 __iomem *cfgspace;
506
507 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
508
509 /* Allocate fixups array */
510 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
511 BUG_ON(mpic->fixups == NULL);
512 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
513
514 /* Init spinlock */
515 spin_lock_init(&mpic->fixup_lock);
516
517 /* Map U3 config space. We assume all IO-APICs are on the primary bus
518 * so we only need to map 64kB.
519 */
520 cfgspace = ioremap(0xf2000000, 0x10000);
521 BUG_ON(cfgspace == NULL);
522
523 /* Now we scan all slots. We do a very quick scan, we read the header
524 * type, vendor ID and device ID only, that's plenty enough
525 */
526 for (devfn = 0; devfn < 0x100; devfn++) {
527 u8 __iomem *devbase = cfgspace + (devfn << 8);
528 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
529 u32 l = readl(devbase + PCI_VENDOR_ID);
530 u16 s;
531
532 DBG("devfn %x, l: %x\n", devfn, l);
533
534 /* If no device, skip */
535 if (l == 0xffffffff || l == 0x00000000 ||
536 l == 0x0000ffff || l == 0xffff0000)
537 goto next;
538 /* Check if is supports capability lists */
539 s = readw(devbase + PCI_STATUS);
540 if (!(s & PCI_STATUS_CAP_LIST))
541 goto next;
542
543 mpic_scan_ht_pic(mpic, devbase, devfn, l);
544 mpic_scan_ht_msi(mpic, devbase, devfn);
545
546 next:
547 /* next device, if function 0 */
548 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
549 devfn += 7;
550 }
551 }
552
553 #else /* CONFIG_MPIC_U3_HT_IRQS */
554
555 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
556 {
557 return 0;
558 }
559
560 static void __init mpic_scan_ht_pics(struct mpic *mpic)
561 {
562 }
563
564 #endif /* CONFIG_MPIC_U3_HT_IRQS */
565
566 #ifdef CONFIG_SMP
567 static int irq_choose_cpu(unsigned int virt_irq)
568 {
569 cpumask_t mask = irq_desc[virt_irq].affinity;
570 int cpuid;
571
572 if (cpus_equal(mask, CPU_MASK_ALL)) {
573 static int irq_rover;
574 static DEFINE_SPINLOCK(irq_rover_lock);
575 unsigned long flags;
576
577 /* Round-robin distribution... */
578 do_round_robin:
579 spin_lock_irqsave(&irq_rover_lock, flags);
580
581 while (!cpu_online(irq_rover)) {
582 if (++irq_rover >= NR_CPUS)
583 irq_rover = 0;
584 }
585 cpuid = irq_rover;
586 do {
587 if (++irq_rover >= NR_CPUS)
588 irq_rover = 0;
589 } while (!cpu_online(irq_rover));
590
591 spin_unlock_irqrestore(&irq_rover_lock, flags);
592 } else {
593 cpumask_t tmp;
594
595 cpus_and(tmp, cpu_online_map, mask);
596
597 if (cpus_empty(tmp))
598 goto do_round_robin;
599
600 cpuid = first_cpu(tmp);
601 }
602
603 return cpuid;
604 }
605 #else
606 static int irq_choose_cpu(unsigned int virt_irq)
607 {
608 return hard_smp_processor_id();
609 }
610 #endif
611
612 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
613
614 /* Find an mpic associated with a given linux interrupt */
615 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
616 {
617 unsigned int src = mpic_irq_to_hw(irq);
618 struct mpic *mpic;
619
620 if (irq < NUM_ISA_INTERRUPTS)
621 return NULL;
622
623 mpic = irq_desc[irq].chip_data;
624
625 if (is_ipi)
626 *is_ipi = (src >= mpic->ipi_vecs[0] &&
627 src <= mpic->ipi_vecs[3]);
628
629 return mpic;
630 }
631
632 /* Convert a cpu mask from logical to physical cpu numbers. */
633 static inline u32 mpic_physmask(u32 cpumask)
634 {
635 int i;
636 u32 mask = 0;
637
638 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
639 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
640 return mask;
641 }
642
643 #ifdef CONFIG_SMP
644 /* Get the mpic structure from the IPI number */
645 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
646 {
647 return irq_desc[ipi].chip_data;
648 }
649 #endif
650
651 /* Get the mpic structure from the irq number */
652 static inline struct mpic * mpic_from_irq(unsigned int irq)
653 {
654 return irq_desc[irq].chip_data;
655 }
656
657 /* Send an EOI */
658 static inline void mpic_eoi(struct mpic *mpic)
659 {
660 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
661 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
662 }
663
664 #ifdef CONFIG_SMP
665 static irqreturn_t mpic_ipi_action(int irq, void *data)
666 {
667 long ipi = (long)data;
668
669 smp_message_recv(ipi);
670
671 return IRQ_HANDLED;
672 }
673 #endif /* CONFIG_SMP */
674
675 /*
676 * Linux descriptor level callbacks
677 */
678
679
680 void mpic_unmask_irq(unsigned int irq)
681 {
682 unsigned int loops = 100000;
683 struct mpic *mpic = mpic_from_irq(irq);
684 unsigned int src = mpic_irq_to_hw(irq);
685
686 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
687
688 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
689 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
690 ~MPIC_VECPRI_MASK);
691 /* make sure mask gets to controller before we return to user */
692 do {
693 if (!loops--) {
694 printk(KERN_ERR "mpic_enable_irq timeout\n");
695 break;
696 }
697 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
698 }
699
700 void mpic_mask_irq(unsigned int irq)
701 {
702 unsigned int loops = 100000;
703 struct mpic *mpic = mpic_from_irq(irq);
704 unsigned int src = mpic_irq_to_hw(irq);
705
706 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
707
708 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
709 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
710 MPIC_VECPRI_MASK);
711
712 /* make sure mask gets to controller before we return to user */
713 do {
714 if (!loops--) {
715 printk(KERN_ERR "mpic_enable_irq timeout\n");
716 break;
717 }
718 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
719 }
720
721 void mpic_end_irq(unsigned int irq)
722 {
723 struct mpic *mpic = mpic_from_irq(irq);
724
725 #ifdef DEBUG_IRQ
726 DBG("%s: end_irq: %d\n", mpic->name, irq);
727 #endif
728 /* We always EOI on end_irq() even for edge interrupts since that
729 * should only lower the priority, the MPIC should have properly
730 * latched another edge interrupt coming in anyway
731 */
732
733 mpic_eoi(mpic);
734 }
735
736 #ifdef CONFIG_MPIC_U3_HT_IRQS
737
738 static void mpic_unmask_ht_irq(unsigned int irq)
739 {
740 struct mpic *mpic = mpic_from_irq(irq);
741 unsigned int src = mpic_irq_to_hw(irq);
742
743 mpic_unmask_irq(irq);
744
745 if (irq_desc[irq].status & IRQ_LEVEL)
746 mpic_ht_end_irq(mpic, src);
747 }
748
749 static unsigned int mpic_startup_ht_irq(unsigned int irq)
750 {
751 struct mpic *mpic = mpic_from_irq(irq);
752 unsigned int src = mpic_irq_to_hw(irq);
753
754 mpic_unmask_irq(irq);
755 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
756
757 return 0;
758 }
759
760 static void mpic_shutdown_ht_irq(unsigned int irq)
761 {
762 struct mpic *mpic = mpic_from_irq(irq);
763 unsigned int src = mpic_irq_to_hw(irq);
764
765 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
766 mpic_mask_irq(irq);
767 }
768
769 static void mpic_end_ht_irq(unsigned int irq)
770 {
771 struct mpic *mpic = mpic_from_irq(irq);
772 unsigned int src = mpic_irq_to_hw(irq);
773
774 #ifdef DEBUG_IRQ
775 DBG("%s: end_irq: %d\n", mpic->name, irq);
776 #endif
777 /* We always EOI on end_irq() even for edge interrupts since that
778 * should only lower the priority, the MPIC should have properly
779 * latched another edge interrupt coming in anyway
780 */
781
782 if (irq_desc[irq].status & IRQ_LEVEL)
783 mpic_ht_end_irq(mpic, src);
784 mpic_eoi(mpic);
785 }
786 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
787
788 #ifdef CONFIG_SMP
789
790 static void mpic_unmask_ipi(unsigned int irq)
791 {
792 struct mpic *mpic = mpic_from_ipi(irq);
793 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
794
795 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
796 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
797 }
798
799 static void mpic_mask_ipi(unsigned int irq)
800 {
801 /* NEVER disable an IPI... that's just plain wrong! */
802 }
803
804 static void mpic_end_ipi(unsigned int irq)
805 {
806 struct mpic *mpic = mpic_from_ipi(irq);
807
808 /*
809 * IPIs are marked IRQ_PER_CPU. This has the side effect of
810 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
811 * applying to them. We EOI them late to avoid re-entering.
812 * We mark IPI's with IRQF_DISABLED as they must run with
813 * irqs disabled.
814 */
815 mpic_eoi(mpic);
816 }
817
818 #endif /* CONFIG_SMP */
819
820 void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
821 {
822 struct mpic *mpic = mpic_from_irq(irq);
823 unsigned int src = mpic_irq_to_hw(irq);
824
825 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
826 int cpuid = irq_choose_cpu(irq);
827
828 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
829 } else {
830 cpumask_t tmp;
831
832 cpus_and(tmp, cpumask, cpu_online_map);
833
834 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
835 mpic_physmask(cpus_addr(tmp)[0]));
836 }
837 }
838
839 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
840 {
841 /* Now convert sense value */
842 switch(type & IRQ_TYPE_SENSE_MASK) {
843 case IRQ_TYPE_EDGE_RISING:
844 return MPIC_INFO(VECPRI_SENSE_EDGE) |
845 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
846 case IRQ_TYPE_EDGE_FALLING:
847 case IRQ_TYPE_EDGE_BOTH:
848 return MPIC_INFO(VECPRI_SENSE_EDGE) |
849 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
850 case IRQ_TYPE_LEVEL_HIGH:
851 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
852 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
853 case IRQ_TYPE_LEVEL_LOW:
854 default:
855 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
856 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
857 }
858 }
859
860 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
861 {
862 struct mpic *mpic = mpic_from_irq(virq);
863 unsigned int src = mpic_irq_to_hw(virq);
864 struct irq_desc *desc = get_irq_desc(virq);
865 unsigned int vecpri, vold, vnew;
866
867 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
868 mpic, virq, src, flow_type);
869
870 if (src >= mpic->irq_count)
871 return -EINVAL;
872
873 if (flow_type == IRQ_TYPE_NONE)
874 if (mpic->senses && src < mpic->senses_count)
875 flow_type = mpic->senses[src];
876 if (flow_type == IRQ_TYPE_NONE)
877 flow_type = IRQ_TYPE_LEVEL_LOW;
878
879 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
880 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
881 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
882 desc->status |= IRQ_LEVEL;
883
884 if (mpic_is_ht_interrupt(mpic, src))
885 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
886 MPIC_VECPRI_SENSE_EDGE;
887 else
888 vecpri = mpic_type_to_vecpri(mpic, flow_type);
889
890 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
891 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
892 MPIC_INFO(VECPRI_SENSE_MASK));
893 vnew |= vecpri;
894 if (vold != vnew)
895 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
896
897 return 0;
898 }
899
900 void mpic_set_vector(unsigned int virq, unsigned int vector)
901 {
902 struct mpic *mpic = mpic_from_irq(virq);
903 unsigned int src = mpic_irq_to_hw(virq);
904 unsigned int vecpri;
905
906 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
907 mpic, virq, src, vector);
908
909 if (src >= mpic->irq_count)
910 return;
911
912 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
913 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
914 vecpri |= vector;
915 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
916 }
917
918 static struct irq_chip mpic_irq_chip = {
919 .mask = mpic_mask_irq,
920 .unmask = mpic_unmask_irq,
921 .eoi = mpic_end_irq,
922 .set_type = mpic_set_irq_type,
923 };
924
925 #ifdef CONFIG_SMP
926 static struct irq_chip mpic_ipi_chip = {
927 .mask = mpic_mask_ipi,
928 .unmask = mpic_unmask_ipi,
929 .eoi = mpic_end_ipi,
930 };
931 #endif /* CONFIG_SMP */
932
933 #ifdef CONFIG_MPIC_U3_HT_IRQS
934 static struct irq_chip mpic_irq_ht_chip = {
935 .startup = mpic_startup_ht_irq,
936 .shutdown = mpic_shutdown_ht_irq,
937 .mask = mpic_mask_irq,
938 .unmask = mpic_unmask_ht_irq,
939 .eoi = mpic_end_ht_irq,
940 .set_type = mpic_set_irq_type,
941 };
942 #endif /* CONFIG_MPIC_U3_HT_IRQS */
943
944
945 static int mpic_host_match(struct irq_host *h, struct device_node *node)
946 {
947 /* Exact match, unless mpic node is NULL */
948 return h->of_node == NULL || h->of_node == node;
949 }
950
951 static int mpic_host_map(struct irq_host *h, unsigned int virq,
952 irq_hw_number_t hw)
953 {
954 struct mpic *mpic = h->host_data;
955 struct irq_chip *chip;
956
957 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
958
959 if (hw == mpic->spurious_vec)
960 return -EINVAL;
961 if (mpic->protected && test_bit(hw, mpic->protected))
962 return -EINVAL;
963
964 #ifdef CONFIG_SMP
965 else if (hw >= mpic->ipi_vecs[0]) {
966 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
967
968 DBG("mpic: mapping as IPI\n");
969 set_irq_chip_data(virq, mpic);
970 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
971 handle_percpu_irq);
972 return 0;
973 }
974 #endif /* CONFIG_SMP */
975
976 if (hw >= mpic->irq_count)
977 return -EINVAL;
978
979 mpic_msi_reserve_hwirq(mpic, hw);
980
981 /* Default chip */
982 chip = &mpic->hc_irq;
983
984 #ifdef CONFIG_MPIC_U3_HT_IRQS
985 /* Check for HT interrupts, override vecpri */
986 if (mpic_is_ht_interrupt(mpic, hw))
987 chip = &mpic->hc_ht_irq;
988 #endif /* CONFIG_MPIC_U3_HT_IRQS */
989
990 DBG("mpic: mapping to irq chip @%p\n", chip);
991
992 set_irq_chip_data(virq, mpic);
993 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
994
995 /* Set default irq type */
996 set_irq_type(virq, IRQ_TYPE_NONE);
997
998 return 0;
999 }
1000
1001 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1002 u32 *intspec, unsigned int intsize,
1003 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1004
1005 {
1006 static unsigned char map_mpic_senses[4] = {
1007 IRQ_TYPE_EDGE_RISING,
1008 IRQ_TYPE_LEVEL_LOW,
1009 IRQ_TYPE_LEVEL_HIGH,
1010 IRQ_TYPE_EDGE_FALLING,
1011 };
1012
1013 *out_hwirq = intspec[0];
1014 if (intsize > 1) {
1015 u32 mask = 0x3;
1016
1017 /* Apple invented a new race of encoding on machines with
1018 * an HT APIC. They encode, among others, the index within
1019 * the HT APIC. We don't care about it here since thankfully,
1020 * it appears that they have the APIC already properly
1021 * configured, and thus our current fixup code that reads the
1022 * APIC config works fine. However, we still need to mask out
1023 * bits in the specifier to make sure we only get bit 0 which
1024 * is the level/edge bit (the only sense bit exposed by Apple),
1025 * as their bit 1 means something else.
1026 */
1027 if (machine_is(powermac))
1028 mask = 0x1;
1029 *out_flags = map_mpic_senses[intspec[1] & mask];
1030 } else
1031 *out_flags = IRQ_TYPE_NONE;
1032
1033 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1034 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1035
1036 return 0;
1037 }
1038
1039 static struct irq_host_ops mpic_host_ops = {
1040 .match = mpic_host_match,
1041 .map = mpic_host_map,
1042 .xlate = mpic_host_xlate,
1043 };
1044
1045 /*
1046 * Exported functions
1047 */
1048
1049 struct mpic * __init mpic_alloc(struct device_node *node,
1050 phys_addr_t phys_addr,
1051 unsigned int flags,
1052 unsigned int isu_size,
1053 unsigned int irq_count,
1054 const char *name)
1055 {
1056 struct mpic *mpic;
1057 u32 greg_feature;
1058 const char *vers;
1059 int i;
1060 int intvec_top;
1061 u64 paddr = phys_addr;
1062
1063 mpic = alloc_bootmem(sizeof(struct mpic));
1064 if (mpic == NULL)
1065 return NULL;
1066
1067 memset(mpic, 0, sizeof(struct mpic));
1068 mpic->name = name;
1069
1070 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1071 isu_size, &mpic_host_ops,
1072 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1073 if (mpic->irqhost == NULL)
1074 return NULL;
1075
1076 mpic->irqhost->host_data = mpic;
1077 mpic->hc_irq = mpic_irq_chip;
1078 mpic->hc_irq.typename = name;
1079 if (flags & MPIC_PRIMARY)
1080 mpic->hc_irq.set_affinity = mpic_set_affinity;
1081 #ifdef CONFIG_MPIC_U3_HT_IRQS
1082 mpic->hc_ht_irq = mpic_irq_ht_chip;
1083 mpic->hc_ht_irq.typename = name;
1084 if (flags & MPIC_PRIMARY)
1085 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1086 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1087
1088 #ifdef CONFIG_SMP
1089 mpic->hc_ipi = mpic_ipi_chip;
1090 mpic->hc_ipi.typename = name;
1091 #endif /* CONFIG_SMP */
1092
1093 mpic->flags = flags;
1094 mpic->isu_size = isu_size;
1095 mpic->irq_count = irq_count;
1096 mpic->num_sources = 0; /* so far */
1097
1098 if (flags & MPIC_LARGE_VECTORS)
1099 intvec_top = 2047;
1100 else
1101 intvec_top = 255;
1102
1103 mpic->timer_vecs[0] = intvec_top - 8;
1104 mpic->timer_vecs[1] = intvec_top - 7;
1105 mpic->timer_vecs[2] = intvec_top - 6;
1106 mpic->timer_vecs[3] = intvec_top - 5;
1107 mpic->ipi_vecs[0] = intvec_top - 4;
1108 mpic->ipi_vecs[1] = intvec_top - 3;
1109 mpic->ipi_vecs[2] = intvec_top - 2;
1110 mpic->ipi_vecs[3] = intvec_top - 1;
1111 mpic->spurious_vec = intvec_top;
1112
1113 /* Check for "big-endian" in device-tree */
1114 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1115 mpic->flags |= MPIC_BIG_ENDIAN;
1116
1117 /* Look for protected sources */
1118 if (node) {
1119 int psize;
1120 unsigned int bits, mapsize;
1121 const u32 *psrc =
1122 of_get_property(node, "protected-sources", &psize);
1123 if (psrc) {
1124 psize /= 4;
1125 bits = intvec_top + 1;
1126 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1127 mpic->protected = alloc_bootmem(mapsize);
1128 BUG_ON(mpic->protected == NULL);
1129 memset(mpic->protected, 0, mapsize);
1130 for (i = 0; i < psize; i++) {
1131 if (psrc[i] > intvec_top)
1132 continue;
1133 __set_bit(psrc[i], mpic->protected);
1134 }
1135 }
1136 }
1137
1138 #ifdef CONFIG_MPIC_WEIRD
1139 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1140 #endif
1141
1142 /* default register type */
1143 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1144 mpic_access_mmio_be : mpic_access_mmio_le;
1145
1146 /* If no physical address is passed in, a device-node is mandatory */
1147 BUG_ON(paddr == 0 && node == NULL);
1148
1149 /* If no physical address passed in, check if it's dcr based */
1150 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1151 #ifdef CONFIG_PPC_DCR
1152 mpic->flags |= MPIC_USES_DCR;
1153 mpic->reg_type = mpic_access_dcr;
1154 #else
1155 BUG();
1156 #endif /* CONFIG_PPC_DCR */
1157 }
1158
1159 /* If the MPIC is not DCR based, and no physical address was passed
1160 * in, try to obtain one
1161 */
1162 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1163 const u32 *reg = of_get_property(node, "reg", NULL);
1164 BUG_ON(reg == NULL);
1165 paddr = of_translate_address(node, reg);
1166 BUG_ON(paddr == OF_BAD_ADDR);
1167 }
1168
1169 /* Map the global registers */
1170 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1171 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1172
1173 /* Reset */
1174 if (flags & MPIC_WANTS_RESET) {
1175 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1176 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1177 | MPIC_GREG_GCONF_RESET);
1178 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1179 & MPIC_GREG_GCONF_RESET)
1180 mb();
1181 }
1182
1183 if (flags & MPIC_ENABLE_MCK)
1184 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1185 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1186 | MPIC_GREG_GCONF_MCK);
1187
1188 /* Read feature register, calculate num CPUs and, for non-ISU
1189 * MPICs, num sources as well. On ISU MPICs, sources are counted
1190 * as ISUs are added
1191 */
1192 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1193 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1194 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1195 if (isu_size == 0) {
1196 if (flags & MPIC_BROKEN_FRR_NIRQS)
1197 mpic->num_sources = mpic->irq_count;
1198 else
1199 mpic->num_sources =
1200 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1201 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1202 }
1203
1204 /* Map the per-CPU registers */
1205 for (i = 0; i < mpic->num_cpus; i++) {
1206 mpic_map(mpic, paddr, &mpic->cpuregs[i],
1207 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1208 0x1000);
1209 }
1210
1211 /* Initialize main ISU if none provided */
1212 if (mpic->isu_size == 0) {
1213 mpic->isu_size = mpic->num_sources;
1214 mpic_map(mpic, paddr, &mpic->isus[0],
1215 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1216 }
1217 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1218 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1219
1220 /* Display version */
1221 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1222 case 1:
1223 vers = "1.0";
1224 break;
1225 case 2:
1226 vers = "1.2";
1227 break;
1228 case 3:
1229 vers = "1.3";
1230 break;
1231 default:
1232 vers = "<unknown>";
1233 break;
1234 }
1235 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1236 " max %d CPUs\n",
1237 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1238 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1239 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1240
1241 mpic->next = mpics;
1242 mpics = mpic;
1243
1244 if (flags & MPIC_PRIMARY) {
1245 mpic_primary = mpic;
1246 irq_set_default_host(mpic->irqhost);
1247 }
1248
1249 return mpic;
1250 }
1251
1252 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1253 phys_addr_t paddr)
1254 {
1255 unsigned int isu_first = isu_num * mpic->isu_size;
1256
1257 BUG_ON(isu_num >= MPIC_MAX_ISU);
1258
1259 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1260 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1261 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1262 mpic->num_sources = isu_first + mpic->isu_size;
1263 }
1264
1265 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1266 {
1267 mpic->senses = senses;
1268 mpic->senses_count = count;
1269 }
1270
1271 void __init mpic_init(struct mpic *mpic)
1272 {
1273 int i;
1274
1275 BUG_ON(mpic->num_sources == 0);
1276
1277 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1278
1279 /* Set current processor priority to max */
1280 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1281
1282 /* Initialize timers: just disable them all */
1283 for (i = 0; i < 4; i++) {
1284 mpic_write(mpic->tmregs,
1285 i * MPIC_INFO(TIMER_STRIDE) +
1286 MPIC_INFO(TIMER_DESTINATION), 0);
1287 mpic_write(mpic->tmregs,
1288 i * MPIC_INFO(TIMER_STRIDE) +
1289 MPIC_INFO(TIMER_VECTOR_PRI),
1290 MPIC_VECPRI_MASK |
1291 (mpic->timer_vecs[0] + i));
1292 }
1293
1294 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1295 mpic_test_broken_ipi(mpic);
1296 for (i = 0; i < 4; i++) {
1297 mpic_ipi_write(i,
1298 MPIC_VECPRI_MASK |
1299 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1300 (mpic->ipi_vecs[0] + i));
1301 }
1302
1303 /* Initialize interrupt sources */
1304 if (mpic->irq_count == 0)
1305 mpic->irq_count = mpic->num_sources;
1306
1307 /* Do the HT PIC fixups on U3 broken mpic */
1308 DBG("MPIC flags: %x\n", mpic->flags);
1309 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1310 mpic_scan_ht_pics(mpic);
1311 mpic_u3msi_init(mpic);
1312 }
1313
1314 mpic_pasemi_msi_init(mpic);
1315
1316 for (i = 0; i < mpic->num_sources; i++) {
1317 /* start with vector = source number, and masked */
1318 u32 vecpri = MPIC_VECPRI_MASK | i |
1319 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1320
1321 /* check if protected */
1322 if (mpic->protected && test_bit(i, mpic->protected))
1323 continue;
1324 /* init hw */
1325 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1326 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1327 1 << hard_smp_processor_id());
1328 }
1329
1330 /* Init spurious vector */
1331 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1332
1333 /* Disable 8259 passthrough, if supported */
1334 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1335 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1336 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1337 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1338
1339 if (mpic->flags & MPIC_NO_BIAS)
1340 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1341 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1342 | MPIC_GREG_GCONF_NO_BIAS);
1343
1344 /* Set current processor priority to 0 */
1345 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1346
1347 #ifdef CONFIG_PM
1348 /* allocate memory to save mpic state */
1349 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1350 BUG_ON(mpic->save_data == NULL);
1351 #endif
1352 }
1353
1354 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1355 {
1356 u32 v;
1357
1358 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1359 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1360 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1361 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1362 }
1363
1364 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1365 {
1366 unsigned long flags;
1367 u32 v;
1368
1369 spin_lock_irqsave(&mpic_lock, flags);
1370 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1371 if (enable)
1372 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1373 else
1374 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1375 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1376 spin_unlock_irqrestore(&mpic_lock, flags);
1377 }
1378
1379 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1380 {
1381 unsigned int is_ipi;
1382 struct mpic *mpic = mpic_find(irq, &is_ipi);
1383 unsigned int src = mpic_irq_to_hw(irq);
1384 unsigned long flags;
1385 u32 reg;
1386
1387 if (!mpic)
1388 return;
1389
1390 spin_lock_irqsave(&mpic_lock, flags);
1391 if (is_ipi) {
1392 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1393 ~MPIC_VECPRI_PRIORITY_MASK;
1394 mpic_ipi_write(src - mpic->ipi_vecs[0],
1395 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1396 } else {
1397 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1398 & ~MPIC_VECPRI_PRIORITY_MASK;
1399 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1400 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1401 }
1402 spin_unlock_irqrestore(&mpic_lock, flags);
1403 }
1404
1405 void mpic_setup_this_cpu(void)
1406 {
1407 #ifdef CONFIG_SMP
1408 struct mpic *mpic = mpic_primary;
1409 unsigned long flags;
1410 u32 msk = 1 << hard_smp_processor_id();
1411 unsigned int i;
1412
1413 BUG_ON(mpic == NULL);
1414
1415 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1416
1417 spin_lock_irqsave(&mpic_lock, flags);
1418
1419 /* let the mpic know we want intrs. default affinity is 0xffffffff
1420 * until changed via /proc. That's how it's done on x86. If we want
1421 * it differently, then we should make sure we also change the default
1422 * values of irq_desc[].affinity in irq.c.
1423 */
1424 if (distribute_irqs) {
1425 for (i = 0; i < mpic->num_sources ; i++)
1426 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1427 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1428 }
1429
1430 /* Set current processor priority to 0 */
1431 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1432
1433 spin_unlock_irqrestore(&mpic_lock, flags);
1434 #endif /* CONFIG_SMP */
1435 }
1436
1437 int mpic_cpu_get_priority(void)
1438 {
1439 struct mpic *mpic = mpic_primary;
1440
1441 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1442 }
1443
1444 void mpic_cpu_set_priority(int prio)
1445 {
1446 struct mpic *mpic = mpic_primary;
1447
1448 prio &= MPIC_CPU_TASKPRI_MASK;
1449 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1450 }
1451
1452 void mpic_teardown_this_cpu(int secondary)
1453 {
1454 struct mpic *mpic = mpic_primary;
1455 unsigned long flags;
1456 u32 msk = 1 << hard_smp_processor_id();
1457 unsigned int i;
1458
1459 BUG_ON(mpic == NULL);
1460
1461 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1462 spin_lock_irqsave(&mpic_lock, flags);
1463
1464 /* let the mpic know we don't want intrs. */
1465 for (i = 0; i < mpic->num_sources ; i++)
1466 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1467 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1468
1469 /* Set current processor priority to max */
1470 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1471 /* We need to EOI the IPI since not all platforms reset the MPIC
1472 * on boot and new interrupts wouldn't get delivered otherwise.
1473 */
1474 mpic_eoi(mpic);
1475
1476 spin_unlock_irqrestore(&mpic_lock, flags);
1477 }
1478
1479
1480 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1481 {
1482 struct mpic *mpic = mpic_primary;
1483
1484 BUG_ON(mpic == NULL);
1485
1486 #ifdef DEBUG_IPI
1487 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1488 #endif
1489
1490 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1491 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1492 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1493 }
1494
1495 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1496 {
1497 u32 src;
1498
1499 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1500 #ifdef DEBUG_LOW
1501 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1502 #endif
1503 if (unlikely(src == mpic->spurious_vec)) {
1504 if (mpic->flags & MPIC_SPV_EOI)
1505 mpic_eoi(mpic);
1506 return NO_IRQ;
1507 }
1508 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1509 if (printk_ratelimit())
1510 printk(KERN_WARNING "%s: Got protected source %d !\n",
1511 mpic->name, (int)src);
1512 mpic_eoi(mpic);
1513 return NO_IRQ;
1514 }
1515
1516 return irq_linear_revmap(mpic->irqhost, src);
1517 }
1518
1519 unsigned int mpic_get_one_irq(struct mpic *mpic)
1520 {
1521 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1522 }
1523
1524 unsigned int mpic_get_irq(void)
1525 {
1526 struct mpic *mpic = mpic_primary;
1527
1528 BUG_ON(mpic == NULL);
1529
1530 return mpic_get_one_irq(mpic);
1531 }
1532
1533 unsigned int mpic_get_mcirq(void)
1534 {
1535 struct mpic *mpic = mpic_primary;
1536
1537 BUG_ON(mpic == NULL);
1538
1539 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1540 }
1541
1542 #ifdef CONFIG_SMP
1543 void mpic_request_ipis(void)
1544 {
1545 struct mpic *mpic = mpic_primary;
1546 long i, err;
1547 static char *ipi_names[] = {
1548 "IPI0 (call function)",
1549 "IPI1 (reschedule)",
1550 "IPI2 (call function single)",
1551 "IPI3 (debugger break)",
1552 };
1553 BUG_ON(mpic == NULL);
1554
1555 printk(KERN_INFO "mpic: requesting IPIs ... \n");
1556
1557 for (i = 0; i < 4; i++) {
1558 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1559 mpic->ipi_vecs[0] + i);
1560 if (vipi == NO_IRQ) {
1561 printk(KERN_ERR "Failed to map IPI %ld\n", i);
1562 break;
1563 }
1564 err = request_irq(vipi, mpic_ipi_action,
1565 IRQF_DISABLED|IRQF_PERCPU,
1566 ipi_names[i], (void *)i);
1567 if (err) {
1568 printk(KERN_ERR "Request of irq %d for IPI %ld failed\n",
1569 vipi, i);
1570 break;
1571 }
1572 }
1573 }
1574
1575 void smp_mpic_message_pass(int target, int msg)
1576 {
1577 /* make sure we're sending something that translates to an IPI */
1578 if ((unsigned int)msg > 3) {
1579 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1580 smp_processor_id(), msg);
1581 return;
1582 }
1583 switch (target) {
1584 case MSG_ALL:
1585 mpic_send_ipi(msg, 0xffffffff);
1586 break;
1587 case MSG_ALL_BUT_SELF:
1588 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1589 break;
1590 default:
1591 mpic_send_ipi(msg, 1 << target);
1592 break;
1593 }
1594 }
1595
1596 int __init smp_mpic_probe(void)
1597 {
1598 int nr_cpus;
1599
1600 DBG("smp_mpic_probe()...\n");
1601
1602 nr_cpus = cpus_weight(cpu_possible_map);
1603
1604 DBG("nr_cpus: %d\n", nr_cpus);
1605
1606 if (nr_cpus > 1)
1607 mpic_request_ipis();
1608
1609 return nr_cpus;
1610 }
1611
1612 void __devinit smp_mpic_setup_cpu(int cpu)
1613 {
1614 mpic_setup_this_cpu();
1615 }
1616 #endif /* CONFIG_SMP */
1617
1618 #ifdef CONFIG_PM
1619 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1620 {
1621 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1622 int i;
1623
1624 for (i = 0; i < mpic->num_sources; i++) {
1625 mpic->save_data[i].vecprio =
1626 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1627 mpic->save_data[i].dest =
1628 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1629 }
1630
1631 return 0;
1632 }
1633
1634 static int mpic_resume(struct sys_device *dev)
1635 {
1636 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1637 int i;
1638
1639 for (i = 0; i < mpic->num_sources; i++) {
1640 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1641 mpic->save_data[i].vecprio);
1642 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1643 mpic->save_data[i].dest);
1644
1645 #ifdef CONFIG_MPIC_U3_HT_IRQS
1646 {
1647 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1648
1649 if (fixup->base) {
1650 /* we use the lowest bit in an inverted meaning */
1651 if ((mpic->save_data[i].fixup_data & 1) == 0)
1652 continue;
1653
1654 /* Enable and configure */
1655 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1656
1657 writel(mpic->save_data[i].fixup_data & ~1,
1658 fixup->base + 4);
1659 }
1660 }
1661 #endif
1662 } /* end for loop */
1663
1664 return 0;
1665 }
1666 #endif
1667
1668 static struct sysdev_class mpic_sysclass = {
1669 #ifdef CONFIG_PM
1670 .resume = mpic_resume,
1671 .suspend = mpic_suspend,
1672 #endif
1673 .name = "mpic",
1674 };
1675
1676 static int mpic_init_sys(void)
1677 {
1678 struct mpic *mpic = mpics;
1679 int error, id = 0;
1680
1681 error = sysdev_class_register(&mpic_sysclass);
1682
1683 while (mpic && !error) {
1684 mpic->sysdev.cls = &mpic_sysclass;
1685 mpic->sysdev.id = id++;
1686 error = sysdev_register(&mpic->sysdev);
1687 mpic = mpic->next;
1688 }
1689 return error;
1690 }
1691
1692 device_initcall(mpic_init_sys);
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