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Linux 2.6.28-rc5
[cris-mirror.git] / arch / powerpc / sysdev / ppc4xx_pci.c
blobd3e4d61030b59039759ad4d4d2eaa9318e32abe0
1 /*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
17 */
18
19 #undef DEBUG
20
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
27
28 #include <asm/io.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
31 #include <asm/dcr.h>
32 #include <asm/dcr-regs.h>
33 #include <mm/mmu_decl.h>
34
35 #include "ppc4xx_pci.h"
36
37 static int dma_offset_set;
38
39 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
40 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
41
42 #define RES_TO_U32_LOW(val) \
43 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
44 #define RES_TO_U32_HIGH(val) \
45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
46
47 static inline int ppc440spe_revA(void)
48 {
49 /* Catch both 440SPe variants, with and without RAID6 support */
50 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
51 return 1;
52 else
53 return 0;
54 }
55
56 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
57 {
58 struct pci_controller *hose;
59 int i;
60
61 if (dev->devfn != 0 || dev->bus->self != NULL)
62 return;
63
64 hose = pci_bus_to_host(dev->bus);
65 if (hose == NULL)
66 return;
67
68 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
69 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
70 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
71 return;
72
73 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
74 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
75 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
76 }
77
78 /* Hide the PCI host BARs from the kernel as their content doesn't
79 * fit well in the resource management
80 */
81 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
82 dev->resource[i].start = dev->resource[i].end = 0;
83 dev->resource[i].flags = 0;
84 }
85
86 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
87 pci_name(dev));
88 }
89 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
90
91 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
92 void __iomem *reg,
93 struct resource *res)
94 {
95 u64 size;
96 const u32 *ranges;
97 int rlen;
98 int pna = of_n_addr_cells(hose->dn);
99 int np = pna + 5;
100
101 /* Default */
102 res->start = 0;
103 size = 0x80000000;
104 res->end = size - 1;
105 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
106
107 /* Get dma-ranges property */
108 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
109 if (ranges == NULL)
110 goto out;
111
112 /* Walk it */
113 while ((rlen -= np * 4) >= 0) {
114 u32 pci_space = ranges[0];
115 u64 pci_addr = of_read_number(ranges + 1, 2);
116 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
117 size = of_read_number(ranges + pna + 3, 2);
118 ranges += np;
119 if (cpu_addr == OF_BAD_ADDR || size == 0)
120 continue;
121
122 /* We only care about memory */
123 if ((pci_space & 0x03000000) != 0x02000000)
124 continue;
125
126 /* We currently only support memory at 0, and pci_addr
127 * within 32 bits space
128 */
129 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
130 printk(KERN_WARNING "%s: Ignored unsupported dma range"
131 " 0x%016llx...0x%016llx -> 0x%016llx\n",
132 hose->dn->full_name,
133 pci_addr, pci_addr + size - 1, cpu_addr);
134 continue;
135 }
136
137 /* Check if not prefetchable */
138 if (!(pci_space & 0x40000000))
139 res->flags &= ~IORESOURCE_PREFETCH;
140
141
142 /* Use that */
143 res->start = pci_addr;
144 /* Beware of 32 bits resources */
145 if (sizeof(resource_size_t) == sizeof(u32) &&
146 (pci_addr + size) > 0x100000000ull)
147 res->end = 0xffffffff;
148 else
149 res->end = res->start + size - 1;
150 break;
151 }
152
153 /* We only support one global DMA offset */
154 if (dma_offset_set && pci_dram_offset != res->start) {
155 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
156 hose->dn->full_name);
157 return -ENXIO;
158 }
159
160 /* Check that we can fit all of memory as we don't support
161 * DMA bounce buffers
162 */
163 if (size < total_memory) {
164 printk(KERN_ERR "%s: dma-ranges too small "
165 "(size=%llx total_memory=%llx)\n",
166 hose->dn->full_name, size, (u64)total_memory);
167 return -ENXIO;
168 }
169
170 /* Check we are a power of 2 size and that base is a multiple of size*/
171 if ((size & (size - 1)) != 0 ||
172 (res->start & (size - 1)) != 0) {
173 printk(KERN_ERR "%s: dma-ranges unaligned\n",
174 hose->dn->full_name);
175 return -ENXIO;
176 }
177
178 /* Check that we are fully contained within 32 bits space */
179 if (res->end > 0xffffffff) {
180 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
181 hose->dn->full_name);
182 return -ENXIO;
183 }
184 out:
185 dma_offset_set = 1;
186 pci_dram_offset = res->start;
187
188 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
189 pci_dram_offset);
190 return 0;
191 }
192
193 /*
194 * 4xx PCI 2.x part
195 */
196
197 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
198 void __iomem *reg)
199 {
200 u32 la, ma, pcila, pciha;
201 int i, j;
202
203 /* Setup outbound memory windows */
204 for (i = j = 0; i < 3; i++) {
205 struct resource *res = &hose->mem_resources[i];
206
207 /* we only care about memory windows */
208 if (!(res->flags & IORESOURCE_MEM))
209 continue;
210 if (j > 2) {
211 printk(KERN_WARNING "%s: Too many ranges\n",
212 hose->dn->full_name);
213 break;
214 }
215
216 /* Calculate register values */
217 la = res->start;
218 pciha = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
219 pcila = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
220
221 ma = res->end + 1 - res->start;
222 if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
223 printk(KERN_WARNING "%s: Resource out of range\n",
224 hose->dn->full_name);
225 continue;
226 }
227 ma = (0xffffffffu << ilog2(ma)) | 0x1;
228 if (res->flags & IORESOURCE_PREFETCH)
229 ma |= 0x2;
230
231 /* Program register values */
232 writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
233 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
234 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
235 writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
236 j++;
237 }
238 }
239
240 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
241 void __iomem *reg,
242 const struct resource *res)
243 {
244 resource_size_t size = res->end - res->start + 1;
245 u32 sa;
246
247 /* Calculate window size */
248 sa = (0xffffffffu << ilog2(size)) | 1;
249 sa |= 0x1;
250
251 /* RAM is always at 0 local for now */
252 writel(0, reg + PCIL0_PTM1LA);
253 writel(sa, reg + PCIL0_PTM1MS);
254
255 /* Map on PCI side */
256 early_write_config_dword(hose, hose->first_busno, 0,
257 PCI_BASE_ADDRESS_1, res->start);
258 early_write_config_dword(hose, hose->first_busno, 0,
259 PCI_BASE_ADDRESS_2, 0x00000000);
260 early_write_config_word(hose, hose->first_busno, 0,
261 PCI_COMMAND, 0x0006);
262 }
263
264 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
265 {
266 /* NYI */
267 struct resource rsrc_cfg;
268 struct resource rsrc_reg;
269 struct resource dma_window;
270 struct pci_controller *hose = NULL;
271 void __iomem *reg = NULL;
272 const int *bus_range;
273 int primary = 0;
274
275 /* Check if device is enabled */
276 if (!of_device_is_available(np)) {
277 printk(KERN_INFO "%s: Port disabled via device-tree\n",
278 np->full_name);
279 return;
280 }
281
282 /* Fetch config space registers address */
283 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
284 printk(KERN_ERR "%s: Can't get PCI config register base !",
285 np->full_name);
286 return;
287 }
288 /* Fetch host bridge internal registers address */
289 if (of_address_to_resource(np, 3, &rsrc_reg)) {
290 printk(KERN_ERR "%s: Can't get PCI internal register base !",
291 np->full_name);
292 return;
293 }
294
295 /* Check if primary bridge */
296 if (of_get_property(np, "primary", NULL))
297 primary = 1;
298
299 /* Get bus range if any */
300 bus_range = of_get_property(np, "bus-range", NULL);
301
302 /* Map registers */
303 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
304 if (reg == NULL) {
305 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
306 goto fail;
307 }
308
309 /* Allocate the host controller data structure */
310 hose = pcibios_alloc_controller(np);
311 if (!hose)
312 goto fail;
313
314 hose->first_busno = bus_range ? bus_range[0] : 0x0;
315 hose->last_busno = bus_range ? bus_range[1] : 0xff;
316
317 /* Setup config space */
318 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
319
320 /* Disable all windows */
321 writel(0, reg + PCIL0_PMM0MA);
322 writel(0, reg + PCIL0_PMM1MA);
323 writel(0, reg + PCIL0_PMM2MA);
324 writel(0, reg + PCIL0_PTM1MS);
325 writel(0, reg + PCIL0_PTM2MS);
326
327 /* Parse outbound mapping resources */
328 pci_process_bridge_OF_ranges(hose, np, primary);
329
330 /* Parse inbound mapping resources */
331 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
332 goto fail;
333
334 /* Configure outbound ranges POMs */
335 ppc4xx_configure_pci_PMMs(hose, reg);
336
337 /* Configure inbound ranges PIMs */
338 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
339
340 /* We don't need the registers anymore */
341 iounmap(reg);
342 return;
343
344 fail:
345 if (hose)
346 pcibios_free_controller(hose);
347 if (reg)
348 iounmap(reg);
349 }
350
351 /*
352 * 4xx PCI-X part
353 */
354
355 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
356 void __iomem *reg)
357 {
358 u32 lah, lal, pciah, pcial, sa;
359 int i, j;
360
361 /* Setup outbound memory windows */
362 for (i = j = 0; i < 3; i++) {
363 struct resource *res = &hose->mem_resources[i];
364
365 /* we only care about memory windows */
366 if (!(res->flags & IORESOURCE_MEM))
367 continue;
368 if (j > 1) {
369 printk(KERN_WARNING "%s: Too many ranges\n",
370 hose->dn->full_name);
371 break;
372 }
373
374 /* Calculate register values */
375 lah = RES_TO_U32_HIGH(res->start);
376 lal = RES_TO_U32_LOW(res->start);
377 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
378 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
379 sa = res->end + 1 - res->start;
380 if (!is_power_of_2(sa) || sa < 0x100000 ||
381 sa > 0xffffffffu) {
382 printk(KERN_WARNING "%s: Resource out of range\n",
383 hose->dn->full_name);
384 continue;
385 }
386 sa = (0xffffffffu << ilog2(sa)) | 0x1;
387
388 /* Program register values */
389 if (j == 0) {
390 writel(lah, reg + PCIX0_POM0LAH);
391 writel(lal, reg + PCIX0_POM0LAL);
392 writel(pciah, reg + PCIX0_POM0PCIAH);
393 writel(pcial, reg + PCIX0_POM0PCIAL);
394 writel(sa, reg + PCIX0_POM0SA);
395 } else {
396 writel(lah, reg + PCIX0_POM1LAH);
397 writel(lal, reg + PCIX0_POM1LAL);
398 writel(pciah, reg + PCIX0_POM1PCIAH);
399 writel(pcial, reg + PCIX0_POM1PCIAL);
400 writel(sa, reg + PCIX0_POM1SA);
401 }
402 j++;
403 }
404 }
405
406 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
407 void __iomem *reg,
408 const struct resource *res,
409 int big_pim,
410 int enable_msi_hole)
411 {
412 resource_size_t size = res->end - res->start + 1;
413 u32 sa;
414
415 /* RAM is always at 0 */
416 writel(0x00000000, reg + PCIX0_PIM0LAH);
417 writel(0x00000000, reg + PCIX0_PIM0LAL);
418
419 /* Calculate window size */
420 sa = (0xffffffffu << ilog2(size)) | 1;
421 sa |= 0x1;
422 if (res->flags & IORESOURCE_PREFETCH)
423 sa |= 0x2;
424 if (enable_msi_hole)
425 sa |= 0x4;
426 writel(sa, reg + PCIX0_PIM0SA);
427 if (big_pim)
428 writel(0xffffffff, reg + PCIX0_PIM0SAH);
429
430 /* Map on PCI side */
431 writel(0x00000000, reg + PCIX0_BAR0H);
432 writel(res->start, reg + PCIX0_BAR0L);
433 writew(0x0006, reg + PCIX0_COMMAND);
434 }
435
436 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
437 {
438 struct resource rsrc_cfg;
439 struct resource rsrc_reg;
440 struct resource dma_window;
441 struct pci_controller *hose = NULL;
442 void __iomem *reg = NULL;
443 const int *bus_range;
444 int big_pim = 0, msi = 0, primary = 0;
445
446 /* Fetch config space registers address */
447 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
448 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
449 np->full_name);
450 return;
451 }
452 /* Fetch host bridge internal registers address */
453 if (of_address_to_resource(np, 3, &rsrc_reg)) {
454 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
455 np->full_name);
456 return;
457 }
458
459 /* Check if it supports large PIMs (440GX) */
460 if (of_get_property(np, "large-inbound-windows", NULL))
461 big_pim = 1;
462
463 /* Check if we should enable MSIs inbound hole */
464 if (of_get_property(np, "enable-msi-hole", NULL))
465 msi = 1;
466
467 /* Check if primary bridge */
468 if (of_get_property(np, "primary", NULL))
469 primary = 1;
470
471 /* Get bus range if any */
472 bus_range = of_get_property(np, "bus-range", NULL);
473
474 /* Map registers */
475 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
476 if (reg == NULL) {
477 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
478 goto fail;
479 }
480
481 /* Allocate the host controller data structure */
482 hose = pcibios_alloc_controller(np);
483 if (!hose)
484 goto fail;
485
486 hose->first_busno = bus_range ? bus_range[0] : 0x0;
487 hose->last_busno = bus_range ? bus_range[1] : 0xff;
488
489 /* Setup config space */
490 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
491
492 /* Disable all windows */
493 writel(0, reg + PCIX0_POM0SA);
494 writel(0, reg + PCIX0_POM1SA);
495 writel(0, reg + PCIX0_POM2SA);
496 writel(0, reg + PCIX0_PIM0SA);
497 writel(0, reg + PCIX0_PIM1SA);
498 writel(0, reg + PCIX0_PIM2SA);
499 if (big_pim) {
500 writel(0, reg + PCIX0_PIM0SAH);
501 writel(0, reg + PCIX0_PIM2SAH);
502 }
503
504 /* Parse outbound mapping resources */
505 pci_process_bridge_OF_ranges(hose, np, primary);
506
507 /* Parse inbound mapping resources */
508 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
509 goto fail;
510
511 /* Configure outbound ranges POMs */
512 ppc4xx_configure_pcix_POMs(hose, reg);
513
514 /* Configure inbound ranges PIMs */
515 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
516
517 /* We don't need the registers anymore */
518 iounmap(reg);
519 return;
520
521 fail:
522 if (hose)
523 pcibios_free_controller(hose);
524 if (reg)
525 iounmap(reg);
526 }
527
528 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
529
530 /*
531 * 4xx PCI-Express part
532 *
533 * We support 3 parts currently based on the compatible property:
534 *
535 * ibm,plb-pciex-440spe
536 * ibm,plb-pciex-405ex
537 * ibm,plb-pciex-460ex
538 *
539 * Anything else will be rejected for now as they are all subtly
540 * different unfortunately.
541 *
542 */
543
544 #define MAX_PCIE_BUS_MAPPED 0x40
545
546 struct ppc4xx_pciex_port
547 {
548 struct pci_controller *hose;
549 struct device_node *node;
550 unsigned int index;
551 int endpoint;
552 int link;
553 int has_ibpre;
554 unsigned int sdr_base;
555 dcr_host_t dcrs;
556 struct resource cfg_space;
557 struct resource utl_regs;
558 void __iomem *utl_base;
559 };
560
561 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
562 static unsigned int ppc4xx_pciex_port_count;
563
564 struct ppc4xx_pciex_hwops
565 {
566 int (*core_init)(struct device_node *np);
567 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
568 int (*setup_utl)(struct ppc4xx_pciex_port *port);
569 };
570
571 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
572
573 #ifdef CONFIG_44x
574
575 /* Check various reset bits of the 440SPe PCIe core */
576 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
577 {
578 u32 valPE0, valPE1, valPE2;
579 int err = 0;
580
581 /* SDR0_PEGPLLLCT1 reset */
582 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
583 /*
584 * the PCIe core was probably already initialised
585 * by firmware - let's re-reset RCSSET regs
586 *
587 * -- Shouldn't we also re-reset the whole thing ? -- BenH
588 */
589 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
590 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
591 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
592 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
593 }
594
595 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
596 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
597 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
598
599 /* SDR0_PExRCSSET rstgu */
600 if (!(valPE0 & 0x01000000) ||
601 !(valPE1 & 0x01000000) ||
602 !(valPE2 & 0x01000000)) {
603 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
604 err = -1;
605 }
606
607 /* SDR0_PExRCSSET rstdl */
608 if (!(valPE0 & 0x00010000) ||
609 !(valPE1 & 0x00010000) ||
610 !(valPE2 & 0x00010000)) {
611 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
612 err = -1;
613 }
614
615 /* SDR0_PExRCSSET rstpyn */
616 if ((valPE0 & 0x00001000) ||
617 (valPE1 & 0x00001000) ||
618 (valPE2 & 0x00001000)) {
619 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
620 err = -1;
621 }
622
623 /* SDR0_PExRCSSET hldplb */
624 if ((valPE0 & 0x10000000) ||
625 (valPE1 & 0x10000000) ||
626 (valPE2 & 0x10000000)) {
627 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
628 err = -1;
629 }
630
631 /* SDR0_PExRCSSET rdy */
632 if ((valPE0 & 0x00100000) ||
633 (valPE1 & 0x00100000) ||
634 (valPE2 & 0x00100000)) {
635 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
636 err = -1;
637 }
638
639 /* SDR0_PExRCSSET shutdown */
640 if ((valPE0 & 0x00000100) ||
641 (valPE1 & 0x00000100) ||
642 (valPE2 & 0x00000100)) {
643 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
644 err = -1;
645 }
646
647 return err;
648 }
649
650 /* Global PCIe core initializations for 440SPe core */
651 static int __init ppc440spe_pciex_core_init(struct device_node *np)
652 {
653 int time_out = 20;
654
655 /* Set PLL clock receiver to LVPECL */
656 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
657
658 /* Shouldn't we do all the calibration stuff etc... here ? */
659 if (ppc440spe_pciex_check_reset(np))
660 return -ENXIO;
661
662 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
663 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
664 "failed (0x%08x)\n",
665 mfdcri(SDR0, PESDR0_PLLLCT2));
666 return -1;
667 }
668
669 /* De-assert reset of PCIe PLL, wait for lock */
670 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
671 udelay(3);
672
673 while (time_out) {
674 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
675 time_out--;
676 udelay(1);
677 } else
678 break;
679 }
680 if (!time_out) {
681 printk(KERN_INFO "PCIE: VCO output not locked\n");
682 return -1;
683 }
684
685 pr_debug("PCIE initialization OK\n");
686
687 return 3;
688 }
689
690 static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
691 {
692 u32 val = 1 << 24;
693
694 if (port->endpoint)
695 val = PTYPE_LEGACY_ENDPOINT << 20;
696 else
697 val = PTYPE_ROOT_PORT << 20;
698
699 if (port->index == 0)
700 val |= LNKW_X8 << 12;
701 else
702 val |= LNKW_X4 << 12;
703
704 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
705 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
706 if (ppc440spe_revA())
707 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
708 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
709 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
710 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
711 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
712 if (port->index == 0) {
713 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
714 0x35000000);
715 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
716 0x35000000);
717 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
718 0x35000000);
719 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
720 0x35000000);
721 }
722 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
723 (1 << 24) | (1 << 16), 1 << 12);
724
725 return 0;
726 }
727
728 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
729 {
730 return ppc440spe_pciex_init_port_hw(port);
731 }
732
733 static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
734 {
735 int rc = ppc440spe_pciex_init_port_hw(port);
736
737 port->has_ibpre = 1;
738
739 return rc;
740 }
741
742 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
743 {
744 /* XXX Check what that value means... I hate magic */
745 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
746
747 /*
748 * Set buffer allocations and then assert VRB and TXE.
749 */
750 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
751 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
752 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
753 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
754 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
755 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
756 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
757 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
758
759 return 0;
760 }
761
762 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
763 {
764 /* Report CRS to the operating system */
765 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
766
767 return 0;
768 }
769
770 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
771 {
772 .core_init = ppc440spe_pciex_core_init,
773 .port_init_hw = ppc440speA_pciex_init_port_hw,
774 .setup_utl = ppc440speA_pciex_init_utl,
775 };
776
777 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
778 {
779 .core_init = ppc440spe_pciex_core_init,
780 .port_init_hw = ppc440speB_pciex_init_port_hw,
781 .setup_utl = ppc440speB_pciex_init_utl,
782 };
783
784 static int __init ppc460ex_pciex_core_init(struct device_node *np)
785 {
786 /* Nothing to do, return 2 ports */
787 return 2;
788 }
789
790 static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
791 {
792 u32 val;
793 u32 utlset1;
794
795 if (port->endpoint)
796 val = PTYPE_LEGACY_ENDPOINT << 20;
797 else
798 val = PTYPE_ROOT_PORT << 20;
799
800 if (port->index == 0) {
801 val |= LNKW_X1 << 12;
802 utlset1 = 0x20000000;
803 } else {
804 val |= LNKW_X4 << 12;
805 utlset1 = 0x20101101;
806 }
807
808 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
809 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
810 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
811
812 switch (port->index) {
813 case 0:
814 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
815 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
816 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
817
818 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
819 break;
820
821 case 1:
822 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
823 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
824 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
825 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
826 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
827 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
828 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
829 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
830 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
831 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
832 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
833 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
834
835 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
836 break;
837 }
838
839 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
840 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
841 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
842
843 /* Poll for PHY reset */
844 /* XXX FIXME add timeout */
845 switch (port->index) {
846 case 0:
847 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
848 udelay(10);
849 break;
850 case 1:
851 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
852 udelay(10);
853 break;
854 }
855
856 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
857 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
858 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
859 PESDRx_RCSSET_RSTPYN);
860
861 port->has_ibpre = 1;
862
863 return 0;
864 }
865
866 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
867 {
868 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
869
870 /*
871 * Set buffer allocations and then assert VRB and TXE.
872 */
873 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
874 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
875 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
876 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
877 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
878 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
879 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
880 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
881 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
882
883 return 0;
884 }
885
886 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
887 {
888 .core_init = ppc460ex_pciex_core_init,
889 .port_init_hw = ppc460ex_pciex_init_port_hw,
890 .setup_utl = ppc460ex_pciex_init_utl,
891 };
892
893 #endif /* CONFIG_44x */
894
895 #ifdef CONFIG_40x
896
897 static int __init ppc405ex_pciex_core_init(struct device_node *np)
898 {
899 /* Nothing to do, return 2 ports */
900 return 2;
901 }
902
903 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
904 {
905 /* Assert the PE0_PHY reset */
906 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
907 msleep(1);
908
909 /* deassert the PE0_hotreset */
910 if (port->endpoint)
911 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
912 else
913 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
914
915 /* poll for phy !reset */
916 /* XXX FIXME add timeout */
917 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
918 ;
919
920 /* deassert the PE0_gpl_utl_reset */
921 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
922 }
923
924 static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
925 {
926 u32 val;
927
928 if (port->endpoint)
929 val = PTYPE_LEGACY_ENDPOINT;
930 else
931 val = PTYPE_ROOT_PORT;
932
933 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
934 1 << 24 | val << 20 | LNKW_X1 << 12);
935
936 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
937 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
938 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
939 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
940
941 /*
942 * Only reset the PHY when no link is currently established.
943 * This is for the Atheros PCIe board which has problems to establish
944 * the link (again) after this PHY reset. All other currently tested
945 * PCIe boards don't show this problem.
946 * This has to be re-tested and fixed in a later release!
947 */
948 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
949 if (!(val & 0x00001000))
950 ppc405ex_pcie_phy_reset(port);
951
952 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
953
954 port->has_ibpre = 1;
955
956 return 0;
957 }
958
959 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
960 {
961 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
962
963 /*
964 * Set buffer allocations and then assert VRB and TXE.
965 */
966 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
967 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
968 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
969 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
970 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
971 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
972 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
973 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
974
975 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
976
977 return 0;
978 }
979
980 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
981 {
982 .core_init = ppc405ex_pciex_core_init,
983 .port_init_hw = ppc405ex_pciex_init_port_hw,
984 .setup_utl = ppc405ex_pciex_init_utl,
985 };
986
987 #endif /* CONFIG_40x */
988
989
990 /* Check that the core has been initied and if not, do it */
991 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
992 {
993 static int core_init;
994 int count = -ENODEV;
995
996 if (core_init++)
997 return 0;
998
999 #ifdef CONFIG_44x
1000 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1001 if (ppc440spe_revA())
1002 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1003 else
1004 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1005 }
1006 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1007 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1008 #endif /* CONFIG_44x */
1009 #ifdef CONFIG_40x
1010 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1011 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1012 #endif
1013 if (ppc4xx_pciex_hwops == NULL) {
1014 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1015 np->full_name);
1016 return -ENODEV;
1017 }
1018
1019 count = ppc4xx_pciex_hwops->core_init(np);
1020 if (count > 0) {
1021 ppc4xx_pciex_ports =
1022 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1023 GFP_KERNEL);
1024 if (ppc4xx_pciex_ports) {
1025 ppc4xx_pciex_port_count = count;
1026 return 0;
1027 }
1028 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1029 return -ENOMEM;
1030 }
1031 return -ENODEV;
1032 }
1033
1034 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1035 {
1036 /* We map PCI Express configuration based on the reg property */
1037 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1038 RES_TO_U32_HIGH(port->cfg_space.start));
1039 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1040 RES_TO_U32_LOW(port->cfg_space.start));
1041
1042 /* XXX FIXME: Use size from reg property. For now, map 512M */
1043 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1044
1045 /* We map UTL registers based on the reg property */
1046 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1047 RES_TO_U32_HIGH(port->utl_regs.start));
1048 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1049 RES_TO_U32_LOW(port->utl_regs.start));
1050
1051 /* XXX FIXME: Use size from reg property */
1052 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1053
1054 /* Disable all other outbound windows */
1055 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1056 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1057 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1058 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1059 }
1060
1061 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1062 unsigned int sdr_offset,
1063 unsigned int mask,
1064 unsigned int value,
1065 int timeout_ms)
1066 {
1067 u32 val;
1068
1069 while(timeout_ms--) {
1070 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1071 if ((val & mask) == value) {
1072 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1073 port->index, sdr_offset, timeout_ms, val);
1074 return 0;
1075 }
1076 msleep(1);
1077 }
1078 return -1;
1079 }
1080
1081 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1082 {
1083 int rc = 0;
1084
1085 /* Init HW */
1086 if (ppc4xx_pciex_hwops->port_init_hw)
1087 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1088 if (rc != 0)
1089 return rc;
1090
1091 printk(KERN_INFO "PCIE%d: Checking link...\n",
1092 port->index);
1093
1094 /* Wait for reset to complete */
1095 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1096 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1097 port->index);
1098 return -1;
1099 }
1100
1101 /* Check for card presence detect if supported, if not, just wait for
1102 * link unconditionally.
1103 *
1104 * note that we don't fail if there is no link, we just filter out
1105 * config space accesses. That way, it will be easier to implement
1106 * hotplug later on.
1107 */
1108 if (!port->has_ibpre ||
1109 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1110 1 << 28, 1 << 28, 100)) {
1111 printk(KERN_INFO
1112 "PCIE%d: Device detected, waiting for link...\n",
1113 port->index);
1114 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1115 0x1000, 0x1000, 2000))
1116 printk(KERN_WARNING
1117 "PCIE%d: Link up failed\n", port->index);
1118 else {
1119 printk(KERN_INFO
1120 "PCIE%d: link is up !\n", port->index);
1121 port->link = 1;
1122 }
1123 } else
1124 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
1125
1126 /*
1127 * Initialize mapping: disable all regions and configure
1128 * CFG and REG regions based on resources in the device tree
1129 */
1130 ppc4xx_pciex_port_init_mapping(port);
1131
1132 /*
1133 * Map UTL
1134 */
1135 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1136 BUG_ON(port->utl_base == NULL);
1137
1138 /*
1139 * Setup UTL registers --BenH.
1140 */
1141 if (ppc4xx_pciex_hwops->setup_utl)
1142 ppc4xx_pciex_hwops->setup_utl(port);
1143
1144 /*
1145 * Check for VC0 active and assert RDY.
1146 */
1147 if (port->link &&
1148 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1149 1 << 16, 1 << 16, 5000)) {
1150 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1151 port->link = 0;
1152 }
1153
1154 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1155 msleep(100);
1156
1157 return 0;
1158 }
1159
1160 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1161 struct pci_bus *bus,
1162 unsigned int devfn)
1163 {
1164 static int message;
1165
1166 /* Endpoint can not generate upstream(remote) config cycles */
1167 if (port->endpoint && bus->number != port->hose->first_busno)
1168 return PCIBIOS_DEVICE_NOT_FOUND;
1169
1170 /* Check we are within the mapped range */
1171 if (bus->number > port->hose->last_busno) {
1172 if (!message) {
1173 printk(KERN_WARNING "Warning! Probing bus %u"
1174 " out of range !\n", bus->number);
1175 message++;
1176 }
1177 return PCIBIOS_DEVICE_NOT_FOUND;
1178 }
1179
1180 /* The root complex has only one device / function */
1181 if (bus->number == port->hose->first_busno && devfn != 0)
1182 return PCIBIOS_DEVICE_NOT_FOUND;
1183
1184 /* The other side of the RC has only one device as well */
1185 if (bus->number == (port->hose->first_busno + 1) &&
1186 PCI_SLOT(devfn) != 0)
1187 return PCIBIOS_DEVICE_NOT_FOUND;
1188
1189 /* Check if we have a link */
1190 if ((bus->number != port->hose->first_busno) && !port->link)
1191 return PCIBIOS_DEVICE_NOT_FOUND;
1192
1193 return 0;
1194 }
1195
1196 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1197 struct pci_bus *bus,
1198 unsigned int devfn)
1199 {
1200 int relbus;
1201
1202 /* Remove the casts when we finally remove the stupid volatile
1203 * in struct pci_controller
1204 */
1205 if (bus->number == port->hose->first_busno)
1206 return (void __iomem *)port->hose->cfg_addr;
1207
1208 relbus = bus->number - (port->hose->first_busno + 1);
1209 return (void __iomem *)port->hose->cfg_data +
1210 ((relbus << 20) | (devfn << 12));
1211 }
1212
1213 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1214 int offset, int len, u32 *val)
1215 {
1216 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1217 struct ppc4xx_pciex_port *port =
1218 &ppc4xx_pciex_ports[hose->indirect_type];
1219 void __iomem *addr;
1220 u32 gpl_cfg;
1221
1222 BUG_ON(hose != port->hose);
1223
1224 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1225 return PCIBIOS_DEVICE_NOT_FOUND;
1226
1227 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1228
1229 /*
1230 * Reading from configuration space of non-existing device can
1231 * generate transaction errors. For the read duration we suppress
1232 * assertion of machine check exceptions to avoid those.
1233 */
1234 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1235 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1236
1237 /* Make sure no CRS is recorded */
1238 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1239
1240 switch (len) {
1241 case 1:
1242 *val = in_8((u8 *)(addr + offset));
1243 break;
1244 case 2:
1245 *val = in_le16((u16 *)(addr + offset));
1246 break;
1247 default:
1248 *val = in_le32((u32 *)(addr + offset));
1249 break;
1250 }
1251
1252 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1253 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1254 bus->number, hose->first_busno, hose->last_busno,
1255 devfn, offset, len, addr + offset, *val);
1256
1257 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1258 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1259 pr_debug("Got CRS !\n");
1260 if (len != 4 || offset != 0)
1261 return PCIBIOS_DEVICE_NOT_FOUND;
1262 *val = 0xffff0001;
1263 }
1264
1265 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1266
1267 return PCIBIOS_SUCCESSFUL;
1268 }
1269
1270 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1271 int offset, int len, u32 val)
1272 {
1273 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1274 struct ppc4xx_pciex_port *port =
1275 &ppc4xx_pciex_ports[hose->indirect_type];
1276 void __iomem *addr;
1277 u32 gpl_cfg;
1278
1279 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1280 return PCIBIOS_DEVICE_NOT_FOUND;
1281
1282 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1283
1284 /*
1285 * Reading from configuration space of non-existing device can
1286 * generate transaction errors. For the read duration we suppress
1287 * assertion of machine check exceptions to avoid those.
1288 */
1289 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1290 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1291
1292 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1293 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1294 bus->number, hose->first_busno, hose->last_busno,
1295 devfn, offset, len, addr + offset, val);
1296
1297 switch (len) {
1298 case 1:
1299 out_8((u8 *)(addr + offset), val);
1300 break;
1301 case 2:
1302 out_le16((u16 *)(addr + offset), val);
1303 break;
1304 default:
1305 out_le32((u32 *)(addr + offset), val);
1306 break;
1307 }
1308
1309 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1310
1311 return PCIBIOS_SUCCESSFUL;
1312 }
1313
1314 static struct pci_ops ppc4xx_pciex_pci_ops =
1315 {
1316 .read = ppc4xx_pciex_read_config,
1317 .write = ppc4xx_pciex_write_config,
1318 };
1319
1320 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1321 struct pci_controller *hose,
1322 void __iomem *mbase)
1323 {
1324 u32 lah, lal, pciah, pcial, sa;
1325 int i, j;
1326
1327 /* Setup outbound memory windows */
1328 for (i = j = 0; i < 3; i++) {
1329 struct resource *res = &hose->mem_resources[i];
1330
1331 /* we only care about memory windows */
1332 if (!(res->flags & IORESOURCE_MEM))
1333 continue;
1334 if (j > 1) {
1335 printk(KERN_WARNING "%s: Too many ranges\n",
1336 port->node->full_name);
1337 break;
1338 }
1339
1340 /* Calculate register values */
1341 lah = RES_TO_U32_HIGH(res->start);
1342 lal = RES_TO_U32_LOW(res->start);
1343 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
1344 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
1345 sa = res->end + 1 - res->start;
1346 if (!is_power_of_2(sa) || sa < 0x100000 ||
1347 sa > 0xffffffffu) {
1348 printk(KERN_WARNING "%s: Resource out of range\n",
1349 port->node->full_name);
1350 continue;
1351 }
1352 sa = (0xffffffffu << ilog2(sa)) | 0x1;
1353
1354 /* Program register values */
1355 switch (j) {
1356 case 0:
1357 out_le32(mbase + PECFG_POM0LAH, pciah);
1358 out_le32(mbase + PECFG_POM0LAL, pcial);
1359 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1360 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1361 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1362 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1363 break;
1364 case 1:
1365 out_le32(mbase + PECFG_POM1LAH, pciah);
1366 out_le32(mbase + PECFG_POM1LAL, pcial);
1367 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1368 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1369 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1370 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1371 break;
1372 }
1373 j++;
1374 }
1375
1376 /* Configure IO, always 64K starting at 0 */
1377 if (hose->io_resource.flags & IORESOURCE_IO) {
1378 lah = RES_TO_U32_HIGH(hose->io_base_phys);
1379 lal = RES_TO_U32_LOW(hose->io_base_phys);
1380 out_le32(mbase + PECFG_POM2LAH, 0);
1381 out_le32(mbase + PECFG_POM2LAL, 0);
1382 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1383 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1384 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1385 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0xffff0000 | 3);
1386 }
1387 }
1388
1389 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1390 struct pci_controller *hose,
1391 void __iomem *mbase,
1392 struct resource *res)
1393 {
1394 resource_size_t size = res->end - res->start + 1;
1395 u64 sa;
1396
1397 if (port->endpoint) {
1398 resource_size_t ep_addr = 0;
1399 resource_size_t ep_size = 32 << 20;
1400
1401 /* Currently we map a fixed 64MByte window to PLB address
1402 * 0 (SDRAM). This should probably be configurable via a dts
1403 * property.
1404 */
1405
1406 /* Calculate window size */
1407 sa = (0xffffffffffffffffull << ilog2(ep_size));;
1408
1409 /* Setup BAR0 */
1410 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1411 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1412 PCI_BASE_ADDRESS_MEM_TYPE_64);
1413
1414 /* Disable BAR1 & BAR2 */
1415 out_le32(mbase + PECFG_BAR1MPA, 0);
1416 out_le32(mbase + PECFG_BAR2HMPA, 0);
1417 out_le32(mbase + PECFG_BAR2LMPA, 0);
1418
1419 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1420 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1421
1422 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1423 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1424 } else {
1425 /* Calculate window size */
1426 sa = (0xffffffffffffffffull << ilog2(size));;
1427 if (res->flags & IORESOURCE_PREFETCH)
1428 sa |= 0x8;
1429
1430 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1431 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1432
1433 /* The setup of the split looks weird to me ... let's see
1434 * if it works
1435 */
1436 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1437 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1438 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1439 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1440 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1441 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1442
1443 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1444 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1445 }
1446
1447 /* Enable inbound mapping */
1448 out_le32(mbase + PECFG_PIMEN, 0x1);
1449
1450 /* Enable I/O, Mem, and Busmaster cycles */
1451 out_le16(mbase + PCI_COMMAND,
1452 in_le16(mbase + PCI_COMMAND) |
1453 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1454 }
1455
1456 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1457 {
1458 struct resource dma_window;
1459 struct pci_controller *hose = NULL;
1460 const int *bus_range;
1461 int primary = 0, busses;
1462 void __iomem *mbase = NULL, *cfg_data = NULL;
1463 const u32 *pval;
1464 u32 val;
1465
1466 /* Check if primary bridge */
1467 if (of_get_property(port->node, "primary", NULL))
1468 primary = 1;
1469
1470 /* Get bus range if any */
1471 bus_range = of_get_property(port->node, "bus-range", NULL);
1472
1473 /* Allocate the host controller data structure */
1474 hose = pcibios_alloc_controller(port->node);
1475 if (!hose)
1476 goto fail;
1477
1478 /* We stick the port number in "indirect_type" so the config space
1479 * ops can retrieve the port data structure easily
1480 */
1481 hose->indirect_type = port->index;
1482
1483 /* Get bus range */
1484 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1485 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1486
1487 /* Because of how big mapping the config space is (1M per bus), we
1488 * limit how many busses we support. In the long run, we could replace
1489 * that with something akin to kmap_atomic instead. We set aside 1 bus
1490 * for the host itself too.
1491 */
1492 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1493 if (busses > MAX_PCIE_BUS_MAPPED) {
1494 busses = MAX_PCIE_BUS_MAPPED;
1495 hose->last_busno = hose->first_busno + busses;
1496 }
1497
1498 if (!port->endpoint) {
1499 /* Only map the external config space in cfg_data for
1500 * PCIe root-complexes. External space is 1M per bus
1501 */
1502 cfg_data = ioremap(port->cfg_space.start +
1503 (hose->first_busno + 1) * 0x100000,
1504 busses * 0x100000);
1505 if (cfg_data == NULL) {
1506 printk(KERN_ERR "%s: Can't map external config space !",
1507 port->node->full_name);
1508 goto fail;
1509 }
1510 hose->cfg_data = cfg_data;
1511 }
1512
1513 /* Always map the host config space in cfg_addr.
1514 * Internal space is 4K
1515 */
1516 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1517 if (mbase == NULL) {
1518 printk(KERN_ERR "%s: Can't map internal config space !",
1519 port->node->full_name);
1520 goto fail;
1521 }
1522 hose->cfg_addr = mbase;
1523
1524 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1525 hose->first_busno, hose->last_busno);
1526 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1527 hose->cfg_addr, hose->cfg_data);
1528
1529 /* Setup config space */
1530 hose->ops = &ppc4xx_pciex_pci_ops;
1531 port->hose = hose;
1532 mbase = (void __iomem *)hose->cfg_addr;
1533
1534 if (!port->endpoint) {
1535 /*
1536 * Set bus numbers on our root port
1537 */
1538 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1539 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1540 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1541 }
1542
1543 /*
1544 * OMRs are already reset, also disable PIMs
1545 */
1546 out_le32(mbase + PECFG_PIMEN, 0);
1547
1548 /* Parse outbound mapping resources */
1549 pci_process_bridge_OF_ranges(hose, port->node, primary);
1550
1551 /* Parse inbound mapping resources */
1552 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1553 goto fail;
1554
1555 /* Configure outbound ranges POMs */
1556 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1557
1558 /* Configure inbound ranges PIMs */
1559 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1560
1561 /* The root complex doesn't show up if we don't set some vendor
1562 * and device IDs into it. The defaults below are the same bogus
1563 * one that the initial code in arch/ppc had. This can be
1564 * overwritten by setting the "vendor-id/device-id" properties
1565 * in the pciex node.
1566 */
1567
1568 /* Get the (optional) vendor-/device-id from the device-tree */
1569 pval = of_get_property(port->node, "vendor-id", NULL);
1570 if (pval) {
1571 val = *pval;
1572 } else {
1573 if (!port->endpoint)
1574 val = 0xaaa0 + port->index;
1575 else
1576 val = 0xeee0 + port->index;
1577 }
1578 out_le16(mbase + 0x200, val);
1579
1580 pval = of_get_property(port->node, "device-id", NULL);
1581 if (pval) {
1582 val = *pval;
1583 } else {
1584 if (!port->endpoint)
1585 val = 0xbed0 + port->index;
1586 else
1587 val = 0xfed0 + port->index;
1588 }
1589 out_le16(mbase + 0x202, val);
1590
1591 if (!port->endpoint) {
1592 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1593 out_le32(mbase + 0x208, 0x06040001);
1594
1595 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1596 port->index);
1597 } else {
1598 /* Set Class Code to Processor/PPC */
1599 out_le32(mbase + 0x208, 0x0b200001);
1600
1601 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1602 port->index);
1603 }
1604
1605 return;
1606 fail:
1607 if (hose)
1608 pcibios_free_controller(hose);
1609 if (cfg_data)
1610 iounmap(cfg_data);
1611 if (mbase)
1612 iounmap(mbase);
1613 }
1614
1615 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1616 {
1617 struct ppc4xx_pciex_port *port;
1618 const u32 *pval;
1619 int portno;
1620 unsigned int dcrs;
1621 const char *val;
1622
1623 /* First, proceed to core initialization as we assume there's
1624 * only one PCIe core in the system
1625 */
1626 if (ppc4xx_pciex_check_core_init(np))
1627 return;
1628
1629 /* Get the port number from the device-tree */
1630 pval = of_get_property(np, "port", NULL);
1631 if (pval == NULL) {
1632 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1633 np->full_name);
1634 return;
1635 }
1636 portno = *pval;
1637 if (portno >= ppc4xx_pciex_port_count) {
1638 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1639 np->full_name);
1640 return;
1641 }
1642 port = &ppc4xx_pciex_ports[portno];
1643 port->index = portno;
1644
1645 /*
1646 * Check if device is enabled
1647 */
1648 if (!of_device_is_available(np)) {
1649 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
1650 return;
1651 }
1652
1653 port->node = of_node_get(np);
1654 pval = of_get_property(np, "sdr-base", NULL);
1655 if (pval == NULL) {
1656 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1657 np->full_name);
1658 return;
1659 }
1660 port->sdr_base = *pval;
1661
1662 /* Check if device_type property is set to "pci" or "pci-endpoint".
1663 * Resulting from this setup this PCIe port will be configured
1664 * as root-complex or as endpoint.
1665 */
1666 val = of_get_property(port->node, "device_type", NULL);
1667 if (!strcmp(val, "pci-endpoint")) {
1668 port->endpoint = 1;
1669 } else if (!strcmp(val, "pci")) {
1670 port->endpoint = 0;
1671 } else {
1672 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1673 np->full_name);
1674 return;
1675 }
1676
1677 /* Fetch config space registers address */
1678 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1679 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1680 np->full_name);
1681 return;
1682 }
1683 /* Fetch host bridge internal registers address */
1684 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1685 printk(KERN_ERR "%s: Can't get UTL register base !",
1686 np->full_name);
1687 return;
1688 }
1689
1690 /* Map DCRs */
1691 dcrs = dcr_resource_start(np, 0);
1692 if (dcrs == 0) {
1693 printk(KERN_ERR "%s: Can't get DCR register base !",
1694 np->full_name);
1695 return;
1696 }
1697 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1698
1699 /* Initialize the port specific registers */
1700 if (ppc4xx_pciex_port_init(port)) {
1701 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
1702 return;
1703 }
1704
1705 /* Setup the linux hose data structure */
1706 ppc4xx_pciex_port_setup_hose(port);
1707 }
1708
1709 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1710
1711 static int __init ppc4xx_pci_find_bridges(void)
1712 {
1713 struct device_node *np;
1714
1715 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
1716 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1717 ppc4xx_probe_pciex_bridge(np);
1718 #endif
1719 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1720 ppc4xx_probe_pcix_bridge(np);
1721 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1722 ppc4xx_probe_pci_bridge(np);
1723
1724 return 0;
1725 }
1726 arch_initcall(ppc4xx_pci_find_bridges);
1727
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