arch/sh/kernel/cpu/sh2a/probe.c

   1 /*
   2  * arch/sh/kernel/cpu/sh2a/probe.c
   3  *
   4  * CPU Subtype Probing for SH-2A.
   5  *
   6  * Copyright (C) 2004 - 2007  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <asm/processor.h>
  14 #include <asm/cache.h>
  15
  16 int __init detect_cpu_and_cache_system(void)
  17 {
  18         /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
  19         boot_cpu_data.flags                     |= CPU_HAS_OP32;
  20
  21 #if defined(CONFIG_CPU_SUBTYPE_SH7203)
  22         boot_cpu_data.type                      = CPU_SH7203;
  23         /* SH7203 has an FPU.. */
  24         boot_cpu_data.flags                     |= CPU_HAS_FPU;
  25 #elif defined(CONFIG_CPU_SUBTYPE_SH7263)
  26         boot_cpu_data.type                      = CPU_SH7263;
  27         boot_cpu_data.flags                     |= CPU_HAS_FPU;
  28 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
  29         boot_cpu_data.type                      = CPU_SH7206;
  30         /* While SH7206 has a DSP.. */
  31         boot_cpu_data.flags                     |= CPU_HAS_DSP;
  32 #elif defined(CONFIG_CPU_SUBTYPE_MXG)
  33         boot_cpu_data.type                      = CPU_MXG;
  34         boot_cpu_data.flags                     |= CPU_HAS_DSP;
  35 #endif
  36
  37         boot_cpu_data.dcache.ways               = 4;
  38         boot_cpu_data.dcache.way_incr           = (1 << 11);
  39         boot_cpu_data.dcache.sets               = 128;
  40         boot_cpu_data.dcache.entry_shift        = 4;
  41         boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
  42         boot_cpu_data.dcache.flags              = 0;
  43
  44         /*
  45          * The icache is the same as the dcache as far as this setup is
  46          * concerned. The only real difference in hardware is that the icache
  47          * lacks the U bit that the dcache has, none of this has any bearing
  48          * on the cache info.
  49          */
  50         boot_cpu_data.icache            = boot_cpu_data.dcache;
  51
  52         return 0;
  53 }