| blob | 7e3d535754863cbd433b033ac8b9916de5fb0060 |
1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
3 bool
4 default y
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_SET_MEMORY
11 select ARCH_HAS_PHYS_TO_DMA
12 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
13 select ARCH_HAS_STRICT_MODULE_RWX if MMU
14 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
15 select ARCH_HAVE_CUSTOM_GPIO_H
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_MIGHT_HAVE_PC_PARPORT
18 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
19 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
20 select ARCH_SUPPORTS_ATOMIC_RMW
21 select ARCH_USE_BUILTIN_BSWAP
22 select ARCH_USE_CMPXCHG_LOCKREF
23 select ARCH_WANT_IPC_PARSE_VERSION
24 select BUILDTIME_EXTABLE_SORT if MMU
25 select CLONE_BACKWARDS
26 select CPU_PM if (SUSPEND || CPU_IDLE)
27 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
28 select DMA_DIRECT_OPS if !MMU
29 select EDAC_SUPPORT
30 select EDAC_ATOMIC_SCRUB
31 select GENERIC_ALLOCATOR
32 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
33 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
34 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select HANDLE_DOMAIN_IRQ
47 select HARDIRQS_SW_RESEND
48 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
49 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
50 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
51 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
52 select HAVE_ARCH_MMAP_RND_BITS if MMU
53 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
54 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
55 select HAVE_ARCH_TRACEHOOK
56 select HAVE_ARM_SMCCC if CPU_V7
57 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
58 select HAVE_CC_STACKPROTECTOR
59 select HAVE_CONTEXT_TRACKING
60 select HAVE_C_RECORDMCOUNT
61 select HAVE_DEBUG_KMEMLEAK
62 select HAVE_DMA_API_DEBUG
63 select HAVE_DMA_CONTIGUOUS if MMU
64 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
65 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
66 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
67 select HAVE_EXIT_THREAD
68 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
69 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
70 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
71 select HAVE_GCC_PLUGINS
72 select HAVE_GENERIC_DMA_COHERENT
73 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
74 select HAVE_IDE if PCI || ISA || PCMCIA
75 select HAVE_IRQ_TIME_ACCOUNTING
76 select HAVE_KERNEL_GZIP
77 select HAVE_KERNEL_LZ4
78 select HAVE_KERNEL_LZMA
79 select HAVE_KERNEL_LZO
80 select HAVE_KERNEL_XZ
81 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
82 select HAVE_KRETPROBES if (HAVE_KPROBES)
83 select HAVE_MEMBLOCK
84 select HAVE_MOD_ARCH_SPECIFIC
85 select HAVE_NMI
86 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
87 select HAVE_OPTPROBES if !THUMB2_KERNEL
88 select HAVE_PERF_EVENTS
89 select HAVE_PERF_REGS
90 select HAVE_PERF_USER_STACK_DUMP
91 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
92 select HAVE_REGS_AND_STACK_ACCESS_API
93 select HAVE_SYSCALL_TRACEPOINTS
94 select HAVE_UID16
95 select HAVE_VIRT_CPU_ACCOUNTING_GEN
96 select IRQ_FORCED_THREADING
97 select MODULES_USE_ELF_REL
98 select NO_BOOTMEM
99 select OF_EARLY_FLATTREE if OF
100 select OF_RESERVED_MEM if OF
101 select OLD_SIGACTION
102 select OLD_SIGSUSPEND3
103 select PERF_USE_VMALLOC
104 select REFCOUNT_FULL
105 select RTC_LIB
106 select SYS_SUPPORTS_APM_EMULATION
107 # Above selects are sorted alphabetically; please add new ones
108 # according to that. Thanks.
109 help
110 The ARM series is a line of low-power-consumption RISC chip designs
111 licensed by ARM Ltd and targeted at embedded applications and
112 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
113 manufactured, but legacy ARM-based PC hardware remains popular in
114 Europe. There is an ARM Linux project with a web page at
115 <http://www.arm.linux.org.uk/>.
117 config ARM_HAS_SG_CHAIN
118 select ARCH_HAS_SG_CHAIN
119 bool
121 config NEED_SG_DMA_LENGTH
122 bool
124 config ARM_DMA_USE_IOMMU
125 bool
126 select ARM_HAS_SG_CHAIN
127 select NEED_SG_DMA_LENGTH
129 if ARM_DMA_USE_IOMMU
131 config ARM_DMA_IOMMU_ALIGNMENT
132 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
133 range 4 9
134 default 8
135 help
136 DMA mapping framework by default aligns all buffers to the smallest
137 PAGE_SIZE order which is greater than or equal to the requested buffer
138 size. This works well for buffers up to a few hundreds kilobytes, but
139 for larger buffers it just a waste of address space. Drivers which has
140 relatively small addressing window (like 64Mib) might run out of
141 virtual space with just a few allocations.
143 With this parameter you can specify the maximum PAGE_SIZE order for
144 DMA IOMMU buffers. Larger buffers will be aligned only to this
145 specified order. The order is expressed as a power of two multiplied
146 by the PAGE_SIZE.
148 endif
150 config MIGHT_HAVE_PCI
151 bool
153 config SYS_SUPPORTS_APM_EMULATION
154 bool
156 config HAVE_TCM
157 bool
158 select GENERIC_ALLOCATOR
160 config HAVE_PROC_CPU
161 bool
163 config NO_IOPORT_MAP
164 bool
166 config EISA
167 bool
168 ---help---
169 The Extended Industry Standard Architecture (EISA) bus was
170 developed as an open alternative to the IBM MicroChannel bus.
172 The EISA bus provided some of the features of the IBM MicroChannel
173 bus while maintaining backward compatibility with cards made for
174 the older ISA bus. The EISA bus saw limited use between 1988 and
175 1995 when it was made obsolete by the PCI bus.
177 Say Y here if you are building a kernel for an EISA-based machine.
179 Otherwise, say N.
181 config SBUS
182 bool
184 config STACKTRACE_SUPPORT
185 bool
186 default y
188 config LOCKDEP_SUPPORT
189 bool
190 default y
192 config TRACE_IRQFLAGS_SUPPORT
193 bool
194 default !CPU_V7M
196 config RWSEM_XCHGADD_ALGORITHM
197 bool
198 default y
200 config ARCH_HAS_ILOG2_U32
201 bool
203 config ARCH_HAS_ILOG2_U64
204 bool
206 config ARCH_HAS_BANDGAP
207 bool
209 config FIX_EARLYCON_MEM
210 def_bool y if MMU
212 config GENERIC_HWEIGHT
213 bool
214 default y
216 config GENERIC_CALIBRATE_DELAY
217 bool
218 default y
220 config ARCH_MAY_HAVE_PC_FDC
221 bool
223 config ZONE_DMA
224 bool
226 config NEED_DMA_MAP_STATE
227 def_bool y
229 config ARCH_SUPPORTS_UPROBES
230 def_bool y
232 config ARCH_HAS_DMA_SET_COHERENT_MASK
233 bool
235 config GENERIC_ISA_DMA
236 bool
238 config FIQ
239 bool
241 config NEED_RET_TO_USER
242 bool
244 config ARCH_MTD_XIP
245 bool
247 config ARM_PATCH_PHYS_VIRT
248 bool "Patch physical to virtual translations at runtime" if EMBEDDED
249 default y
250 depends on !XIP_KERNEL && MMU
251 help
252 Patch phys-to-virt and virt-to-phys translation functions at
253 boot and module load time according to the position of the
254 kernel in system memory.
256 This can only be used with non-XIP MMU kernels where the base
257 of physical memory is at a 16MB boundary.
259 Only disable this option if you know that you do not require
260 this feature (eg, building a kernel for a single machine) and
261 you need to shrink the kernel to the minimal size.
263 config NEED_MACH_IO_H
264 bool
265 help
266 Select this when mach/io.h is required to provide special
267 definitions for this platform. The need for mach/io.h should
268 be avoided when possible.
270 config NEED_MACH_MEMORY_H
271 bool
272 help
273 Select this when mach/memory.h is required to provide special
274 definitions for this platform. The need for mach/memory.h should
275 be avoided when possible.
277 config PHYS_OFFSET
278 hex "Physical address of main memory" if MMU
279 depends on !ARM_PATCH_PHYS_VIRT
280 default DRAM_BASE if !MMU
281 default 0x00000000 if ARCH_EBSA110 || \
282 ARCH_FOOTBRIDGE || \
283 ARCH_INTEGRATOR || \
284 ARCH_IOP13XX || \
285 ARCH_KS8695 || \
286 ARCH_REALVIEW
287 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
288 default 0x20000000 if ARCH_S5PV210
289 default 0xc0000000 if ARCH_SA1100
290 help
291 Please provide the physical address corresponding to the
292 location of main memory in your system.
294 config GENERIC_BUG
295 def_bool y
296 depends on BUG
298 config PGTABLE_LEVELS
299 int
300 default 3 if ARM_LPAE
301 default 2
303 source "init/Kconfig"
305 source "kernel/Kconfig.freezer"
307 menu "System Type"
309 config MMU
310 bool "MMU-based Paged Memory Management Support"
311 default y
312 help
313 Select if you want MMU-based virtualised addressing space
314 support by paged memory management. If unsure, say 'Y'.
316 config ARCH_MMAP_RND_BITS_MIN
317 default 8
319 config ARCH_MMAP_RND_BITS_MAX
320 default 14 if PAGE_OFFSET=0x40000000
321 default 15 if PAGE_OFFSET=0x80000000
322 default 16
324 #
325 # The "ARM system type" choice list is ordered alphabetically by option
326 # text. Please add new entries in the option alphabetic order.
327 #
328 choice
329 prompt "ARM system type"
330 default ARM_SINGLE_ARMV7M if !MMU
331 default ARCH_MULTIPLATFORM if MMU
333 config ARCH_MULTIPLATFORM
334 bool "Allow multiple platforms to be selected"
335 depends on MMU
336 select ARM_HAS_SG_CHAIN
337 select ARM_PATCH_PHYS_VIRT
338 select AUTO_ZRELADDR
339 select TIMER_OF
340 select COMMON_CLK
341 select GENERIC_CLOCKEVENTS
342 select MIGHT_HAVE_PCI
343 select MULTI_IRQ_HANDLER
344 select PCI_DOMAINS if PCI
345 select SPARSE_IRQ
346 select USE_OF
348 config ARM_SINGLE_ARMV7M
349 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
350 depends on !MMU
351 select ARM_NVIC
352 select AUTO_ZRELADDR
353 select TIMER_OF
354 select COMMON_CLK
355 select CPU_V7M
356 select GENERIC_CLOCKEVENTS
357 select NO_IOPORT_MAP
358 select SPARSE_IRQ
359 select USE_OF
361 config ARCH_EBSA110
362 bool "EBSA-110"
363 select ARCH_USES_GETTIMEOFFSET
364 select CPU_SA110
365 select ISA
366 select NEED_MACH_IO_H
367 select NEED_MACH_MEMORY_H
368 select NO_IOPORT_MAP
369 help
370 This is an evaluation board for the StrongARM processor available
371 from Digital. It has limited hardware on-board, including an
372 Ethernet interface, two PCMCIA sockets, two serial ports and a
373 parallel port.
375 config ARCH_EP93XX
376 bool "EP93xx-based"
377 select ARCH_SPARSEMEM_ENABLE
378 select ARM_AMBA
379 imply ARM_PATCH_PHYS_VIRT
380 select ARM_VIC
381 select AUTO_ZRELADDR
382 select CLKDEV_LOOKUP
383 select CLKSRC_MMIO
384 select CPU_ARM920T
385 select GENERIC_CLOCKEVENTS
386 select GPIOLIB
387 help
388 This enables support for the Cirrus EP93xx series of CPUs.
390 config ARCH_FOOTBRIDGE
391 bool "FootBridge"
392 select CPU_SA110
393 select FOOTBRIDGE
394 select GENERIC_CLOCKEVENTS
395 select HAVE_IDE
396 select NEED_MACH_IO_H if !MMU
397 select NEED_MACH_MEMORY_H
398 help
399 Support for systems based on the DC21285 companion chip
400 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
402 config ARCH_NETX
403 bool "Hilscher NetX based"
404 select ARM_VIC
405 select CLKSRC_MMIO
406 select CPU_ARM926T
407 select GENERIC_CLOCKEVENTS
408 help
409 This enables support for systems based on the Hilscher NetX Soc
411 config ARCH_IOP13XX
412 bool "IOP13xx-based"
413 depends on MMU
414 select CPU_XSC3
415 select NEED_MACH_MEMORY_H
416 select NEED_RET_TO_USER
417 select PCI
418 select PLAT_IOP
419 select VMSPLIT_1G
420 select SPARSE_IRQ
421 help
422 Support for Intel's IOP13XX (XScale) family of processors.
424 config ARCH_IOP32X
425 bool "IOP32x-based"
426 depends on MMU
427 select CPU_XSCALE
428 select GPIO_IOP
429 select GPIOLIB
430 select NEED_RET_TO_USER
431 select PCI
432 select PLAT_IOP
433 help
434 Support for Intel's 80219 and IOP32X (XScale) family of
435 processors.
437 config ARCH_IOP33X
438 bool "IOP33x-based"
439 depends on MMU
440 select CPU_XSCALE
441 select GPIO_IOP
442 select GPIOLIB
443 select NEED_RET_TO_USER
444 select PCI
445 select PLAT_IOP
446 help
447 Support for Intel's IOP33X (XScale) family of processors.
449 config ARCH_IXP4XX
450 bool "IXP4xx-based"
451 depends on MMU
452 select ARCH_HAS_DMA_SET_COHERENT_MASK
453 select ARCH_SUPPORTS_BIG_ENDIAN
454 select CLKSRC_MMIO
455 select CPU_XSCALE
456 select DMABOUNCE if PCI
457 select GENERIC_CLOCKEVENTS
458 select GPIOLIB
459 select MIGHT_HAVE_PCI
460 select NEED_MACH_IO_H
461 select USB_EHCI_BIG_ENDIAN_DESC
462 select USB_EHCI_BIG_ENDIAN_MMIO
463 help
464 Support for Intel's IXP4XX (XScale) family of processors.
466 config ARCH_DOVE
467 bool "Marvell Dove"
468 select CPU_PJ4
469 select GENERIC_CLOCKEVENTS
470 select GPIOLIB
471 select MIGHT_HAVE_PCI
472 select MULTI_IRQ_HANDLER
473 select MVEBU_MBUS
474 select PINCTRL
475 select PINCTRL_DOVE
476 select PLAT_ORION_LEGACY
477 select SPARSE_IRQ
478 select PM_GENERIC_DOMAINS if PM
479 help
480 Support for the Marvell Dove SoC 88AP510
482 config ARCH_KS8695
483 bool "Micrel/Kendin KS8695"
484 select CLKSRC_MMIO
485 select CPU_ARM922T
486 select GENERIC_CLOCKEVENTS
487 select GPIOLIB
488 select NEED_MACH_MEMORY_H
489 help
490 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
491 System-on-Chip devices.
493 config ARCH_W90X900
494 bool "Nuvoton W90X900 CPU"
495 select CLKDEV_LOOKUP
496 select CLKSRC_MMIO
497 select CPU_ARM926T
498 select GENERIC_CLOCKEVENTS
499 select GPIOLIB
500 help
501 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
502 At present, the w90x900 has been renamed nuc900, regarding
503 the ARM series product line, you can login the following
504 link address to know more.
506 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
507 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
509 config ARCH_LPC32XX
510 bool "NXP LPC32XX"
511 select ARM_AMBA
512 select CLKDEV_LOOKUP
513 select CLKSRC_LPC32XX
514 select COMMON_CLK
515 select CPU_ARM926T
516 select GENERIC_CLOCKEVENTS
517 select GPIOLIB
518 select MULTI_IRQ_HANDLER
519 select SPARSE_IRQ
520 select USE_OF
521 help
522 Support for the NXP LPC32XX family of processors
524 config ARCH_PXA
525 bool "PXA2xx/PXA3xx-based"
526 depends on MMU
527 select ARCH_MTD_XIP
528 select ARM_CPU_SUSPEND if PM
529 select AUTO_ZRELADDR
530 select COMMON_CLK
531 select CLKDEV_LOOKUP
532 select CLKSRC_PXA
533 select CLKSRC_MMIO
534 select TIMER_OF
535 select CPU_XSCALE if !CPU_XSC3
536 select GENERIC_CLOCKEVENTS
537 select GPIO_PXA
538 select GPIOLIB
539 select HAVE_IDE
540 select IRQ_DOMAIN
541 select MULTI_IRQ_HANDLER
542 select PLAT_PXA
543 select SPARSE_IRQ
544 help
545 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
547 config ARCH_RPC
548 bool "RiscPC"
549 depends on MMU
550 select ARCH_ACORN
551 select ARCH_MAY_HAVE_PC_FDC
552 select ARCH_SPARSEMEM_ENABLE
553 select ARCH_USES_GETTIMEOFFSET
554 select CPU_SA110
555 select FIQ
556 select HAVE_IDE
557 select HAVE_PATA_PLATFORM
558 select ISA_DMA_API
559 select NEED_MACH_IO_H
560 select NEED_MACH_MEMORY_H
561 select NO_IOPORT_MAP
562 help
563 On the Acorn Risc-PC, Linux can support the internal IDE disk and
564 CD-ROM interface, serial and parallel port, and the floppy drive.
566 config ARCH_SA1100
567 bool "SA1100-based"
568 select ARCH_MTD_XIP
569 select ARCH_SPARSEMEM_ENABLE
570 select CLKDEV_LOOKUP
571 select CLKSRC_MMIO
572 select CLKSRC_PXA
573 select TIMER_OF if OF
574 select CPU_FREQ
575 select CPU_SA1100
576 select GENERIC_CLOCKEVENTS
577 select GPIOLIB
578 select HAVE_IDE
579 select IRQ_DOMAIN
580 select ISA
581 select MULTI_IRQ_HANDLER
582 select NEED_MACH_MEMORY_H
583 select SPARSE_IRQ
584 help
585 Support for StrongARM 11x0 based boards.
587 config ARCH_S3C24XX
588 bool "Samsung S3C24XX SoCs"
589 select ATAGS
590 select CLKDEV_LOOKUP
591 select CLKSRC_SAMSUNG_PWM
592 select GENERIC_CLOCKEVENTS
593 select GPIO_SAMSUNG
594 select GPIOLIB
595 select HAVE_S3C2410_I2C if I2C
596 select HAVE_S3C2410_WATCHDOG if WATCHDOG
597 select HAVE_S3C_RTC if RTC_CLASS
598 select MULTI_IRQ_HANDLER
599 select NEED_MACH_IO_H
600 select SAMSUNG_ATAGS
601 select USE_OF
602 help
603 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
604 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
605 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
606 Samsung SMDK2410 development board (and derivatives).
608 config ARCH_DAVINCI
609 bool "TI DaVinci"
610 select ARCH_HAS_HOLES_MEMORYMODEL
611 select CLKDEV_LOOKUP
612 select CPU_ARM926T
613 select GENERIC_ALLOCATOR
614 select GENERIC_CLOCKEVENTS
615 select GENERIC_IRQ_CHIP
616 select GPIOLIB
617 select HAVE_IDE
618 select USE_OF
619 select ZONE_DMA
620 help
621 Support for TI's DaVinci platform.
623 config ARCH_OMAP1
624 bool "TI OMAP1"
625 depends on MMU
626 select ARCH_HAS_HOLES_MEMORYMODEL
627 select ARCH_OMAP
628 select CLKDEV_LOOKUP
629 select CLKSRC_MMIO
630 select GENERIC_CLOCKEVENTS
631 select GENERIC_IRQ_CHIP
632 select GPIOLIB
633 select HAVE_IDE
634 select IRQ_DOMAIN
635 select MULTI_IRQ_HANDLER
636 select NEED_MACH_IO_H if PCCARD
637 select NEED_MACH_MEMORY_H
638 select SPARSE_IRQ
639 help
640 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
642 endchoice
644 menu "Multiple platform selection"
645 depends on ARCH_MULTIPLATFORM
647 comment "CPU Core family selection"
649 config ARCH_MULTI_V4
650 bool "ARMv4 based platforms (FA526)"
651 depends on !ARCH_MULTI_V6_V7
652 select ARCH_MULTI_V4_V5
653 select CPU_FA526
655 config ARCH_MULTI_V4T
656 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
657 depends on !ARCH_MULTI_V6_V7
658 select ARCH_MULTI_V4_V5
659 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
660 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
661 CPU_ARM925T || CPU_ARM940T)
663 config ARCH_MULTI_V5
664 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
665 depends on !ARCH_MULTI_V6_V7
666 select ARCH_MULTI_V4_V5
667 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
668 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
669 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
671 config ARCH_MULTI_V4_V5
672 bool
674 config ARCH_MULTI_V6
675 bool "ARMv6 based platforms (ARM11)"
676 select ARCH_MULTI_V6_V7
677 select CPU_V6K
679 config ARCH_MULTI_V7
680 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
681 default y
682 select ARCH_MULTI_V6_V7
683 select CPU_V7
684 select HAVE_SMP
686 config ARCH_MULTI_V6_V7
687 bool
688 select MIGHT_HAVE_CACHE_L2X0
690 config ARCH_MULTI_CPU_AUTO
691 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
692 select ARCH_MULTI_V5
694 endmenu
696 config ARCH_VIRT
697 bool "Dummy Virtual Machine"
698 depends on ARCH_MULTI_V7
699 select ARM_AMBA
700 select ARM_GIC
701 select ARM_GIC_V2M if PCI
702 select ARM_GIC_V3
703 select ARM_GIC_V3_ITS if PCI
704 select ARM_PSCI
705 select HAVE_ARM_ARCH_TIMER
707 #
708 # This is sorted alphabetically by mach-* pathname. However, plat-*
709 # Kconfigs may be included either alphabetically (according to the
710 # plat- suffix) or along side the corresponding mach-* source.
711 #
712 source "arch/arm/mach-mvebu/Kconfig"
714 source "arch/arm/mach-actions/Kconfig"
716 source "arch/arm/mach-alpine/Kconfig"
718 source "arch/arm/mach-artpec/Kconfig"
720 source "arch/arm/mach-asm9260/Kconfig"
722 source "arch/arm/mach-at91/Kconfig"
724 source "arch/arm/mach-axxia/Kconfig"
726 source "arch/arm/mach-bcm/Kconfig"
728 source "arch/arm/mach-berlin/Kconfig"
730 source "arch/arm/mach-clps711x/Kconfig"
732 source "arch/arm/mach-cns3xxx/Kconfig"
734 source "arch/arm/mach-davinci/Kconfig"
736 source "arch/arm/mach-digicolor/Kconfig"
738 source "arch/arm/mach-dove/Kconfig"
740 source "arch/arm/mach-ep93xx/Kconfig"
742 source "arch/arm/mach-footbridge/Kconfig"
744 source "arch/arm/mach-gemini/Kconfig"
746 source "arch/arm/mach-highbank/Kconfig"
748 source "arch/arm/mach-hisi/Kconfig"
750 source "arch/arm/mach-integrator/Kconfig"
752 source "arch/arm/mach-iop32x/Kconfig"
754 source "arch/arm/mach-iop33x/Kconfig"
756 source "arch/arm/mach-iop13xx/Kconfig"
758 source "arch/arm/mach-ixp4xx/Kconfig"
760 source "arch/arm/mach-keystone/Kconfig"
762 source "arch/arm/mach-ks8695/Kconfig"
764 source "arch/arm/mach-meson/Kconfig"
766 source "arch/arm/mach-moxart/Kconfig"
768 source "arch/arm/mach-aspeed/Kconfig"
770 source "arch/arm/mach-mv78xx0/Kconfig"
772 source "arch/arm/mach-imx/Kconfig"
774 source "arch/arm/mach-mediatek/Kconfig"
776 source "arch/arm/mach-mxs/Kconfig"
778 source "arch/arm/mach-netx/Kconfig"
780 source "arch/arm/mach-nomadik/Kconfig"
782 source "arch/arm/mach-nspire/Kconfig"
784 source "arch/arm/plat-omap/Kconfig"
786 source "arch/arm/mach-omap1/Kconfig"
788 source "arch/arm/mach-omap2/Kconfig"
790 source "arch/arm/mach-orion5x/Kconfig"
792 source "arch/arm/mach-picoxcell/Kconfig"
794 source "arch/arm/mach-pxa/Kconfig"
795 source "arch/arm/plat-pxa/Kconfig"
797 source "arch/arm/mach-mmp/Kconfig"
799 source "arch/arm/mach-oxnas/Kconfig"
801 source "arch/arm/mach-qcom/Kconfig"
803 source "arch/arm/mach-realview/Kconfig"
805 source "arch/arm/mach-rockchip/Kconfig"
807 source "arch/arm/mach-sa1100/Kconfig"
809 source "arch/arm/mach-socfpga/Kconfig"
811 source "arch/arm/mach-spear/Kconfig"
813 source "arch/arm/mach-sti/Kconfig"
815 source "arch/arm/mach-stm32/Kconfig"
817 source "arch/arm/mach-s3c24xx/Kconfig"
819 source "arch/arm/mach-s3c64xx/Kconfig"
821 source "arch/arm/mach-s5pv210/Kconfig"
823 source "arch/arm/mach-exynos/Kconfig"
824 source "arch/arm/plat-samsung/Kconfig"
826 source "arch/arm/mach-shmobile/Kconfig"
828 source "arch/arm/mach-sunxi/Kconfig"
830 source "arch/arm/mach-prima2/Kconfig"
832 source "arch/arm/mach-tango/Kconfig"
834 source "arch/arm/mach-tegra/Kconfig"
836 source "arch/arm/mach-u300/Kconfig"
838 source "arch/arm/mach-uniphier/Kconfig"
840 source "arch/arm/mach-ux500/Kconfig"
842 source "arch/arm/mach-versatile/Kconfig"
844 source "arch/arm/mach-vexpress/Kconfig"
845 source "arch/arm/plat-versatile/Kconfig"
847 source "arch/arm/mach-vt8500/Kconfig"
849 source "arch/arm/mach-w90x900/Kconfig"
851 source "arch/arm/mach-zx/Kconfig"
853 source "arch/arm/mach-zynq/Kconfig"
855 # ARMv7-M architecture
856 config ARCH_EFM32
857 bool "Energy Micro efm32"
858 depends on ARM_SINGLE_ARMV7M
859 select GPIOLIB
860 help
861 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
862 processors.
864 config ARCH_LPC18XX
865 bool "NXP LPC18xx/LPC43xx"
866 depends on ARM_SINGLE_ARMV7M
867 select ARCH_HAS_RESET_CONTROLLER
868 select ARM_AMBA
869 select CLKSRC_LPC32XX
870 select PINCTRL
871 help
872 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
873 high performance microcontrollers.
875 config ARCH_MPS2
876 bool "ARM MPS2 platform"
877 depends on ARM_SINGLE_ARMV7M
878 select ARM_AMBA
879 select CLKSRC_MPS2
880 help
881 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
882 with a range of available cores like Cortex-M3/M4/M7.
884 Please, note that depends which Application Note is used memory map
885 for the platform may vary, so adjustment of RAM base might be needed.
887 # Definitions to make life easier
888 config ARCH_ACORN
889 bool
891 config PLAT_IOP
892 bool
893 select GENERIC_CLOCKEVENTS
895 config PLAT_ORION
896 bool
897 select CLKSRC_MMIO
898 select COMMON_CLK
899 select GENERIC_IRQ_CHIP
900 select IRQ_DOMAIN
902 config PLAT_ORION_LEGACY
903 bool
904 select PLAT_ORION
906 config PLAT_PXA
907 bool
909 config PLAT_VERSATILE
910 bool
912 source "arch/arm/firmware/Kconfig"
914 source arch/arm/mm/Kconfig
916 config IWMMXT
917 bool "Enable iWMMXt support"
918 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
919 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
920 help
921 Enable support for iWMMXt context switching at run time if
922 running on a CPU that supports it.
924 config MULTI_IRQ_HANDLER
925 bool
926 help
927 Allow each machine to specify it's own IRQ handler at run time.
929 if !MMU
930 source "arch/arm/Kconfig-nommu"
931 endif
933 config PJ4B_ERRATA_4742
934 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
935 depends on CPU_PJ4B && MACH_ARMADA_370
936 default y
937 help
938 When coming out of either a Wait for Interrupt (WFI) or a Wait for
939 Event (WFE) IDLE states, a specific timing sensitivity exists between
940 the retiring WFI/WFE instructions and the newly issued subsequent
941 instructions. This sensitivity can result in a CPU hang scenario.
942 Workaround:
943 The software must insert either a Data Synchronization Barrier (DSB)
944 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
945 instruction
947 config ARM_ERRATA_326103
948 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
949 depends on CPU_V6
950 help
951 Executing a SWP instruction to read-only memory does not set bit 11
952 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
953 treat the access as a read, preventing a COW from occurring and
954 causing the faulting task to livelock.
956 config ARM_ERRATA_411920
957 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
958 depends on CPU_V6 || CPU_V6K
959 help
960 Invalidation of the Instruction Cache operation can
961 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
962 It does not affect the MPCore. This option enables the ARM Ltd.
963 recommended workaround.
965 config ARM_ERRATA_430973
966 bool "ARM errata: Stale prediction on replaced interworking branch"
967 depends on CPU_V7
968 help
969 This option enables the workaround for the 430973 Cortex-A8
970 r1p* erratum. If a code sequence containing an ARM/Thumb
971 interworking branch is replaced with another code sequence at the
972 same virtual address, whether due to self-modifying code or virtual
973 to physical address re-mapping, Cortex-A8 does not recover from the
974 stale interworking branch prediction. This results in Cortex-A8
975 executing the new code sequence in the incorrect ARM or Thumb state.
976 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
977 and also flushes the branch target cache at every context switch.
978 Note that setting specific bits in the ACTLR register may not be
979 available in non-secure mode.
981 config ARM_ERRATA_458693
982 bool "ARM errata: Processor deadlock when a false hazard is created"
983 depends on CPU_V7
984 depends on !ARCH_MULTIPLATFORM
985 help
986 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
987 erratum. For very specific sequences of memory operations, it is
988 possible for a hazard condition intended for a cache line to instead
989 be incorrectly associated with a different cache line. This false
990 hazard might then cause a processor deadlock. The workaround enables
991 the L1 caching of the NEON accesses and disables the PLD instruction
992 in the ACTLR register. Note that setting specific bits in the ACTLR
993 register may not be available in non-secure mode.
995 config ARM_ERRATA_460075
996 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
997 depends on CPU_V7
998 depends on !ARCH_MULTIPLATFORM
999 help
1000 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1001 erratum. Any asynchronous access to the L2 cache may encounter a
1002 situation in which recent store transactions to the L2 cache are lost
1003 and overwritten with stale memory contents from external memory. The
1004 workaround disables the write-allocate mode for the L2 cache via the
1005 ACTLR register. Note that setting specific bits in the ACTLR register
1006 may not be available in non-secure mode.
1008 config ARM_ERRATA_742230
1009 bool "ARM errata: DMB operation may be faulty"
1010 depends on CPU_V7 && SMP
1011 depends on !ARCH_MULTIPLATFORM
1012 help
1013 This option enables the workaround for the 742230 Cortex-A9
1014 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1015 between two write operations may not ensure the correct visibility
1016 ordering of the two writes. This workaround sets a specific bit in
1017 the diagnostic register of the Cortex-A9 which causes the DMB
1018 instruction to behave as a DSB, ensuring the correct behaviour of
1019 the two writes.
1021 config ARM_ERRATA_742231
1022 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1023 depends on CPU_V7 && SMP
1024 depends on !ARCH_MULTIPLATFORM
1025 help
1026 This option enables the workaround for the 742231 Cortex-A9
1027 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1028 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1029 accessing some data located in the same cache line, may get corrupted
1030 data due to bad handling of the address hazard when the line gets
1031 replaced from one of the CPUs at the same time as another CPU is
1032 accessing it. This workaround sets specific bits in the diagnostic
1033 register of the Cortex-A9 which reduces the linefill issuing
1034 capabilities of the processor.
1036 config ARM_ERRATA_643719
1037 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1038 depends on CPU_V7 && SMP
1039 default y
1040 help
1041 This option enables the workaround for the 643719 Cortex-A9 (prior to
1042 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1043 register returns zero when it should return one. The workaround
1044 corrects this value, ensuring cache maintenance operations which use
1045 it behave as intended and avoiding data corruption.
1047 config ARM_ERRATA_720789
1048 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1049 depends on CPU_V7
1050 help
1051 This option enables the workaround for the 720789 Cortex-A9 (prior to
1052 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1053 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1054 As a consequence of this erratum, some TLB entries which should be
1055 invalidated are not, resulting in an incoherency in the system page
1056 tables. The workaround changes the TLB flushing routines to invalidate
1057 entries regardless of the ASID.
1059 config ARM_ERRATA_743622
1060 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1061 depends on CPU_V7
1062 depends on !ARCH_MULTIPLATFORM
1063 help
1064 This option enables the workaround for the 743622 Cortex-A9
1065 (r2p*) erratum. Under very rare conditions, a faulty
1066 optimisation in the Cortex-A9 Store Buffer may lead to data
1067 corruption. This workaround sets a specific bit in the diagnostic
1068 register of the Cortex-A9 which disables the Store Buffer
1069 optimisation, preventing the defect from occurring. This has no
1070 visible impact on the overall performance or power consumption of the
1071 processor.
1073 config ARM_ERRATA_751472
1074 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1075 depends on CPU_V7
1076 depends on !ARCH_MULTIPLATFORM
1077 help
1078 This option enables the workaround for the 751472 Cortex-A9 (prior
1079 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1080 completion of a following broadcasted operation if the second
1081 operation is received by a CPU before the ICIALLUIS has completed,
1082 potentially leading to corrupted entries in the cache or TLB.
1084 config ARM_ERRATA_754322
1085 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1086 depends on CPU_V7
1087 help
1088 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1089 r3p*) erratum. A speculative memory access may cause a page table walk
1090 which starts prior to an ASID switch but completes afterwards. This
1091 can populate the micro-TLB with a stale entry which may be hit with
1092 the new ASID. This workaround places two dsb instructions in the mm
1093 switching code so that no page table walks can cross the ASID switch.
1095 config ARM_ERRATA_754327
1096 bool "ARM errata: no automatic Store Buffer drain"
1097 depends on CPU_V7 && SMP
1098 help
1099 This option enables the workaround for the 754327 Cortex-A9 (prior to
1100 r2p0) erratum. The Store Buffer does not have any automatic draining
1101 mechanism and therefore a livelock may occur if an external agent
1102 continuously polls a memory location waiting to observe an update.
1103 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1104 written polling loops from denying visibility of updates to memory.
1106 config ARM_ERRATA_364296
1107 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1108 depends on CPU_V6
1109 help
1110 This options enables the workaround for the 364296 ARM1136
1111 r0p2 erratum (possible cache data corruption with
1112 hit-under-miss enabled). It sets the undocumented bit 31 in
1113 the auxiliary control register and the FI bit in the control
1114 register, thus disabling hit-under-miss without putting the
1115 processor into full low interrupt latency mode. ARM11MPCore
1116 is not affected.
1118 config ARM_ERRATA_764369
1119 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1120 depends on CPU_V7 && SMP
1121 help
1122 This option enables the workaround for erratum 764369
1123 affecting Cortex-A9 MPCore with two or more processors (all
1124 current revisions). Under certain timing circumstances, a data
1125 cache line maintenance operation by MVA targeting an Inner
1126 Shareable memory region may fail to proceed up to either the
1127 Point of Coherency or to the Point of Unification of the
1128 system. This workaround adds a DSB instruction before the
1129 relevant cache maintenance functions and sets a specific bit
1130 in the diagnostic control register of the SCU.
1132 config ARM_ERRATA_775420
1133 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1134 depends on CPU_V7
1135 help
1136 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1137 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1138 operation aborts with MMU exception, it might cause the processor
1139 to deadlock. This workaround puts DSB before executing ISB if
1140 an abort may occur on cache maintenance.
1142 config ARM_ERRATA_798181
1143 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1144 depends on CPU_V7 && SMP
1145 help
1146 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1147 adequately shooting down all use of the old entries. This
1148 option enables the Linux kernel workaround for this erratum
1149 which sends an IPI to the CPUs that are running the same ASID
1150 as the one being invalidated.
1152 config ARM_ERRATA_773022
1153 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1154 depends on CPU_V7
1155 help
1156 This option enables the workaround for the 773022 Cortex-A15
1157 (up to r0p4) erratum. In certain rare sequences of code, the
1158 loop buffer may deliver incorrect instructions. This
1159 workaround disables the loop buffer to avoid the erratum.
1161 config ARM_ERRATA_818325_852422
1162 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1163 depends on CPU_V7
1164 help
1165 This option enables the workaround for:
1166 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1167 instruction might deadlock. Fixed in r0p1.
1168 - Cortex-A12 852422: Execution of a sequence of instructions might
1169 lead to either a data corruption or a CPU deadlock. Not fixed in
1170 any Cortex-A12 cores yet.
1171 This workaround for all both errata involves setting bit[12] of the
1172 Feature Register. This bit disables an optimisation applied to a
1173 sequence of 2 instructions that use opposing condition codes.
1175 config ARM_ERRATA_821420
1176 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1177 depends on CPU_V7
1178 help
1179 This option enables the workaround for the 821420 Cortex-A12
1180 (all revs) erratum. In very rare timing conditions, a sequence
1181 of VMOV to Core registers instructions, for which the second
1182 one is in the shadow of a branch or abort, can lead to a
1183 deadlock when the VMOV instructions are issued out-of-order.
1185 config ARM_ERRATA_825619
1186 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1187 depends on CPU_V7
1188 help
1189 This option enables the workaround for the 825619 Cortex-A12
1190 (all revs) erratum. Within rare timing constraints, executing a
1191 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1192 and Device/Strongly-Ordered loads and stores might cause deadlock
1194 config ARM_ERRATA_852421
1195 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1196 depends on CPU_V7
1197 help
1198 This option enables the workaround for the 852421 Cortex-A17
1199 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1200 execution of a DMB ST instruction might fail to properly order
1201 stores from GroupA and stores from GroupB.
1203 config ARM_ERRATA_852423
1204 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1205 depends on CPU_V7
1206 help
1207 This option enables the workaround for:
1208 - Cortex-A17 852423: Execution of a sequence of instructions might
1209 lead to either a data corruption or a CPU deadlock. Not fixed in
1210 any Cortex-A17 cores yet.
1211 This is identical to Cortex-A12 erratum 852422. It is a separate
1212 config option from the A12 erratum due to the way errata are checked
1213 for and handled.
1215 endmenu
1217 source "arch/arm/common/Kconfig"
1219 menu "Bus support"
1221 config ISA
1222 bool
1223 help
1224 Find out whether you have ISA slots on your motherboard. ISA is the
1225 name of a bus system, i.e. the way the CPU talks to the other stuff
1226 inside your box. Other bus systems are PCI, EISA, MicroChannel
1227 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1228 newer boards don't support it. If you have ISA, say Y, otherwise N.
1230 # Select ISA DMA controller support
1231 config ISA_DMA
1232 bool
1233 select ISA_DMA_API
1235 # Select ISA DMA interface
1236 config ISA_DMA_API
1237 bool
1239 config PCI
1240 bool "PCI support" if MIGHT_HAVE_PCI
1241 help
1242 Find out whether you have a PCI motherboard. PCI is the name of a
1243 bus system, i.e. the way the CPU talks to the other stuff inside
1244 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1245 VESA. If you have PCI, say Y, otherwise N.
1247 config PCI_DOMAINS
1248 bool
1249 depends on PCI
1251 config PCI_DOMAINS_GENERIC
1252 def_bool PCI_DOMAINS
1254 config PCI_NANOENGINE
1255 bool "BSE nanoEngine PCI support"
1256 depends on SA1100_NANOENGINE
1257 help
1258 Enable PCI on the BSE nanoEngine board.
1260 config PCI_SYSCALL
1261 def_bool PCI
1263 config PCI_HOST_ITE8152
1264 bool
1265 depends on PCI && MACH_ARMCORE
1266 default y
1267 select DMABOUNCE
1269 source "drivers/pci/Kconfig"
1271 source "drivers/pcmcia/Kconfig"
1273 endmenu
1275 menu "Kernel Features"
1277 config HAVE_SMP
1278 bool
1279 help
1280 This option should be selected by machines which have an SMP-
1281 capable CPU.
1283 The only effect of this option is to make the SMP-related
1284 options available to the user for configuration.
1286 config SMP
1287 bool "Symmetric Multi-Processing"
1288 depends on CPU_V6K || CPU_V7
1289 depends on GENERIC_CLOCKEVENTS
1290 depends on HAVE_SMP
1291 depends on MMU || ARM_MPU
1292 select IRQ_WORK
1293 help
1294 This enables support for systems with more than one CPU. If you have
1295 a system with only one CPU, say N. If you have a system with more
1296 than one CPU, say Y.
1298 If you say N here, the kernel will run on uni- and multiprocessor
1299 machines, but will use only one CPU of a multiprocessor machine. If
1300 you say Y here, the kernel will run on many, but not all,
1301 uniprocessor machines. On a uniprocessor machine, the kernel
1302 will run faster if you say N here.
1304 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1305 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1306 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1308 If you don't know what to do here, say N.
1310 config SMP_ON_UP
1311 bool "Allow booting SMP kernel on uniprocessor systems"
1312 depends on SMP && !XIP_KERNEL && MMU
1313 default y
1314 help
1315 SMP kernels contain instructions which fail on non-SMP processors.
1316 Enabling this option allows the kernel to modify itself to make
1317 these instructions safe. Disabling it allows about 1K of space
1318 savings.
1320 If you don't know what to do here, say Y.
1322 config ARM_CPU_TOPOLOGY
1323 bool "Support cpu topology definition"
1324 depends on SMP && CPU_V7
1325 default y
1326 help
1327 Support ARM cpu topology definition. The MPIDR register defines
1328 affinity between processors which is then used to describe the cpu
1329 topology of an ARM System.
1331 config SCHED_MC
1332 bool "Multi-core scheduler support"
1333 depends on ARM_CPU_TOPOLOGY
1334 help
1335 Multi-core scheduler support improves the CPU scheduler's decision
1336 making when dealing with multi-core CPU chips at a cost of slightly
1337 increased overhead in some places. If unsure say N here.
1339 config SCHED_SMT
1340 bool "SMT scheduler support"
1341 depends on ARM_CPU_TOPOLOGY
1342 help
1343 Improves the CPU scheduler's decision making when dealing with
1344 MultiThreading at a cost of slightly increased overhead in some
1345 places. If unsure say N here.
1347 config HAVE_ARM_SCU
1348 bool
1349 help
1350 This option enables support for the ARM system coherency unit
1352 config HAVE_ARM_ARCH_TIMER
1353 bool "Architected timer support"
1354 depends on CPU_V7
1355 select ARM_ARCH_TIMER
1356 select GENERIC_CLOCKEVENTS
1357 help
1358 This option enables support for the ARM architected timer
1360 config HAVE_ARM_TWD
1361 bool
1362 select TIMER_OF if OF
1363 help
1364 This options enables support for the ARM timer and watchdog unit
1366 config MCPM
1367 bool "Multi-Cluster Power Management"
1368 depends on CPU_V7 && SMP
1369 help
1370 This option provides the common power management infrastructure
1371 for (multi-)cluster based systems, such as big.LITTLE based
1372 systems.
1374 config MCPM_QUAD_CLUSTER
1375 bool
1376 depends on MCPM
1377 help
1378 To avoid wasting resources unnecessarily, MCPM only supports up
1379 to 2 clusters by default.
1380 Platforms with 3 or 4 clusters that use MCPM must select this
1381 option to allow the additional clusters to be managed.
1383 config BIG_LITTLE
1384 bool "big.LITTLE support (Experimental)"
1385 depends on CPU_V7 && SMP
1386 select MCPM
1387 help
1388 This option enables support selections for the big.LITTLE
1389 system architecture.
1391 config BL_SWITCHER
1392 bool "big.LITTLE switcher support"
1393 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1394 select CPU_PM
1395 help
1396 The big.LITTLE "switcher" provides the core functionality to
1397 transparently handle transition between a cluster of A15's
1398 and a cluster of A7's in a big.LITTLE system.
1400 config BL_SWITCHER_DUMMY_IF
1401 tristate "Simple big.LITTLE switcher user interface"
1402 depends on BL_SWITCHER && DEBUG_KERNEL
1403 help
1404 This is a simple and dummy char dev interface to control
1405 the big.LITTLE switcher core code. It is meant for
1406 debugging purposes only.
1408 choice
1409 prompt "Memory split"
1410 depends on MMU
1411 default VMSPLIT_3G
1412 help
1413 Select the desired split between kernel and user memory.
1415 If you are not absolutely sure what you are doing, leave this
1416 option alone!
1418 config VMSPLIT_3G
1419 bool "3G/1G user/kernel split"
1420 config VMSPLIT_3G_OPT
1421 depends on !ARM_LPAE
1422 bool "3G/1G user/kernel split (for full 1G low memory)"
1423 config VMSPLIT_2G
1424 bool "2G/2G user/kernel split"
1425 config VMSPLIT_1G
1426 bool "1G/3G user/kernel split"
1427 endchoice
1429 config PAGE_OFFSET
1430 hex
1431 default PHYS_OFFSET if !MMU
1432 default 0x40000000 if VMSPLIT_1G
1433 default 0x80000000 if VMSPLIT_2G
1434 default 0xB0000000 if VMSPLIT_3G_OPT
1435 default 0xC0000000
1437 config NR_CPUS
1438 int "Maximum number of CPUs (2-32)"
1439 range 2 32
1440 depends on SMP
1441 default "4"
1443 config HOTPLUG_CPU
1444 bool "Support for hot-pluggable CPUs"
1445 depends on SMP
1446 help
1447 Say Y here to experiment with turning CPUs off and on. CPUs
1448 can be controlled through /sys/devices/system/cpu.
1450 config ARM_PSCI
1451 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1452 depends on HAVE_ARM_SMCCC
1453 select ARM_PSCI_FW
1454 help
1455 Say Y here if you want Linux to communicate with system firmware
1456 implementing the PSCI specification for CPU-centric power
1457 management operations described in ARM document number ARM DEN
1458 0022A ("Power State Coordination Interface System Software on
1459 ARM processors").
1461 # The GPIO number here must be sorted by descending number. In case of
1462 # a multiplatform kernel, we just want the highest value required by the
1463 # selected platforms.
1464 config ARCH_NR_GPIO
1465 int
1466 default 2048 if ARCH_SOCFPGA
1467 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1468 ARCH_ZYNQ
1469 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1470 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1471 default 416 if ARCH_SUNXI
1472 default 392 if ARCH_U8500
1473 default 352 if ARCH_VT8500
1474 default 288 if ARCH_ROCKCHIP
1475 default 264 if MACH_H4700
1476 default 0
1477 help
1478 Maximum number of GPIOs in the system.
1480 If unsure, leave the default value.
1482 source kernel/Kconfig.preempt
1484 config HZ_FIXED
1485 int
1486 default 200 if ARCH_EBSA110
1487 default 128 if SOC_AT91RM9200
1488 default 0
1490 choice
1491 depends on HZ_FIXED = 0
1492 prompt "Timer frequency"
1494 config HZ_100
1495 bool "100 Hz"
1497 config HZ_200
1498 bool "200 Hz"
1500 config HZ_250
1501 bool "250 Hz"
1503 config HZ_300
1504 bool "300 Hz"
1506 config HZ_500
1507 bool "500 Hz"
1509 config HZ_1000
1510 bool "1000 Hz"
1512 endchoice
1514 config HZ
1515 int
1516 default HZ_FIXED if HZ_FIXED != 0
1517 default 100 if HZ_100
1518 default 200 if HZ_200
1519 default 250 if HZ_250
1520 default 300 if HZ_300
1521 default 500 if HZ_500
1522 default 1000
1524 config SCHED_HRTICK
1525 def_bool HIGH_RES_TIMERS
1527 config THUMB2_KERNEL
1528 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1529 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1530 default y if CPU_THUMBONLY
1531 select ARM_UNWIND
1532 help
1533 By enabling this option, the kernel will be compiled in
1534 Thumb-2 mode.
1536 If unsure, say N.
1538 config THUMB2_AVOID_R_ARM_THM_JUMP11
1539 bool "Work around buggy Thumb-2 short branch relocations in gas"
1540 depends on THUMB2_KERNEL && MODULES
1541 default y
1542 help
1543 Various binutils versions can resolve Thumb-2 branches to
1544 locally-defined, preemptible global symbols as short-range "b.n"
1545 branch instructions.
1547 This is a problem, because there's no guarantee the final
1548 destination of the symbol, or any candidate locations for a
1549 trampoline, are within range of the branch. For this reason, the
1550 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1551 relocation in modules at all, and it makes little sense to add
1552 support.
1554 The symptom is that the kernel fails with an "unsupported
1555 relocation" error when loading some modules.
1557 Until fixed tools are available, passing
1558 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1559 code which hits this problem, at the cost of a bit of extra runtime
1560 stack usage in some cases.
1562 The problem is described in more detail at:
1563 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1565 Only Thumb-2 kernels are affected.
1567 Unless you are sure your tools don't have this problem, say Y.
1569 config ARM_PATCH_IDIV
1570 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1571 depends on CPU_32v7 && !XIP_KERNEL
1572 default y
1573 help
1574 The ARM compiler inserts calls to __aeabi_idiv() and
1575 __aeabi_uidiv() when it needs to perform division on signed
1576 and unsigned integers. Some v7 CPUs have support for the sdiv
1577 and udiv instructions that can be used to implement those
1578 functions.
1580 Enabling this option allows the kernel to modify itself to
1581 replace the first two instructions of these library functions
1582 with the sdiv or udiv plus "bx lr" instructions when the CPU
1583 it is running on supports them. Typically this will be faster
1584 and less power intensive than running the original library
1585 code to do integer division.
1587 config AEABI
1588 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1589 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1590 help
1591 This option allows for the kernel to be compiled using the latest
1592 ARM ABI (aka EABI). This is only useful if you are using a user
1593 space environment that is also compiled with EABI.
1595 Since there are major incompatibilities between the legacy ABI and
1596 EABI, especially with regard to structure member alignment, this
1597 option also changes the kernel syscall calling convention to
1598 disambiguate both ABIs and allow for backward compatibility support
1599 (selected with CONFIG_OABI_COMPAT).
1601 To use this you need GCC version 4.0.0 or later.
1603 config OABI_COMPAT
1604 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1605 depends on AEABI && !THUMB2_KERNEL
1606 help
1607 This option preserves the old syscall interface along with the
1608 new (ARM EABI) one. It also provides a compatibility layer to
1609 intercept syscalls that have structure arguments which layout
1610 in memory differs between the legacy ABI and the new ARM EABI
1611 (only for non "thumb" binaries). This option adds a tiny
1612 overhead to all syscalls and produces a slightly larger kernel.
1614 The seccomp filter system will not be available when this is
1615 selected, since there is no way yet to sensibly distinguish
1616 between calling conventions during filtering.
1618 If you know you'll be using only pure EABI user space then you
1619 can say N here. If this option is not selected and you attempt
1620 to execute a legacy ABI binary then the result will be
1621 UNPREDICTABLE (in fact it can be predicted that it won't work
1622 at all). If in doubt say N.
1624 config ARCH_HAS_HOLES_MEMORYMODEL
1625 bool
1627 config ARCH_SPARSEMEM_ENABLE
1628 bool
1630 config ARCH_SPARSEMEM_DEFAULT
1631 def_bool ARCH_SPARSEMEM_ENABLE
1633 config ARCH_SELECT_MEMORY_MODEL
1634 def_bool ARCH_SPARSEMEM_ENABLE
1636 config HAVE_ARCH_PFN_VALID
1637 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1639 config HAVE_GENERIC_GUP
1640 def_bool y
1641 depends on ARM_LPAE
1643 config HIGHMEM
1644 bool "High Memory Support"
1645 depends on MMU
1646 help
1647 The address space of ARM processors is only 4 Gigabytes large
1648 and it has to accommodate user address space, kernel address
1649 space as well as some memory mapped IO. That means that, if you
1650 have a large amount of physical memory and/or IO, not all of the
1651 memory can be "permanently mapped" by the kernel. The physical
1652 memory that is not permanently mapped is called "high memory".
1654 Depending on the selected kernel/user memory split, minimum
1655 vmalloc space and actual amount of RAM, you may not need this
1656 option which should result in a slightly faster kernel.
1658 If unsure, say n.
1660 config HIGHPTE
1661 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1662 depends on HIGHMEM
1663 default y
1664 help
1665 The VM uses one page of physical memory for each page table.
1666 For systems with a lot of processes, this can use a lot of
1667 precious low memory, eventually leading to low memory being
1668 consumed by page tables. Setting this option will allow
1669 user-space 2nd level page tables to reside in high memory.
1671 config CPU_SW_DOMAIN_PAN
1672 bool "Enable use of CPU domains to implement privileged no-access"
1673 depends on MMU && !ARM_LPAE
1674 default y
1675 help
1676 Increase kernel security by ensuring that normal kernel accesses
1677 are unable to access userspace addresses. This can help prevent
1678 use-after-free bugs becoming an exploitable privilege escalation
1679 by ensuring that magic values (such as LIST_POISON) will always
1680 fault when dereferenced.
1682 CPUs with low-vector mappings use a best-efforts implementation.
1683 Their lower 1MB needs to remain accessible for the vectors, but
1684 the remainder of userspace will become appropriately inaccessible.
1686 config HW_PERF_EVENTS
1687 def_bool y
1688 depends on ARM_PMU
1690 config SYS_SUPPORTS_HUGETLBFS
1691 def_bool y
1692 depends on ARM_LPAE
1694 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1695 def_bool y
1696 depends on ARM_LPAE
1698 config ARCH_WANT_GENERAL_HUGETLB
1699 def_bool y
1701 config ARM_MODULE_PLTS
1702 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1703 depends on MODULES
1704 help
1705 Allocate PLTs when loading modules so that jumps and calls whose
1706 targets are too far away for their relative offsets to be encoded
1707 in the instructions themselves can be bounced via veneers in the
1708 module's PLT. This allows modules to be allocated in the generic
1709 vmalloc area after the dedicated module memory area has been
1710 exhausted. The modules will use slightly more memory, but after
1711 rounding up to page size, the actual memory footprint is usually
1712 the same.
1714 Say y if you are getting out of memory errors while loading modules
1716 source "mm/Kconfig"
1718 config FORCE_MAX_ZONEORDER
1719 int "Maximum zone order"
1720 default "12" if SOC_AM33XX
1721 default "9" if SA1111 || ARCH_EFM32
1722 default "11"
1723 help
1724 The kernel memory allocator divides physically contiguous memory
1725 blocks into "zones", where each zone is a power of two number of
1726 pages. This option selects the largest power of two that the kernel
1727 keeps in the memory allocator. If you need to allocate very large
1728 blocks of physically contiguous memory, then you may need to
1729 increase this value.
1731 This config option is actually maximum order plus one. For example,
1732 a value of 11 means that the largest free memory block is 2^10 pages.
1734 config ALIGNMENT_TRAP
1735 bool
1736 depends on CPU_CP15_MMU
1737 default y if !ARCH_EBSA110
1738 select HAVE_PROC_CPU if PROC_FS
1739 help
1740 ARM processors cannot fetch/store information which is not
1741 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1742 address divisible by 4. On 32-bit ARM processors, these non-aligned
1743 fetch/store instructions will be emulated in software if you say
1744 here, which has a severe performance impact. This is necessary for
1745 correct operation of some network protocols. With an IP-only
1746 configuration it is safe to say N, otherwise say Y.
1748 config UACCESS_WITH_MEMCPY
1749 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1750 depends on MMU
1751 default y if CPU_FEROCEON
1752 help
1753 Implement faster copy_to_user and clear_user methods for CPU
1754 cores where a 8-word STM instruction give significantly higher
1755 memory write throughput than a sequence of individual 32bit stores.
1757 A possible side effect is a slight increase in scheduling latency
1758 between threads sharing the same address space if they invoke
1759 such copy operations with large buffers.
1761 However, if the CPU data cache is using a write-allocate mode,
1762 this option is unlikely to provide any performance gain.
1764 config SECCOMP
1765 bool
1766 prompt "Enable seccomp to safely compute untrusted bytecode"
1767 ---help---
1768 This kernel feature is useful for number crunching applications
1769 that may need to compute untrusted bytecode during their
1770 execution. By using pipes or other transports made available to
1771 the process as file descriptors supporting the read/write
1772 syscalls, it's possible to isolate those applications in
1773 their own address space using seccomp. Once seccomp is
1774 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1775 and the task is only allowed to execute a few safe syscalls
1776 defined by each seccomp mode.
1778 config SWIOTLB
1779 def_bool y
1781 config IOMMU_HELPER
1782 def_bool SWIOTLB
1784 config PARAVIRT
1785 bool "Enable paravirtualization code"
1786 help
1787 This changes the kernel so it can modify itself when it is run
1788 under a hypervisor, potentially improving performance significantly
1789 over full virtualization.
1791 config PARAVIRT_TIME_ACCOUNTING
1792 bool "Paravirtual steal time accounting"
1793 select PARAVIRT
1794 default n
1795 help
1796 Select this option to enable fine granularity task steal time
1797 accounting. Time spent executing other tasks in parallel with
1798 the current vCPU is discounted from the vCPU power. To account for
1799 that, there can be a small performance impact.
1801 If in doubt, say N here.
1803 config XEN_DOM0
1804 def_bool y
1805 depends on XEN
1807 config XEN
1808 bool "Xen guest support on ARM"
1809 depends on ARM && AEABI && OF
1810 depends on CPU_V7 && !CPU_V6
1811 depends on !GENERIC_ATOMIC64
1812 depends on MMU
1813 select ARCH_DMA_ADDR_T_64BIT
1814 select ARM_PSCI
1815 select SWIOTLB_XEN
1816 select PARAVIRT
1817 help
1818 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1820 endmenu
1822 menu "Boot options"
1824 config USE_OF
1825 bool "Flattened Device Tree support"
1826 select IRQ_DOMAIN
1827 select OF
1828 help
1829 Include support for flattened device tree machine descriptions.
1831 config ATAGS
1832 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1833 default y
1834 help
1835 This is the traditional way of passing data to the kernel at boot
1836 time. If you are solely relying on the flattened device tree (or
1837 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1838 to remove ATAGS support from your kernel binary. If unsure,
1839 leave this to y.
1841 config DEPRECATED_PARAM_STRUCT
1842 bool "Provide old way to pass kernel parameters"
1843 depends on ATAGS
1844 help
1845 This was deprecated in 2001 and announced to live on for 5 years.
1846 Some old boot loaders still use this way.
1848 # Compressed boot loader in ROM. Yes, we really want to ask about
1849 # TEXT and BSS so we preserve their values in the config files.
1850 config ZBOOT_ROM_TEXT
1851 hex "Compressed ROM boot loader base address"
1852 default "0"
1853 help
1854 The physical address at which the ROM-able zImage is to be
1855 placed in the target. Platforms which normally make use of
1856 ROM-able zImage formats normally set this to a suitable
1857 value in their defconfig file.
1859 If ZBOOT_ROM is not enabled, this has no effect.
1861 config ZBOOT_ROM_BSS
1862 hex "Compressed ROM boot loader BSS address"
1863 default "0"
1864 help
1865 The base address of an area of read/write memory in the target
1866 for the ROM-able zImage which must be available while the
1867 decompressor is running. It must be large enough to hold the
1868 entire decompressed kernel plus an additional 128 KiB.
1869 Platforms which normally make use of ROM-able zImage formats
1870 normally set this to a suitable value in their defconfig file.
1872 If ZBOOT_ROM is not enabled, this has no effect.
1874 config ZBOOT_ROM
1875 bool "Compressed boot loader in ROM/flash"
1876 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1877 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1878 help
1879 Say Y here if you intend to execute your compressed kernel image
1880 (zImage) directly from ROM or flash. If unsure, say N.
1882 config ARM_APPENDED_DTB
1883 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1884 depends on OF
1885 help
1886 With this option, the boot code will look for a device tree binary
1887 (DTB) appended to zImage
1888 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1890 This is meant as a backward compatibility convenience for those
1891 systems with a bootloader that can't be upgraded to accommodate
1892 the documented boot protocol using a device tree.
1894 Beware that there is very little in terms of protection against
1895 this option being confused by leftover garbage in memory that might
1896 look like a DTB header after a reboot if no actual DTB is appended
1897 to zImage. Do not leave this option active in a production kernel
1898 if you don't intend to always append a DTB. Proper passing of the
1899 location into r2 of a bootloader provided DTB is always preferable
1900 to this option.
1902 config ARM_ATAG_DTB_COMPAT
1903 bool "Supplement the appended DTB with traditional ATAG information"
1904 depends on ARM_APPENDED_DTB
1905 help
1906 Some old bootloaders can't be updated to a DTB capable one, yet
1907 they provide ATAGs with memory configuration, the ramdisk address,
1908 the kernel cmdline string, etc. Such information is dynamically
1909 provided by the bootloader and can't always be stored in a static
1910 DTB. To allow a device tree enabled kernel to be used with such
1911 bootloaders, this option allows zImage to extract the information
1912 from the ATAG list and store it at run time into the appended DTB.
1914 choice
1915 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1916 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1918 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919 bool "Use bootloader kernel arguments if available"
1920 help
1921 Uses the command-line options passed by the boot loader instead of
1922 the device tree bootargs property. If the boot loader doesn't provide
1923 any, the device tree bootargs property will be used.
1925 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1926 bool "Extend with bootloader kernel arguments"
1927 help
1928 The command-line arguments provided by the boot loader will be
1929 appended to the the device tree bootargs property.
1931 endchoice
1933 config CMDLINE
1934 string "Default kernel command string"
1935 default ""
1936 help
1937 On some architectures (EBSA110 and CATS), there is currently no way
1938 for the boot loader to pass arguments to the kernel. For these
1939 architectures, you should supply some command-line options at build
1940 time by entering them here. As a minimum, you should specify the
1941 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1943 choice
1944 prompt "Kernel command line type" if CMDLINE != ""
1945 default CMDLINE_FROM_BOOTLOADER
1946 depends on ATAGS
1948 config CMDLINE_FROM_BOOTLOADER
1949 bool "Use bootloader kernel arguments if available"
1950 help
1951 Uses the command-line options passed by the boot loader. If
1952 the boot loader doesn't provide any, the default kernel command
1953 string provided in CMDLINE will be used.
1955 config CMDLINE_EXTEND
1956 bool "Extend bootloader kernel arguments"
1957 help
1958 The command-line arguments provided by the boot loader will be
1959 appended to the default kernel command string.
1961 config CMDLINE_FORCE
1962 bool "Always use the default kernel command string"
1963 help
1964 Always use the default kernel command string, even if the boot
1965 loader passes other arguments to the kernel.
1966 This is useful if you cannot or don't want to change the
1967 command-line options your boot loader passes to the kernel.
1968 endchoice
1970 config XIP_KERNEL
1971 bool "Kernel Execute-In-Place from ROM"
1972 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1973 help
1974 Execute-In-Place allows the kernel to run from non-volatile storage
1975 directly addressable by the CPU, such as NOR flash. This saves RAM
1976 space since the text section of the kernel is not loaded from flash
1977 to RAM. Read-write sections, such as the data section and stack,
1978 are still copied to RAM. The XIP kernel is not compressed since
1979 it has to run directly from flash, so it will take more space to
1980 store it. The flash address used to link the kernel object files,
1981 and for storing it, is configuration dependent. Therefore, if you
1982 say Y here, you must know the proper physical address where to
1983 store the kernel image depending on your own flash memory usage.
1985 Also note that the make target becomes "make xipImage" rather than
1986 "make zImage" or "make Image". The final kernel binary to put in
1987 ROM memory will be arch/arm/boot/xipImage.
1989 If unsure, say N.
1991 config XIP_PHYS_ADDR
1992 hex "XIP Kernel Physical Location"
1993 depends on XIP_KERNEL
1994 default "0x00080000"
1995 help
1996 This is the physical address in your flash memory the kernel will
1997 be linked for and stored to. This address is dependent on your
1998 own flash usage.
2000 config XIP_DEFLATED_DATA
2001 bool "Store kernel .data section compressed in ROM"
2002 depends on XIP_KERNEL
2003 select ZLIB_INFLATE
2004 help
2005 Before the kernel is actually executed, its .data section has to be
2006 copied to RAM from ROM. This option allows for storing that data
2007 in compressed form and decompressed to RAM rather than merely being
2008 copied, saving some precious ROM space. A possible drawback is a
2009 slightly longer boot delay.
2011 config KEXEC
2012 bool "Kexec system call (EXPERIMENTAL)"
2013 depends on (!SMP || PM_SLEEP_SMP)
2014 depends on !CPU_V7M
2015 select KEXEC_CORE
2016 help
2017 kexec is a system call that implements the ability to shutdown your
2018 current kernel, and to start another kernel. It is like a reboot
2019 but it is independent of the system firmware. And like a reboot
2020 you can start any kernel with it, not just Linux.
2022 It is an ongoing process to be certain the hardware in a machine
2023 is properly shutdown, so do not be surprised if this code does not
2024 initially work for you.
2026 config ATAGS_PROC
2027 bool "Export atags in procfs"
2028 depends on ATAGS && KEXEC
2029 default y
2030 help
2031 Should the atags used to boot the kernel be exported in an "atags"
2032 file in procfs. Useful with kexec.
2034 config CRASH_DUMP
2035 bool "Build kdump crash kernel (EXPERIMENTAL)"
2036 help
2037 Generate crash dump after being started by kexec. This should
2038 be normally only set in special crash dump kernels which are
2039 loaded in the main kernel with kexec-tools into a specially
2040 reserved region and then later executed after a crash by
2041 kdump/kexec. The crash dump kernel must be compiled to a
2042 memory address not used by the main kernel
2044 For more details see Documentation/kdump/kdump.txt
2046 config AUTO_ZRELADDR
2047 bool "Auto calculation of the decompressed kernel image address"
2048 help
2049 ZRELADDR is the physical address where the decompressed kernel
2050 image will be placed. If AUTO_ZRELADDR is selected, the address
2051 will be determined at run-time by masking the current IP with
2052 0xf8000000. This assumes the zImage being placed in the first 128MB
2053 from start of memory.
2055 config EFI_STUB
2056 bool
2058 config EFI
2059 bool "UEFI runtime support"
2060 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2061 select UCS2_STRING
2062 select EFI_PARAMS_FROM_FDT
2063 select EFI_STUB
2064 select EFI_ARMSTUB
2065 select EFI_RUNTIME_WRAPPERS
2066 ---help---
2067 This option provides support for runtime services provided
2068 by UEFI firmware (such as non-volatile variables, realtime
2069 clock, and platform reset). A UEFI stub is also provided to
2070 allow the kernel to be booted as an EFI application. This
2071 is only useful for kernels that may run on systems that have
2072 UEFI firmware.
2074 config DMI
2075 bool "Enable support for SMBIOS (DMI) tables"
2076 depends on EFI
2077 default y
2078 help
2079 This enables SMBIOS/DMI feature for systems.
2081 This option is only useful on systems that have UEFI firmware.
2082 However, even with this option, the resultant kernel should
2083 continue to boot on existing non-UEFI platforms.
2085 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2086 i.e., the the practice of identifying the platform via DMI to
2087 decide whether certain workarounds for buggy hardware and/or
2088 firmware need to be enabled. This would require the DMI subsystem
2089 to be enabled much earlier than we do on ARM, which is non-trivial.
2091 endmenu
2093 menu "CPU Power Management"
2095 source "drivers/cpufreq/Kconfig"
2097 source "drivers/cpuidle/Kconfig"
2099 endmenu
2101 menu "Floating point emulation"
2103 comment "At least one emulation must be selected"
2105 config FPE_NWFPE
2106 bool "NWFPE math emulation"
2107 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2108 ---help---
2109 Say Y to include the NWFPE floating point emulator in the kernel.
2110 This is necessary to run most binaries. Linux does not currently
2111 support floating point hardware so you need to say Y here even if
2112 your machine has an FPA or floating point co-processor podule.
2114 You may say N here if you are going to load the Acorn FPEmulator
2115 early in the bootup.
2117 config FPE_NWFPE_XP
2118 bool "Support extended precision"
2119 depends on FPE_NWFPE
2120 help
2121 Say Y to include 80-bit support in the kernel floating-point
2122 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2123 Note that gcc does not generate 80-bit operations by default,
2124 so in most cases this option only enlarges the size of the
2125 floating point emulator without any good reason.
2127 You almost surely want to say N here.
2129 config FPE_FASTFPE
2130 bool "FastFPE math emulation (EXPERIMENTAL)"
2131 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2132 ---help---
2133 Say Y here to include the FAST floating point emulator in the kernel.
2134 This is an experimental much faster emulator which now also has full
2135 precision for the mantissa. It does not support any exceptions.
2136 It is very simple, and approximately 3-6 times faster than NWFPE.
2138 It should be sufficient for most programs. It may be not suitable
2139 for scientific calculations, but you have to check this for yourself.
2140 If you do not feel you need a faster FP emulation you should better
2141 choose NWFPE.
2143 config VFP
2144 bool "VFP-format floating point maths"
2145 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2146 help
2147 Say Y to include VFP support code in the kernel. This is needed
2148 if your hardware includes a VFP unit.
2150 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2151 release notes and additional status information.
2153 Say N if your target does not have VFP hardware.
2155 config VFPv3
2156 bool
2157 depends on VFP
2158 default y if CPU_V7
2160 config NEON
2161 bool "Advanced SIMD (NEON) Extension support"
2162 depends on VFPv3 && CPU_V7
2163 help
2164 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2165 Extension.
2167 config KERNEL_MODE_NEON
2168 bool "Support for NEON in kernel mode"
2169 depends on NEON && AEABI
2170 help
2171 Say Y to include support for NEON in kernel mode.
2173 endmenu
2175 menu "Userspace binary formats"
2177 source "fs/Kconfig.binfmt"
2179 endmenu
2181 menu "Power management options"
2183 source "kernel/power/Kconfig"
2185 config ARCH_SUSPEND_POSSIBLE
2186 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2187 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2188 def_bool y
2190 config ARM_CPU_SUSPEND
2191 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2192 depends on ARCH_SUSPEND_POSSIBLE
2194 config ARCH_HIBERNATION_POSSIBLE
2195 bool
2196 depends on MMU
2197 default y if ARCH_SUSPEND_POSSIBLE
2199 endmenu
2201 source "net/Kconfig"
2203 source "drivers/Kconfig"
2205 source "drivers/firmware/Kconfig"
2207 source "fs/Kconfig"
2209 source "arch/arm/Kconfig.debug"
2211 source "security/Kconfig"
2213 source "crypto/Kconfig"
2214 if CRYPTO
2215 source "arch/arm/crypto/Kconfig"
2216 endif
2218 source "lib/Kconfig"
2220 source "arch/arm/kvm/Kconfig"