arch/arm/mach-ixp4xx/goramo_mlr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Goramo MultiLink router platform code
   4  * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/gpio.h>
   9 #include <linux/hdlc.h>
  10 #include <linux/io.h>
  11 #include <linux/irq.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/serial_8250.h>
  15 #include <asm/mach-types.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/flash.h>
  18 #include <asm/mach/pci.h>
  19 #include <asm/system_info.h>
  20
  21 #define SLOT_ETHA               0x0B    /* IDSEL = AD21 */
  22 #define SLOT_ETHB               0x0C    /* IDSEL = AD20 */
  23 #define SLOT_MPCI               0x0D    /* IDSEL = AD19 */
  24 #define SLOT_NEC                0x0E    /* IDSEL = AD18 */
  25
  26 /* GPIO lines */
  27 #define GPIO_SCL                0
  28 #define GPIO_SDA                1
  29 #define GPIO_STR                2
  30 #define GPIO_IRQ_NEC            3
  31 #define GPIO_IRQ_ETHA           4
  32 #define GPIO_IRQ_ETHB           5
  33 #define GPIO_HSS0_DCD_N         6
  34 #define GPIO_HSS1_DCD_N         7
  35 #define GPIO_UART0_DCD          8
  36 #define GPIO_UART1_DCD          9
  37 #define GPIO_HSS0_CTS_N         10
  38 #define GPIO_HSS1_CTS_N         11
  39 #define GPIO_IRQ_MPCI           12
  40 #define GPIO_HSS1_RTS_N         13
  41 #define GPIO_HSS0_RTS_N         14
  42 /* GPIO15 is not connected */
  43
  44 /* Control outputs from 74HC4094 */
  45 #define CONTROL_HSS0_CLK_INT    0
  46 #define CONTROL_HSS1_CLK_INT    1
  47 #define CONTROL_HSS0_DTR_N      2
  48 #define CONTROL_HSS1_DTR_N      3
  49 #define CONTROL_EXT             4
  50 #define CONTROL_AUTO_RESET      5
  51 #define CONTROL_PCI_RESET_N     6
  52 #define CONTROL_EEPROM_WC_N     7
  53
  54 /* offsets from start of flash ROM = 0x50000000 */
  55 #define CFG_ETH0_ADDRESS        0x40 /* 6 bytes */
  56 #define CFG_ETH1_ADDRESS        0x46 /* 6 bytes */
  57 #define CFG_REV                 0x4C /* u32 */
  58 #define CFG_SDRAM_SIZE          0x50 /* u32 */
  59 #define CFG_SDRAM_CONF          0x54 /* u32 */
  60 #define CFG_SDRAM_MODE          0x58 /* u32 */
  61 #define CFG_SDRAM_REFRESH       0x5C /* u32 */
  62
  63 #define CFG_HW_BITS             0x60 /* u32 */
  64 #define  CFG_HW_USB_PORTS       0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
  65 #define  CFG_HW_HAS_PCI_SLOT    0x00000008
  66 #define  CFG_HW_HAS_ETH0        0x00000010
  67 #define  CFG_HW_HAS_ETH1        0x00000020
  68 #define  CFG_HW_HAS_HSS0        0x00000040
  69 #define  CFG_HW_HAS_HSS1        0x00000080
  70 #define  CFG_HW_HAS_UART0       0x00000100
  71 #define  CFG_HW_HAS_UART1       0x00000200
  72 #define  CFG_HW_HAS_EEPROM      0x00000400
  73
  74 #define FLASH_CMD_READ_ARRAY    0xFF
  75 #define FLASH_CMD_READ_ID       0x90
  76 #define FLASH_SER_OFF           0x102 /* 0x81 in 16-bit mode */
  77
  78 static u32 hw_bits = 0xFFFFFFFD;    /* assume all hardware present */;
  79 static u8 control_value;
  80
  81 /*
  82  * FIXME: this is reimplementing I2C bit-bangining. Move this
  83  * over to using driver/i2c/busses/i2c-gpio.c like all other boards
  84  * and register proper I2C device(s) on the bus for this. (See
  85  * other IXP4xx boards for examples.)
  86  */
  87 static void set_scl(u8 value)
  88 {
  89         gpio_set_value(GPIO_SCL, !!value);
  90         udelay(3);
  91 }
  92
  93 static void set_sda(u8 value)
  94 {
  95         gpio_set_value(GPIO_SDA, !!value);
  96         udelay(3);
  97 }
  98
  99 static void set_str(u8 value)
 100 {
 101         gpio_set_value(GPIO_STR, !!value);
 102         udelay(3);
 103 }
 104
 105 static inline void set_control(int line, int value)
 106 {
 107         if (value)
 108                 control_value |=  (1 << line);
 109         else
 110                 control_value &= ~(1 << line);
 111 }
 112
 113
 114 static void output_control(void)
 115 {
 116         int i;
 117
 118         gpio_direction_output(GPIO_SCL, 1);
 119         gpio_direction_output(GPIO_SDA, 1);
 120
 121         for (i = 0; i < 8; i++) {
 122                 set_scl(0);
 123                 set_sda(control_value & (0x80 >> i)); /* MSB first */
 124                 set_scl(1);     /* active edge */
 125         }
 126
 127         set_str(1);
 128         set_str(0);
 129
 130         set_scl(0);
 131         set_sda(1);             /* Be ready for START */
 132         set_scl(1);
 133 }
 134
 135
 136 static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
 137
 138 static int hss_set_clock(int port, unsigned int clock_type)
 139 {
 140         int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
 141
 142         switch (clock_type) {
 143         case CLOCK_DEFAULT:
 144         case CLOCK_EXT:
 145                 set_control(ctrl_int, 0);
 146                 output_control();
 147                 return CLOCK_EXT;
 148
 149         case CLOCK_INT:
 150                 set_control(ctrl_int, 1);
 151                 output_control();
 152                 return CLOCK_INT;
 153
 154         default:
 155                 return -EINVAL;
 156         }
 157 }
 158
 159 static irqreturn_t hss_dcd_irq(int irq, void *pdev)
 160 {
 161         int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
 162         int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
 163         set_carrier_cb_tab[port](pdev, !i);
 164         return IRQ_HANDLED;
 165 }
 166
 167
 168 static int hss_open(int port, void *pdev,
 169                     void (*set_carrier_cb)(void *pdev, int carrier))
 170 {
 171         int i, irq;
 172
 173         if (!port)
 174                 irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
 175         else
 176                 irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
 177
 178         i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
 179         set_carrier_cb(pdev, !i);
 180
 181         set_carrier_cb_tab[!!port] = set_carrier_cb;
 182
 183         if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
 184                 printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
 185                        irq, i);
 186                 return i;
 187         }
 188
 189         set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
 190         output_control();
 191         gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
 192         return 0;
 193 }
 194
 195 static void hss_close(int port, void *pdev)
 196 {
 197         free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
 198                  IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
 199         set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
 200
 201         set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
 202         output_control();
 203         gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
 204 }
 205
 206
 207 /* Flash memory */
 208 static struct flash_platform_data flash_data = {
 209         .map_name       = "cfi_probe",
 210         .width          = 2,
 211 };
 212
 213 static struct resource flash_resource = {
 214         .flags          = IORESOURCE_MEM,
 215 };
 216
 217 static struct platform_device device_flash = {
 218         .name           = "IXP4XX-Flash",
 219         .id             = 0,
 220         .dev            = { .platform_data = &flash_data },
 221         .num_resources  = 1,
 222         .resource       = &flash_resource,
 223 };
 224
 225 /* IXP425 2 UART ports */
 226 static struct resource uart_resources[] = {
 227         {
 228                 .start          = IXP4XX_UART1_BASE_PHYS,
 229                 .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
 230                 .flags          = IORESOURCE_MEM,
 231         },
 232         {
 233                 .start          = IXP4XX_UART2_BASE_PHYS,
 234                 .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
 235                 .flags          = IORESOURCE_MEM,
 236         }
 237 };
 238
 239 static struct plat_serial8250_port uart_data[] = {
 240         {
 241                 .mapbase        = IXP4XX_UART1_BASE_PHYS,
 242                 .membase        = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
 243                         REG_OFFSET,
 244                 .irq            = IRQ_IXP4XX_UART1,
 245                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 246                 .iotype         = UPIO_MEM,
 247                 .regshift       = 2,
 248                 .uartclk        = IXP4XX_UART_XTAL,
 249         },
 250         {
 251                 .mapbase        = IXP4XX_UART2_BASE_PHYS,
 252                 .membase        = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
 253                         REG_OFFSET,
 254                 .irq            = IRQ_IXP4XX_UART2,
 255                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 256                 .iotype         = UPIO_MEM,
 257                 .regshift       = 2,
 258                 .uartclk        = IXP4XX_UART_XTAL,
 259         },
 260         { },
 261 };
 262
 263 static struct platform_device device_uarts = {
 264         .name                   = "serial8250",
 265         .id                     = PLAT8250_DEV_PLATFORM,
 266         .dev.platform_data      = uart_data,
 267         .num_resources          = 2,
 268         .resource               = uart_resources,
 269 };
 270
 271
 272 /* Built-in 10/100 Ethernet MAC interfaces */
 273 static struct eth_plat_info eth_plat[] = {
 274         {
 275                 .phy            = 0,
 276                 .rxq            = 3,
 277                 .txreadyq       = 32,
 278         }, {
 279                 .phy            = 1,
 280                 .rxq            = 4,
 281                 .txreadyq       = 33,
 282         }
 283 };
 284
 285 static struct platform_device device_eth_tab[] = {
 286         {
 287                 .name                   = "ixp4xx_eth",
 288                 .id                     = IXP4XX_ETH_NPEB,
 289                 .dev.platform_data      = eth_plat,
 290         }, {
 291                 .name                   = "ixp4xx_eth",
 292                 .id                     = IXP4XX_ETH_NPEC,
 293                 .dev.platform_data      = eth_plat + 1,
 294         }
 295 };
 296
 297
 298 /* IXP425 2 synchronous serial ports */
 299 static struct hss_plat_info hss_plat[] = {
 300         {
 301                 .set_clock      = hss_set_clock,
 302                 .open           = hss_open,
 303                 .close          = hss_close,
 304                 .txreadyq       = 34,
 305         }, {
 306                 .set_clock      = hss_set_clock,
 307                 .open           = hss_open,
 308                 .close          = hss_close,
 309                 .txreadyq       = 35,
 310         }
 311 };
 312
 313 static struct platform_device device_hss_tab[] = {
 314         {
 315                 .name                   = "ixp4xx_hss",
 316                 .id                     = 0,
 317                 .dev.platform_data      = hss_plat,
 318         }, {
 319                 .name                   = "ixp4xx_hss",
 320                 .id                     = 1,
 321                 .dev.platform_data      = hss_plat + 1,
 322         }
 323 };
 324
 325
 326 static struct platform_device *device_tab[7] __initdata = {
 327         &device_flash,          /* index 0 */
 328 };
 329
 330 static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
 331 {
 332 #ifdef __ARMEB__
 333         return __raw_readb(flash + addr);
 334 #else
 335         return __raw_readb(flash + (addr ^ 3));
 336 #endif
 337 }
 338
 339 static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
 340 {
 341 #ifdef __ARMEB__
 342         return __raw_readw(flash + addr);
 343 #else
 344         return __raw_readw(flash + (addr ^ 2));
 345 #endif
 346 }
 347
 348 static void __init gmlr_init(void)
 349 {
 350         u8 __iomem *flash;
 351         int i, devices = 1; /* flash */
 352
 353         ixp4xx_sys_init();
 354
 355         if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
 356                 printk(KERN_ERR "goramo-mlr: unable to access system"
 357                        " configuration data\n");
 358         else {
 359                 system_rev = __raw_readl(flash + CFG_REV);
 360                 hw_bits = __raw_readl(flash + CFG_HW_BITS);
 361
 362                 for (i = 0; i < ETH_ALEN; i++) {
 363                         eth_plat[0].hwaddr[i] =
 364                                 flash_readb(flash, CFG_ETH0_ADDRESS + i);
 365                         eth_plat[1].hwaddr[i] =
 366                                 flash_readb(flash, CFG_ETH1_ADDRESS + i);
 367                 }
 368
 369                 __raw_writew(FLASH_CMD_READ_ID, flash);
 370                 system_serial_high = flash_readw(flash, FLASH_SER_OFF);
 371                 system_serial_high <<= 16;
 372                 system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
 373                 system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
 374                 system_serial_low <<= 16;
 375                 system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
 376                 __raw_writew(FLASH_CMD_READ_ARRAY, flash);
 377
 378                 iounmap(flash);
 379         }
 380
 381         switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
 382         case CFG_HW_HAS_UART0:
 383                 memset(&uart_data[1], 0, sizeof(uart_data[1]));
 384                 device_uarts.num_resources = 1;
 385                 break;
 386
 387         case CFG_HW_HAS_UART1:
 388                 device_uarts.dev.platform_data = &uart_data[1];
 389                 device_uarts.resource = &uart_resources[1];
 390                 device_uarts.num_resources = 1;
 391                 break;
 392         }
 393         if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
 394                 device_tab[devices++] = &device_uarts; /* max index 1 */
 395
 396         if (hw_bits & CFG_HW_HAS_ETH0)
 397                 device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
 398         if (hw_bits & CFG_HW_HAS_ETH1)
 399                 device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
 400
 401         if (hw_bits & CFG_HW_HAS_HSS0)
 402                 device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
 403         if (hw_bits & CFG_HW_HAS_HSS1)
 404                 device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
 405
 406         gpio_request(GPIO_SCL, "SCL/clock");
 407         gpio_request(GPIO_SDA, "SDA/data");
 408         gpio_request(GPIO_STR, "strobe");
 409         gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS");
 410         gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS");
 411         gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD");
 412         gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD");
 413
 414         gpio_direction_output(GPIO_SCL, 1);
 415         gpio_direction_output(GPIO_SDA, 1);
 416         gpio_direction_output(GPIO_STR, 0);
 417         gpio_direction_output(GPIO_HSS0_RTS_N, 1);
 418         gpio_direction_output(GPIO_HSS1_RTS_N, 1);
 419         gpio_direction_input(GPIO_HSS0_DCD_N);
 420         gpio_direction_input(GPIO_HSS1_DCD_N);
 421         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
 422         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
 423
 424         set_control(CONTROL_HSS0_DTR_N, 1);
 425         set_control(CONTROL_HSS1_DTR_N, 1);
 426         set_control(CONTROL_EEPROM_WC_N, 1);
 427         set_control(CONTROL_PCI_RESET_N, 1);
 428         output_control();
 429
 430         msleep(1);            /* Wait for PCI devices to initialize */
 431
 432         flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
 433         flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
 434
 435         platform_add_devices(device_tab, devices);
 436 }
 437
 438
 439 #ifdef CONFIG_PCI
 440 static void __init gmlr_pci_preinit(void)
 441 {
 442         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
 443         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
 444         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
 445         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
 446         ixp4xx_pci_preinit();
 447 }
 448
 449 static void __init gmlr_pci_postinit(void)
 450 {
 451         if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
 452             (hw_bits & CFG_HW_USB_PORTS) < 5) {
 453                 /* need to adjust number of USB ports on NEC chip */
 454                 u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
 455                 if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
 456                         value &= ~7;
 457                         value |= (hw_bits & CFG_HW_USB_PORTS);
 458                         ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
 459                 }
 460         }
 461 }
 462
 463 static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 464 {
 465         switch(slot) {
 466         case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
 467         case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
 468         case SLOT_NEC:  return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
 469         default:        return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
 470         }
 471 }
 472
 473 static struct hw_pci gmlr_hw_pci __initdata = {
 474         .nr_controllers = 1,
 475         .ops            = &ixp4xx_ops,
 476         .preinit        = gmlr_pci_preinit,
 477         .postinit       = gmlr_pci_postinit,
 478         .setup          = ixp4xx_setup,
 479         .map_irq        = gmlr_map_irq,
 480 };
 481
 482 static int __init gmlr_pci_init(void)
 483 {
 484         if (machine_is_goramo_mlr() &&
 485             (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
 486                 pci_common_init(&gmlr_hw_pci);
 487         return 0;
 488 }
 489
 490 subsys_initcall(gmlr_pci_init);
 491 #endif /* CONFIG_PCI */
 492
 493
 494 MACHINE_START(GORAMO_MLR, "MultiLink")
 495         /* Maintainer: Krzysztof Halasa */
 496         .map_io         = ixp4xx_map_io,
 497         .init_early     = ixp4xx_init_early,
 498         .init_irq       = ixp4xx_init_irq,
 499         .init_time      = ixp4xx_timer_init,
 500         .atag_offset    = 0x100,
 501         .init_machine   = gmlr_init,
 502 #if defined(CONFIG_PCI)
 503         .dma_zone_size  = SZ_64M,
 504 #endif
 505         .restart        = ixp4xx_restart,
 506 MACHINE_END