?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / arch / arm / mach-omap2 / omap_hwmod_54xx_data.c
blob988e7eaa13304e808ea4031b5a9dea80422c1c48
1 /*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
25
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
30
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_54xx.h"
34 #include "cm2_54xx.h"
35 #include "prm54xx.h"
36 #include "i2c.h"
37 #include "wd_timer.h"
38
39 /* Base offset for all OMAP5 interrupts external to MPUSS */
40 #define OMAP54XX_IRQ_GIC_START 32
41
42 /* Base offset for all OMAP5 dma requests */
43 #define OMAP54XX_DMA_REQ_START 1
44
45
46 /*
47 * IP blocks
48 */
49
50 /*
51 * 'dmm' class
52 * instance(s): dmm
53 */
54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
55 .name = "dmm",
56 };
57
58 /* dmm */
59 static struct omap_hwmod omap54xx_dmm_hwmod = {
60 .name = "dmm",
61 .class = &omap54xx_dmm_hwmod_class,
62 .clkdm_name = "emif_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
66 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
67 },
68 },
69 };
70
71 /*
72 * 'l3' class
73 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
74 */
75 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
76 .name = "l3",
77 };
78
79 /* l3_instr */
80 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
81 .name = "l3_instr",
82 .class = &omap54xx_l3_hwmod_class,
83 .clkdm_name = "l3instr_clkdm",
84 .prcm = {
85 .omap4 = {
86 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
87 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
88 .modulemode = MODULEMODE_HWCTRL,
89 },
90 },
91 };
92
93 /* l3_main_1 */
94 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
95 .name = "l3_main_1",
96 .class = &omap54xx_l3_hwmod_class,
97 .clkdm_name = "l3main1_clkdm",
98 .prcm = {
99 .omap4 = {
100 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
101 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
102 },
103 },
104 };
105
106 /* l3_main_2 */
107 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
108 .name = "l3_main_2",
109 .class = &omap54xx_l3_hwmod_class,
110 .clkdm_name = "l3main2_clkdm",
111 .prcm = {
112 .omap4 = {
113 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
114 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
115 },
116 },
117 };
118
119 /* l3_main_3 */
120 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
121 .name = "l3_main_3",
122 .class = &omap54xx_l3_hwmod_class,
123 .clkdm_name = "l3instr_clkdm",
124 .prcm = {
125 .omap4 = {
126 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
127 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
128 .modulemode = MODULEMODE_HWCTRL,
129 },
130 },
131 };
132
133 /*
134 * 'l4' class
135 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
136 */
137 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
138 .name = "l4",
139 };
140
141 /* l4_abe */
142 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
143 .name = "l4_abe",
144 .class = &omap54xx_l4_hwmod_class,
145 .clkdm_name = "abe_clkdm",
146 .prcm = {
147 .omap4 = {
148 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
149 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
150 },
151 },
152 };
153
154 /* l4_cfg */
155 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
156 .name = "l4_cfg",
157 .class = &omap54xx_l4_hwmod_class,
158 .clkdm_name = "l4cfg_clkdm",
159 .prcm = {
160 .omap4 = {
161 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
162 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
163 },
164 },
165 };
166
167 /* l4_per */
168 static struct omap_hwmod omap54xx_l4_per_hwmod = {
169 .name = "l4_per",
170 .class = &omap54xx_l4_hwmod_class,
171 .clkdm_name = "l4per_clkdm",
172 .prcm = {
173 .omap4 = {
174 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
175 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
176 },
177 },
178 };
179
180 /* l4_wkup */
181 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
182 .name = "l4_wkup",
183 .class = &omap54xx_l4_hwmod_class,
184 .clkdm_name = "wkupaon_clkdm",
185 .prcm = {
186 .omap4 = {
187 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
188 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
189 },
190 },
191 };
192
193 /*
194 * 'mpu_bus' class
195 * instance(s): mpu_private
196 */
197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
198 .name = "mpu_bus",
199 };
200
201 /* mpu_private */
202 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
203 .name = "mpu_private",
204 .class = &omap54xx_mpu_bus_hwmod_class,
205 .clkdm_name = "mpu_clkdm",
206 .prcm = {
207 .omap4 = {
208 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
209 },
210 },
211 };
212
213 /*
214 * 'counter' class
215 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
216 */
217
218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
219 .rev_offs = 0x0000,
220 .sysc_offs = 0x0010,
221 .sysc_flags = SYSC_HAS_SIDLEMODE,
222 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
223 .sysc_fields = &omap_hwmod_sysc_type1,
224 };
225
226 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
227 .name = "counter",
228 .sysc = &omap54xx_counter_sysc,
229 };
230
231 /* counter_32k */
232 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
233 .name = "counter_32k",
234 .class = &omap54xx_counter_hwmod_class,
235 .clkdm_name = "wkupaon_clkdm",
236 .flags = HWMOD_SWSUP_SIDLE,
237 .main_clk = "wkupaon_iclk_mux",
238 .prcm = {
239 .omap4 = {
240 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
241 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
242 },
243 },
244 };
245
246 /*
247 * 'dma' class
248 * dma controller for data exchange between memory to memory (i.e. internal or
249 * external memory) and gp peripherals to memory or memory to gp peripherals
250 */
251
252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
253 .rev_offs = 0x0000,
254 .sysc_offs = 0x002c,
255 .syss_offs = 0x0028,
256 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
257 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
258 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
259 SYSS_HAS_RESET_STATUS),
260 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
261 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
262 .sysc_fields = &omap_hwmod_sysc_type1,
263 };
264
265 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
266 .name = "dma",
267 .sysc = &omap54xx_dma_sysc,
268 };
269
270 /* dma dev_attr */
271 static struct omap_dma_dev_attr dma_dev_attr = {
272 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
273 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
274 .lch_count = 32,
275 };
276
277 /* dma_system */
278 static struct omap_hwmod omap54xx_dma_system_hwmod = {
279 .name = "dma_system",
280 .class = &omap54xx_dma_hwmod_class,
281 .clkdm_name = "dma_clkdm",
282 .main_clk = "l3_iclk_div",
283 .prcm = {
284 .omap4 = {
285 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
286 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
287 },
288 },
289 .dev_attr = &dma_dev_attr,
290 };
291
292 /*
293 * 'dmic' class
294 * digital microphone controller
295 */
296
297 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
298 .rev_offs = 0x0000,
299 .sysc_offs = 0x0010,
300 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
301 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
302 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
303 SIDLE_SMART_WKUP),
304 .sysc_fields = &omap_hwmod_sysc_type2,
305 };
306
307 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
308 .name = "dmic",
309 .sysc = &omap54xx_dmic_sysc,
310 };
311
312 /* dmic */
313 static struct omap_hwmod omap54xx_dmic_hwmod = {
314 .name = "dmic",
315 .class = &omap54xx_dmic_hwmod_class,
316 .clkdm_name = "abe_clkdm",
317 .main_clk = "dmic_gfclk",
318 .prcm = {
319 .omap4 = {
320 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
321 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
322 .modulemode = MODULEMODE_SWCTRL,
323 },
324 },
325 };
326
327 /*
328 * 'dss' class
329 * display sub-system
330 */
331 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
332 .rev_offs = 0x0000,
333 .syss_offs = 0x0014,
334 .sysc_flags = SYSS_HAS_RESET_STATUS,
335 };
336
337 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
338 .name = "dss",
339 .sysc = &omap54xx_dss_sysc,
340 .reset = omap_dss_reset,
341 };
342
343 /* dss */
344 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
345 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
346 { .role = "sys_clk", .clk = "dss_sys_clk" },
347 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
348 };
349
350 static struct omap_hwmod omap54xx_dss_hwmod = {
351 .name = "dss_core",
352 .class = &omap54xx_dss_hwmod_class,
353 .clkdm_name = "dss_clkdm",
354 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
355 .main_clk = "dss_dss_clk",
356 .prcm = {
357 .omap4 = {
358 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
359 .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
360 .modulemode = MODULEMODE_SWCTRL,
361 },
362 },
363 .opt_clks = dss_opt_clks,
364 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
365 };
366
367 /*
368 * 'dispc' class
369 * display controller
370 */
371
372 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
373 .rev_offs = 0x0000,
374 .sysc_offs = 0x0010,
375 .syss_offs = 0x0014,
376 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
377 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
378 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
379 SYSS_HAS_RESET_STATUS),
380 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
381 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
382 .sysc_fields = &omap_hwmod_sysc_type1,
383 };
384
385 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
386 .name = "dispc",
387 .sysc = &omap54xx_dispc_sysc,
388 };
389
390 /* dss_dispc */
391 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
392 { .role = "sys_clk", .clk = "dss_sys_clk" },
393 };
394
395 /* dss_dispc dev_attr */
396 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
397 .has_framedonetv_irq = 1,
398 .manager_count = 4,
399 };
400
401 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
402 .name = "dss_dispc",
403 .class = &omap54xx_dispc_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .main_clk = "dss_dss_clk",
406 .prcm = {
407 .omap4 = {
408 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
409 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
410 },
411 },
412 .opt_clks = dss_dispc_opt_clks,
413 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
414 .dev_attr = &dss_dispc_dev_attr,
415 .parent_hwmod = &omap54xx_dss_hwmod,
416 };
417
418 /*
419 * 'dsi1' class
420 * display serial interface controller
421 */
422
423 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
424 .rev_offs = 0x0000,
425 .sysc_offs = 0x0010,
426 .syss_offs = 0x0014,
427 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
428 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
429 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
430 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
431 .sysc_fields = &omap_hwmod_sysc_type1,
432 };
433
434 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
435 .name = "dsi1",
436 .sysc = &omap54xx_dsi1_sysc,
437 };
438
439 /* dss_dsi1_a */
440 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
441 { .role = "sys_clk", .clk = "dss_sys_clk" },
442 };
443
444 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
445 .name = "dss_dsi1",
446 .class = &omap54xx_dsi1_hwmod_class,
447 .clkdm_name = "dss_clkdm",
448 .main_clk = "dss_dss_clk",
449 .prcm = {
450 .omap4 = {
451 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
452 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
453 },
454 },
455 .opt_clks = dss_dsi1_a_opt_clks,
456 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
457 .parent_hwmod = &omap54xx_dss_hwmod,
458 };
459
460 /* dss_dsi1_c */
461 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
462 { .role = "sys_clk", .clk = "dss_sys_clk" },
463 };
464
465 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
466 .name = "dss_dsi2",
467 .class = &omap54xx_dsi1_hwmod_class,
468 .clkdm_name = "dss_clkdm",
469 .main_clk = "dss_dss_clk",
470 .prcm = {
471 .omap4 = {
472 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
473 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
474 },
475 },
476 .opt_clks = dss_dsi1_c_opt_clks,
477 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
478 .parent_hwmod = &omap54xx_dss_hwmod,
479 };
480
481 /*
482 * 'hdmi' class
483 * hdmi controller
484 */
485
486 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
487 .rev_offs = 0x0000,
488 .sysc_offs = 0x0010,
489 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
490 SYSC_HAS_SOFTRESET),
491 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
492 SIDLE_SMART_WKUP),
493 .sysc_fields = &omap_hwmod_sysc_type2,
494 };
495
496 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
497 .name = "hdmi",
498 .sysc = &omap54xx_hdmi_sysc,
499 };
500
501 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
502 { .role = "sys_clk", .clk = "dss_sys_clk" },
503 };
504
505 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
506 .name = "dss_hdmi",
507 .class = &omap54xx_hdmi_hwmod_class,
508 .clkdm_name = "dss_clkdm",
509 .main_clk = "dss_48mhz_clk",
510 .prcm = {
511 .omap4 = {
512 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
513 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
514 },
515 },
516 .opt_clks = dss_hdmi_opt_clks,
517 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
518 .parent_hwmod = &omap54xx_dss_hwmod,
519 };
520
521 /*
522 * 'rfbi' class
523 * remote frame buffer interface
524 */
525
526 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
527 .rev_offs = 0x0000,
528 .sysc_offs = 0x0010,
529 .syss_offs = 0x0014,
530 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
531 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
532 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
533 .sysc_fields = &omap_hwmod_sysc_type1,
534 };
535
536 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
537 .name = "rfbi",
538 .sysc = &omap54xx_rfbi_sysc,
539 };
540
541 /* dss_rfbi */
542 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
543 { .role = "ick", .clk = "l3_iclk_div" },
544 };
545
546 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
547 .name = "dss_rfbi",
548 .class = &omap54xx_rfbi_hwmod_class,
549 .clkdm_name = "dss_clkdm",
550 .prcm = {
551 .omap4 = {
552 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
553 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
554 },
555 },
556 .opt_clks = dss_rfbi_opt_clks,
557 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
558 .parent_hwmod = &omap54xx_dss_hwmod,
559 };
560
561 /*
562 * 'emif' class
563 * external memory interface no1 (wrapper)
564 */
565
566 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
567 .rev_offs = 0x0000,
568 };
569
570 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
571 .name = "emif",
572 .sysc = &omap54xx_emif_sysc,
573 };
574
575 /* emif1 */
576 static struct omap_hwmod omap54xx_emif1_hwmod = {
577 .name = "emif1",
578 .class = &omap54xx_emif_hwmod_class,
579 .clkdm_name = "emif_clkdm",
580 .flags = HWMOD_INIT_NO_IDLE,
581 .main_clk = "dpll_core_h11x2_ck",
582 .prcm = {
583 .omap4 = {
584 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
585 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
586 .modulemode = MODULEMODE_HWCTRL,
587 },
588 },
589 };
590
591 /* emif2 */
592 static struct omap_hwmod omap54xx_emif2_hwmod = {
593 .name = "emif2",
594 .class = &omap54xx_emif_hwmod_class,
595 .clkdm_name = "emif_clkdm",
596 .flags = HWMOD_INIT_NO_IDLE,
597 .main_clk = "dpll_core_h11x2_ck",
598 .prcm = {
599 .omap4 = {
600 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
601 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
602 .modulemode = MODULEMODE_HWCTRL,
603 },
604 },
605 };
606
607 /*
608 * 'gpio' class
609 * general purpose io module
610 */
611
612 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
613 .rev_offs = 0x0000,
614 .sysc_offs = 0x0010,
615 .syss_offs = 0x0114,
616 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
617 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
618 SYSS_HAS_RESET_STATUS),
619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
620 SIDLE_SMART_WKUP),
621 .sysc_fields = &omap_hwmod_sysc_type1,
622 };
623
624 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
625 .name = "gpio",
626 .sysc = &omap54xx_gpio_sysc,
627 .rev = 2,
628 };
629
630 /* gpio dev_attr */
631 static struct omap_gpio_dev_attr gpio_dev_attr = {
632 .bank_width = 32,
633 .dbck_flag = true,
634 };
635
636 /* gpio1 */
637 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
638 { .role = "dbclk", .clk = "gpio1_dbclk" },
639 };
640
641 static struct omap_hwmod omap54xx_gpio1_hwmod = {
642 .name = "gpio1",
643 .class = &omap54xx_gpio_hwmod_class,
644 .clkdm_name = "wkupaon_clkdm",
645 .main_clk = "wkupaon_iclk_mux",
646 .prcm = {
647 .omap4 = {
648 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
649 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
650 .modulemode = MODULEMODE_HWCTRL,
651 },
652 },
653 .opt_clks = gpio1_opt_clks,
654 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
655 .dev_attr = &gpio_dev_attr,
656 };
657
658 /* gpio2 */
659 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
660 { .role = "dbclk", .clk = "gpio2_dbclk" },
661 };
662
663 static struct omap_hwmod omap54xx_gpio2_hwmod = {
664 .name = "gpio2",
665 .class = &omap54xx_gpio_hwmod_class,
666 .clkdm_name = "l4per_clkdm",
667 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
668 .main_clk = "l4_root_clk_div",
669 .prcm = {
670 .omap4 = {
671 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
672 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
673 .modulemode = MODULEMODE_HWCTRL,
674 },
675 },
676 .opt_clks = gpio2_opt_clks,
677 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
678 .dev_attr = &gpio_dev_attr,
679 };
680
681 /* gpio3 */
682 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
683 { .role = "dbclk", .clk = "gpio3_dbclk" },
684 };
685
686 static struct omap_hwmod omap54xx_gpio3_hwmod = {
687 .name = "gpio3",
688 .class = &omap54xx_gpio_hwmod_class,
689 .clkdm_name = "l4per_clkdm",
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .main_clk = "l4_root_clk_div",
692 .prcm = {
693 .omap4 = {
694 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
695 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
696 .modulemode = MODULEMODE_HWCTRL,
697 },
698 },
699 .opt_clks = gpio3_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
701 .dev_attr = &gpio_dev_attr,
702 };
703
704 /* gpio4 */
705 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
706 { .role = "dbclk", .clk = "gpio4_dbclk" },
707 };
708
709 static struct omap_hwmod omap54xx_gpio4_hwmod = {
710 .name = "gpio4",
711 .class = &omap54xx_gpio_hwmod_class,
712 .clkdm_name = "l4per_clkdm",
713 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714 .main_clk = "l4_root_clk_div",
715 .prcm = {
716 .omap4 = {
717 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
718 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
720 },
721 },
722 .opt_clks = gpio4_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
724 .dev_attr = &gpio_dev_attr,
725 };
726
727 /* gpio5 */
728 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
729 { .role = "dbclk", .clk = "gpio5_dbclk" },
730 };
731
732 static struct omap_hwmod omap54xx_gpio5_hwmod = {
733 .name = "gpio5",
734 .class = &omap54xx_gpio_hwmod_class,
735 .clkdm_name = "l4per_clkdm",
736 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
737 .main_clk = "l4_root_clk_div",
738 .prcm = {
739 .omap4 = {
740 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
741 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
742 .modulemode = MODULEMODE_HWCTRL,
743 },
744 },
745 .opt_clks = gpio5_opt_clks,
746 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
747 .dev_attr = &gpio_dev_attr,
748 };
749
750 /* gpio6 */
751 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
752 { .role = "dbclk", .clk = "gpio6_dbclk" },
753 };
754
755 static struct omap_hwmod omap54xx_gpio6_hwmod = {
756 .name = "gpio6",
757 .class = &omap54xx_gpio_hwmod_class,
758 .clkdm_name = "l4per_clkdm",
759 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
760 .main_clk = "l4_root_clk_div",
761 .prcm = {
762 .omap4 = {
763 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
764 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
765 .modulemode = MODULEMODE_HWCTRL,
766 },
767 },
768 .opt_clks = gpio6_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
770 .dev_attr = &gpio_dev_attr,
771 };
772
773 /* gpio7 */
774 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
775 { .role = "dbclk", .clk = "gpio7_dbclk" },
776 };
777
778 static struct omap_hwmod omap54xx_gpio7_hwmod = {
779 .name = "gpio7",
780 .class = &omap54xx_gpio_hwmod_class,
781 .clkdm_name = "l4per_clkdm",
782 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
783 .main_clk = "l4_root_clk_div",
784 .prcm = {
785 .omap4 = {
786 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
787 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
788 .modulemode = MODULEMODE_HWCTRL,
789 },
790 },
791 .opt_clks = gpio7_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
793 .dev_attr = &gpio_dev_attr,
794 };
795
796 /* gpio8 */
797 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
798 { .role = "dbclk", .clk = "gpio8_dbclk" },
799 };
800
801 static struct omap_hwmod omap54xx_gpio8_hwmod = {
802 .name = "gpio8",
803 .class = &omap54xx_gpio_hwmod_class,
804 .clkdm_name = "l4per_clkdm",
805 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
806 .main_clk = "l4_root_clk_div",
807 .prcm = {
808 .omap4 = {
809 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
810 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
811 .modulemode = MODULEMODE_HWCTRL,
812 },
813 },
814 .opt_clks = gpio8_opt_clks,
815 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
816 .dev_attr = &gpio_dev_attr,
817 };
818
819 /*
820 * 'i2c' class
821 * multimaster high-speed i2c controller
822 */
823
824 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
825 .sysc_offs = 0x0010,
826 .syss_offs = 0x0090,
827 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
828 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
829 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
830 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
831 SIDLE_SMART_WKUP),
832 .sysc_fields = &omap_hwmod_sysc_type1,
833 };
834
835 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
836 .name = "i2c",
837 .sysc = &omap54xx_i2c_sysc,
838 .reset = &omap_i2c_reset,
839 .rev = OMAP_I2C_IP_VERSION_2,
840 };
841
842 /* i2c dev_attr */
843 static struct omap_i2c_dev_attr i2c_dev_attr = {
844 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
845 };
846
847 /* i2c1 */
848 static struct omap_hwmod omap54xx_i2c1_hwmod = {
849 .name = "i2c1",
850 .class = &omap54xx_i2c_hwmod_class,
851 .clkdm_name = "l4per_clkdm",
852 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
853 .main_clk = "func_96m_fclk",
854 .prcm = {
855 .omap4 = {
856 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
857 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
858 .modulemode = MODULEMODE_SWCTRL,
859 },
860 },
861 .dev_attr = &i2c_dev_attr,
862 };
863
864 /* i2c2 */
865 static struct omap_hwmod omap54xx_i2c2_hwmod = {
866 .name = "i2c2",
867 .class = &omap54xx_i2c_hwmod_class,
868 .clkdm_name = "l4per_clkdm",
869 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
870 .main_clk = "func_96m_fclk",
871 .prcm = {
872 .omap4 = {
873 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
874 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
875 .modulemode = MODULEMODE_SWCTRL,
876 },
877 },
878 .dev_attr = &i2c_dev_attr,
879 };
880
881 /* i2c3 */
882 static struct omap_hwmod omap54xx_i2c3_hwmod = {
883 .name = "i2c3",
884 .class = &omap54xx_i2c_hwmod_class,
885 .clkdm_name = "l4per_clkdm",
886 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
887 .main_clk = "func_96m_fclk",
888 .prcm = {
889 .omap4 = {
890 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
891 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
892 .modulemode = MODULEMODE_SWCTRL,
893 },
894 },
895 .dev_attr = &i2c_dev_attr,
896 };
897
898 /* i2c4 */
899 static struct omap_hwmod omap54xx_i2c4_hwmod = {
900 .name = "i2c4",
901 .class = &omap54xx_i2c_hwmod_class,
902 .clkdm_name = "l4per_clkdm",
903 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
904 .main_clk = "func_96m_fclk",
905 .prcm = {
906 .omap4 = {
907 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
908 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
909 .modulemode = MODULEMODE_SWCTRL,
910 },
911 },
912 .dev_attr = &i2c_dev_attr,
913 };
914
915 /* i2c5 */
916 static struct omap_hwmod omap54xx_i2c5_hwmod = {
917 .name = "i2c5",
918 .class = &omap54xx_i2c_hwmod_class,
919 .clkdm_name = "l4per_clkdm",
920 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
921 .main_clk = "func_96m_fclk",
922 .prcm = {
923 .omap4 = {
924 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
925 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
926 .modulemode = MODULEMODE_SWCTRL,
927 },
928 },
929 .dev_attr = &i2c_dev_attr,
930 };
931
932 /*
933 * 'kbd' class
934 * keyboard controller
935 */
936
937 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
938 .rev_offs = 0x0000,
939 .sysc_offs = 0x0010,
940 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
941 SYSC_HAS_SOFTRESET),
942 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
943 .sysc_fields = &omap_hwmod_sysc_type1,
944 };
945
946 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
947 .name = "kbd",
948 .sysc = &omap54xx_kbd_sysc,
949 };
950
951 /* kbd */
952 static struct omap_hwmod omap54xx_kbd_hwmod = {
953 .name = "kbd",
954 .class = &omap54xx_kbd_hwmod_class,
955 .clkdm_name = "wkupaon_clkdm",
956 .main_clk = "sys_32k_ck",
957 .prcm = {
958 .omap4 = {
959 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
960 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
961 .modulemode = MODULEMODE_SWCTRL,
962 },
963 },
964 };
965
966 /*
967 * 'mailbox' class
968 * mailbox module allowing communication between the on-chip processors using a
969 * queued mailbox-interrupt mechanism.
970 */
971
972 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
973 .rev_offs = 0x0000,
974 .sysc_offs = 0x0010,
975 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
976 SYSC_HAS_SOFTRESET),
977 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
978 .sysc_fields = &omap_hwmod_sysc_type2,
979 };
980
981 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
982 .name = "mailbox",
983 .sysc = &omap54xx_mailbox_sysc,
984 };
985
986 /* mailbox */
987 static struct omap_hwmod omap54xx_mailbox_hwmod = {
988 .name = "mailbox",
989 .class = &omap54xx_mailbox_hwmod_class,
990 .clkdm_name = "l4cfg_clkdm",
991 .prcm = {
992 .omap4 = {
993 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
994 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
995 },
996 },
997 };
998
999 /*
1000 * 'mcbsp' class
1001 * multi channel buffered serial port controller
1002 */
1003
1004 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
1005 .sysc_offs = 0x008c,
1006 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1007 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1008 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1009 .sysc_fields = &omap_hwmod_sysc_type1,
1010 };
1011
1012 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
1013 .name = "mcbsp",
1014 .sysc = &omap54xx_mcbsp_sysc,
1015 .rev = MCBSP_CONFIG_TYPE4,
1016 };
1017
1018 /* mcbsp1 */
1019 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1020 { .role = "pad_fck", .clk = "pad_clks_ck" },
1021 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1022 };
1023
1024 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
1025 .name = "mcbsp1",
1026 .class = &omap54xx_mcbsp_hwmod_class,
1027 .clkdm_name = "abe_clkdm",
1028 .main_clk = "mcbsp1_gfclk",
1029 .prcm = {
1030 .omap4 = {
1031 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
1032 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1033 .modulemode = MODULEMODE_SWCTRL,
1034 },
1035 },
1036 .opt_clks = mcbsp1_opt_clks,
1037 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1038 };
1039
1040 /* mcbsp2 */
1041 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1042 { .role = "pad_fck", .clk = "pad_clks_ck" },
1043 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1044 };
1045
1046 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
1047 .name = "mcbsp2",
1048 .class = &omap54xx_mcbsp_hwmod_class,
1049 .clkdm_name = "abe_clkdm",
1050 .main_clk = "mcbsp2_gfclk",
1051 .prcm = {
1052 .omap4 = {
1053 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
1054 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1055 .modulemode = MODULEMODE_SWCTRL,
1056 },
1057 },
1058 .opt_clks = mcbsp2_opt_clks,
1059 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1060 };
1061
1062 /* mcbsp3 */
1063 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1064 { .role = "pad_fck", .clk = "pad_clks_ck" },
1065 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1066 };
1067
1068 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
1069 .name = "mcbsp3",
1070 .class = &omap54xx_mcbsp_hwmod_class,
1071 .clkdm_name = "abe_clkdm",
1072 .main_clk = "mcbsp3_gfclk",
1073 .prcm = {
1074 .omap4 = {
1075 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
1076 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1077 .modulemode = MODULEMODE_SWCTRL,
1078 },
1079 },
1080 .opt_clks = mcbsp3_opt_clks,
1081 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1082 };
1083
1084 /*
1085 * 'mcpdm' class
1086 * multi channel pdm controller (proprietary interface with phoenix power
1087 * ic)
1088 */
1089
1090 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
1091 .rev_offs = 0x0000,
1092 .sysc_offs = 0x0010,
1093 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1094 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1095 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1096 SIDLE_SMART_WKUP),
1097 .sysc_fields = &omap_hwmod_sysc_type2,
1098 };
1099
1100 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
1101 .name = "mcpdm",
1102 .sysc = &omap54xx_mcpdm_sysc,
1103 };
1104
1105 /* mcpdm */
1106 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
1107 .name = "mcpdm",
1108 .class = &omap54xx_mcpdm_hwmod_class,
1109 .clkdm_name = "abe_clkdm",
1110 /*
1111 * It's suspected that the McPDM requires an off-chip main
1112 * functional clock, controlled via I2C. This IP block is
1113 * currently reset very early during boot, before I2C is
1114 * available, so it doesn't seem that we have any choice in
1115 * the kernel other than to avoid resetting it. XXX This is
1116 * really a hardware issue workaround: every IP block should
1117 * be able to source its main functional clock from either
1118 * on-chip or off-chip sources. McPDM seems to be the only
1119 * current exception.
1120 */
1121
1122 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1123 .main_clk = "pad_clks_ck",
1124 .prcm = {
1125 .omap4 = {
1126 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
1127 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
1128 .modulemode = MODULEMODE_SWCTRL,
1129 },
1130 },
1131 };
1132
1133 /*
1134 * 'mcspi' class
1135 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1136 * bus
1137 */
1138
1139 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
1140 .rev_offs = 0x0000,
1141 .sysc_offs = 0x0010,
1142 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1143 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1144 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1145 SIDLE_SMART_WKUP),
1146 .sysc_fields = &omap_hwmod_sysc_type2,
1147 };
1148
1149 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
1150 .name = "mcspi",
1151 .sysc = &omap54xx_mcspi_sysc,
1152 .rev = OMAP4_MCSPI_REV,
1153 };
1154
1155 /* mcspi1 */
1156 /* mcspi1 dev_attr */
1157 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1158 .num_chipselect = 4,
1159 };
1160
1161 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
1162 .name = "mcspi1",
1163 .class = &omap54xx_mcspi_hwmod_class,
1164 .clkdm_name = "l4per_clkdm",
1165 .main_clk = "func_48m_fclk",
1166 .prcm = {
1167 .omap4 = {
1168 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1169 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1170 .modulemode = MODULEMODE_SWCTRL,
1171 },
1172 },
1173 .dev_attr = &mcspi1_dev_attr,
1174 };
1175
1176 /* mcspi2 */
1177 /* mcspi2 dev_attr */
1178 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1179 .num_chipselect = 2,
1180 };
1181
1182 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
1183 .name = "mcspi2",
1184 .class = &omap54xx_mcspi_hwmod_class,
1185 .clkdm_name = "l4per_clkdm",
1186 .main_clk = "func_48m_fclk",
1187 .prcm = {
1188 .omap4 = {
1189 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1190 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1191 .modulemode = MODULEMODE_SWCTRL,
1192 },
1193 },
1194 .dev_attr = &mcspi2_dev_attr,
1195 };
1196
1197 /* mcspi3 */
1198 /* mcspi3 dev_attr */
1199 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1200 .num_chipselect = 2,
1201 };
1202
1203 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
1204 .name = "mcspi3",
1205 .class = &omap54xx_mcspi_hwmod_class,
1206 .clkdm_name = "l4per_clkdm",
1207 .main_clk = "func_48m_fclk",
1208 .prcm = {
1209 .omap4 = {
1210 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1211 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1212 .modulemode = MODULEMODE_SWCTRL,
1213 },
1214 },
1215 .dev_attr = &mcspi3_dev_attr,
1216 };
1217
1218 /* mcspi4 */
1219 /* mcspi4 dev_attr */
1220 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1221 .num_chipselect = 1,
1222 };
1223
1224 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1225 .name = "mcspi4",
1226 .class = &omap54xx_mcspi_hwmod_class,
1227 .clkdm_name = "l4per_clkdm",
1228 .main_clk = "func_48m_fclk",
1229 .prcm = {
1230 .omap4 = {
1231 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1232 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1233 .modulemode = MODULEMODE_SWCTRL,
1234 },
1235 },
1236 .dev_attr = &mcspi4_dev_attr,
1237 };
1238
1239 /*
1240 * 'mmc' class
1241 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1242 */
1243
1244 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1245 .rev_offs = 0x0000,
1246 .sysc_offs = 0x0010,
1247 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1248 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1249 SYSC_HAS_SOFTRESET),
1250 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1251 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1252 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1253 .sysc_fields = &omap_hwmod_sysc_type2,
1254 };
1255
1256 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1257 .name = "mmc",
1258 .sysc = &omap54xx_mmc_sysc,
1259 };
1260
1261 /* mmc1 */
1262 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1263 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1264 };
1265
1266 /* mmc1 dev_attr */
1267 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1268 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1269 };
1270
1271 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1272 .name = "mmc1",
1273 .class = &omap54xx_mmc_hwmod_class,
1274 .clkdm_name = "l3init_clkdm",
1275 .main_clk = "mmc1_fclk",
1276 .prcm = {
1277 .omap4 = {
1278 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1279 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1280 .modulemode = MODULEMODE_SWCTRL,
1281 },
1282 },
1283 .opt_clks = mmc1_opt_clks,
1284 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1285 .dev_attr = &mmc1_dev_attr,
1286 };
1287
1288 /* mmc2 */
1289 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1290 .name = "mmc2",
1291 .class = &omap54xx_mmc_hwmod_class,
1292 .clkdm_name = "l3init_clkdm",
1293 .main_clk = "mmc2_fclk",
1294 .prcm = {
1295 .omap4 = {
1296 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1297 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1298 .modulemode = MODULEMODE_SWCTRL,
1299 },
1300 },
1301 };
1302
1303 /* mmc3 */
1304 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1305 .name = "mmc3",
1306 .class = &omap54xx_mmc_hwmod_class,
1307 .clkdm_name = "l4per_clkdm",
1308 .main_clk = "func_48m_fclk",
1309 .prcm = {
1310 .omap4 = {
1311 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1312 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1313 .modulemode = MODULEMODE_SWCTRL,
1314 },
1315 },
1316 };
1317
1318 /* mmc4 */
1319 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1320 .name = "mmc4",
1321 .class = &omap54xx_mmc_hwmod_class,
1322 .clkdm_name = "l4per_clkdm",
1323 .main_clk = "func_48m_fclk",
1324 .prcm = {
1325 .omap4 = {
1326 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1327 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1328 .modulemode = MODULEMODE_SWCTRL,
1329 },
1330 },
1331 };
1332
1333 /* mmc5 */
1334 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1335 .name = "mmc5",
1336 .class = &omap54xx_mmc_hwmod_class,
1337 .clkdm_name = "l4per_clkdm",
1338 .main_clk = "func_96m_fclk",
1339 .prcm = {
1340 .omap4 = {
1341 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1342 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1343 .modulemode = MODULEMODE_SWCTRL,
1344 },
1345 },
1346 };
1347
1348 /*
1349 * 'mmu' class
1350 * The memory management unit performs virtual to physical address translation
1351 * for its requestors.
1352 */
1353
1354 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1355 .rev_offs = 0x0000,
1356 .sysc_offs = 0x0010,
1357 .syss_offs = 0x0014,
1358 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1359 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1360 SYSS_HAS_RESET_STATUS),
1361 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1362 .sysc_fields = &omap_hwmod_sysc_type1,
1363 };
1364
1365 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1366 .name = "mmu",
1367 .sysc = &omap54xx_mmu_sysc,
1368 };
1369
1370 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1371 { .name = "mmu_cache", .rst_shift = 1 },
1372 };
1373
1374 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1375 .name = "mmu_dsp",
1376 .class = &omap54xx_mmu_hwmod_class,
1377 .clkdm_name = "dsp_clkdm",
1378 .rst_lines = omap54xx_mmu_dsp_resets,
1379 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1380 .main_clk = "dpll_iva_h11x2_ck",
1381 .prcm = {
1382 .omap4 = {
1383 .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1384 .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1385 .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1386 .modulemode = MODULEMODE_HWCTRL,
1387 },
1388 },
1389 };
1390
1391 /* mmu ipu */
1392 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1393 { .name = "mmu_cache", .rst_shift = 2 },
1394 };
1395
1396 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1397 .name = "mmu_ipu",
1398 .class = &omap54xx_mmu_hwmod_class,
1399 .clkdm_name = "ipu_clkdm",
1400 .rst_lines = omap54xx_mmu_ipu_resets,
1401 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1402 .main_clk = "dpll_core_h22x2_ck",
1403 .prcm = {
1404 .omap4 = {
1405 .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1406 .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1407 .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1408 .modulemode = MODULEMODE_HWCTRL,
1409 },
1410 },
1411 };
1412
1413 /*
1414 * 'mpu' class
1415 * mpu sub-system
1416 */
1417
1418 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1419 .name = "mpu",
1420 };
1421
1422 /* mpu */
1423 static struct omap_hwmod omap54xx_mpu_hwmod = {
1424 .name = "mpu",
1425 .class = &omap54xx_mpu_hwmod_class,
1426 .clkdm_name = "mpu_clkdm",
1427 .flags = HWMOD_INIT_NO_IDLE,
1428 .main_clk = "dpll_mpu_m2_ck",
1429 .prcm = {
1430 .omap4 = {
1431 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1432 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1433 },
1434 },
1435 };
1436
1437 /*
1438 * 'spinlock' class
1439 * spinlock provides hardware assistance for synchronizing the processes
1440 * running on multiple processors
1441 */
1442
1443 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1444 .rev_offs = 0x0000,
1445 .sysc_offs = 0x0010,
1446 .syss_offs = 0x0014,
1447 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1448 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1449 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1450 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1451 .sysc_fields = &omap_hwmod_sysc_type1,
1452 };
1453
1454 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1455 .name = "spinlock",
1456 .sysc = &omap54xx_spinlock_sysc,
1457 };
1458
1459 /* spinlock */
1460 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1461 .name = "spinlock",
1462 .class = &omap54xx_spinlock_hwmod_class,
1463 .clkdm_name = "l4cfg_clkdm",
1464 .prcm = {
1465 .omap4 = {
1466 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1467 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1468 },
1469 },
1470 };
1471
1472 /*
1473 * 'ocp2scp' class
1474 * bridge to transform ocp interface protocol to scp (serial control port)
1475 * protocol
1476 */
1477
1478 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1479 .rev_offs = 0x0000,
1480 .sysc_offs = 0x0010,
1481 .syss_offs = 0x0014,
1482 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1483 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1484 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1485 .sysc_fields = &omap_hwmod_sysc_type1,
1486 };
1487
1488 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1489 .name = "ocp2scp",
1490 .sysc = &omap54xx_ocp2scp_sysc,
1491 };
1492
1493 /* ocp2scp1 */
1494 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1495 .name = "ocp2scp1",
1496 .class = &omap54xx_ocp2scp_hwmod_class,
1497 .clkdm_name = "l3init_clkdm",
1498 .main_clk = "l4_root_clk_div",
1499 .prcm = {
1500 .omap4 = {
1501 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1502 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1503 .modulemode = MODULEMODE_HWCTRL,
1504 },
1505 },
1506 };
1507
1508 /*
1509 * 'timer' class
1510 * general purpose timer module with accurate 1ms tick
1511 * This class contains several variants: ['timer_1ms', 'timer']
1512 */
1513
1514 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1515 .rev_offs = 0x0000,
1516 .sysc_offs = 0x0010,
1517 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1518 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1519 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1520 SIDLE_SMART_WKUP),
1521 .sysc_fields = &omap_hwmod_sysc_type2,
1522 };
1523
1524 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1525 .name = "timer",
1526 .sysc = &omap54xx_timer_1ms_sysc,
1527 };
1528
1529 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1530 .rev_offs = 0x0000,
1531 .sysc_offs = 0x0010,
1532 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1533 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1534 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1535 SIDLE_SMART_WKUP),
1536 .sysc_fields = &omap_hwmod_sysc_type2,
1537 };
1538
1539 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1540 .name = "timer",
1541 .sysc = &omap54xx_timer_sysc,
1542 };
1543
1544 /* timer1 */
1545 static struct omap_hwmod omap54xx_timer1_hwmod = {
1546 .name = "timer1",
1547 .class = &omap54xx_timer_1ms_hwmod_class,
1548 .clkdm_name = "wkupaon_clkdm",
1549 .main_clk = "timer1_gfclk_mux",
1550 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1551 .prcm = {
1552 .omap4 = {
1553 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1554 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1555 .modulemode = MODULEMODE_SWCTRL,
1556 },
1557 },
1558 };
1559
1560 /* timer2 */
1561 static struct omap_hwmod omap54xx_timer2_hwmod = {
1562 .name = "timer2",
1563 .class = &omap54xx_timer_1ms_hwmod_class,
1564 .clkdm_name = "l4per_clkdm",
1565 .main_clk = "timer2_gfclk_mux",
1566 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1567 .prcm = {
1568 .omap4 = {
1569 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1570 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1571 .modulemode = MODULEMODE_SWCTRL,
1572 },
1573 },
1574 };
1575
1576 /* timer3 */
1577 static struct omap_hwmod omap54xx_timer3_hwmod = {
1578 .name = "timer3",
1579 .class = &omap54xx_timer_hwmod_class,
1580 .clkdm_name = "l4per_clkdm",
1581 .main_clk = "timer3_gfclk_mux",
1582 .prcm = {
1583 .omap4 = {
1584 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1585 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1586 .modulemode = MODULEMODE_SWCTRL,
1587 },
1588 },
1589 };
1590
1591 /* timer4 */
1592 static struct omap_hwmod omap54xx_timer4_hwmod = {
1593 .name = "timer4",
1594 .class = &omap54xx_timer_hwmod_class,
1595 .clkdm_name = "l4per_clkdm",
1596 .main_clk = "timer4_gfclk_mux",
1597 .prcm = {
1598 .omap4 = {
1599 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1600 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1601 .modulemode = MODULEMODE_SWCTRL,
1602 },
1603 },
1604 };
1605
1606 /* timer5 */
1607 static struct omap_hwmod omap54xx_timer5_hwmod = {
1608 .name = "timer5",
1609 .class = &omap54xx_timer_hwmod_class,
1610 .clkdm_name = "abe_clkdm",
1611 .main_clk = "timer5_gfclk_mux",
1612 .prcm = {
1613 .omap4 = {
1614 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1615 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1616 .modulemode = MODULEMODE_SWCTRL,
1617 },
1618 },
1619 };
1620
1621 /* timer6 */
1622 static struct omap_hwmod omap54xx_timer6_hwmod = {
1623 .name = "timer6",
1624 .class = &omap54xx_timer_hwmod_class,
1625 .clkdm_name = "abe_clkdm",
1626 .main_clk = "timer6_gfclk_mux",
1627 .prcm = {
1628 .omap4 = {
1629 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1630 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1631 .modulemode = MODULEMODE_SWCTRL,
1632 },
1633 },
1634 };
1635
1636 /* timer7 */
1637 static struct omap_hwmod omap54xx_timer7_hwmod = {
1638 .name = "timer7",
1639 .class = &omap54xx_timer_hwmod_class,
1640 .clkdm_name = "abe_clkdm",
1641 .main_clk = "timer7_gfclk_mux",
1642 .prcm = {
1643 .omap4 = {
1644 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1645 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1646 .modulemode = MODULEMODE_SWCTRL,
1647 },
1648 },
1649 };
1650
1651 /* timer8 */
1652 static struct omap_hwmod omap54xx_timer8_hwmod = {
1653 .name = "timer8",
1654 .class = &omap54xx_timer_hwmod_class,
1655 .clkdm_name = "abe_clkdm",
1656 .main_clk = "timer8_gfclk_mux",
1657 .prcm = {
1658 .omap4 = {
1659 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1660 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1661 .modulemode = MODULEMODE_SWCTRL,
1662 },
1663 },
1664 };
1665
1666 /* timer9 */
1667 static struct omap_hwmod omap54xx_timer9_hwmod = {
1668 .name = "timer9",
1669 .class = &omap54xx_timer_hwmod_class,
1670 .clkdm_name = "l4per_clkdm",
1671 .main_clk = "timer9_gfclk_mux",
1672 .prcm = {
1673 .omap4 = {
1674 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1675 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1676 .modulemode = MODULEMODE_SWCTRL,
1677 },
1678 },
1679 };
1680
1681 /* timer10 */
1682 static struct omap_hwmod omap54xx_timer10_hwmod = {
1683 .name = "timer10",
1684 .class = &omap54xx_timer_1ms_hwmod_class,
1685 .clkdm_name = "l4per_clkdm",
1686 .main_clk = "timer10_gfclk_mux",
1687 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1688 .prcm = {
1689 .omap4 = {
1690 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1691 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1692 .modulemode = MODULEMODE_SWCTRL,
1693 },
1694 },
1695 };
1696
1697 /* timer11 */
1698 static struct omap_hwmod omap54xx_timer11_hwmod = {
1699 .name = "timer11",
1700 .class = &omap54xx_timer_hwmod_class,
1701 .clkdm_name = "l4per_clkdm",
1702 .main_clk = "timer11_gfclk_mux",
1703 .prcm = {
1704 .omap4 = {
1705 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1706 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1707 .modulemode = MODULEMODE_SWCTRL,
1708 },
1709 },
1710 };
1711
1712 /*
1713 * 'uart' class
1714 * universal asynchronous receiver/transmitter (uart)
1715 */
1716
1717 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1718 .rev_offs = 0x0050,
1719 .sysc_offs = 0x0054,
1720 .syss_offs = 0x0058,
1721 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1722 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1723 SYSS_HAS_RESET_STATUS),
1724 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1725 SIDLE_SMART_WKUP),
1726 .sysc_fields = &omap_hwmod_sysc_type1,
1727 };
1728
1729 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1730 .name = "uart",
1731 .sysc = &omap54xx_uart_sysc,
1732 };
1733
1734 /* uart1 */
1735 static struct omap_hwmod omap54xx_uart1_hwmod = {
1736 .name = "uart1",
1737 .class = &omap54xx_uart_hwmod_class,
1738 .clkdm_name = "l4per_clkdm",
1739 .flags = HWMOD_SWSUP_SIDLE_ACT,
1740 .main_clk = "func_48m_fclk",
1741 .prcm = {
1742 .omap4 = {
1743 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1744 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1745 .modulemode = MODULEMODE_SWCTRL,
1746 },
1747 },
1748 };
1749
1750 /* uart2 */
1751 static struct omap_hwmod omap54xx_uart2_hwmod = {
1752 .name = "uart2",
1753 .class = &omap54xx_uart_hwmod_class,
1754 .clkdm_name = "l4per_clkdm",
1755 .flags = HWMOD_SWSUP_SIDLE_ACT,
1756 .main_clk = "func_48m_fclk",
1757 .prcm = {
1758 .omap4 = {
1759 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1760 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1761 .modulemode = MODULEMODE_SWCTRL,
1762 },
1763 },
1764 };
1765
1766 /* uart3 */
1767 static struct omap_hwmod omap54xx_uart3_hwmod = {
1768 .name = "uart3",
1769 .class = &omap54xx_uart_hwmod_class,
1770 .clkdm_name = "l4per_clkdm",
1771 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1772 .main_clk = "func_48m_fclk",
1773 .prcm = {
1774 .omap4 = {
1775 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1776 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1777 .modulemode = MODULEMODE_SWCTRL,
1778 },
1779 },
1780 };
1781
1782 /* uart4 */
1783 static struct omap_hwmod omap54xx_uart4_hwmod = {
1784 .name = "uart4",
1785 .class = &omap54xx_uart_hwmod_class,
1786 .clkdm_name = "l4per_clkdm",
1787 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1788 .main_clk = "func_48m_fclk",
1789 .prcm = {
1790 .omap4 = {
1791 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1792 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1793 .modulemode = MODULEMODE_SWCTRL,
1794 },
1795 },
1796 };
1797
1798 /* uart5 */
1799 static struct omap_hwmod omap54xx_uart5_hwmod = {
1800 .name = "uart5",
1801 .class = &omap54xx_uart_hwmod_class,
1802 .clkdm_name = "l4per_clkdm",
1803 .flags = HWMOD_SWSUP_SIDLE_ACT,
1804 .main_clk = "func_48m_fclk",
1805 .prcm = {
1806 .omap4 = {
1807 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1808 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1809 .modulemode = MODULEMODE_SWCTRL,
1810 },
1811 },
1812 };
1813
1814 /* uart6 */
1815 static struct omap_hwmod omap54xx_uart6_hwmod = {
1816 .name = "uart6",
1817 .class = &omap54xx_uart_hwmod_class,
1818 .clkdm_name = "l4per_clkdm",
1819 .flags = HWMOD_SWSUP_SIDLE_ACT,
1820 .main_clk = "func_48m_fclk",
1821 .prcm = {
1822 .omap4 = {
1823 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1824 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1825 .modulemode = MODULEMODE_SWCTRL,
1826 },
1827 },
1828 };
1829
1830 /*
1831 * 'usb_host_hs' class
1832 * high-speed multi-port usb host controller
1833 */
1834
1835 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1836 .rev_offs = 0x0000,
1837 .sysc_offs = 0x0010,
1838 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1839 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1840 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1841 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1842 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1843 .sysc_fields = &omap_hwmod_sysc_type2,
1844 };
1845
1846 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1847 .name = "usb_host_hs",
1848 .sysc = &omap54xx_usb_host_hs_sysc,
1849 };
1850
1851 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1852 .name = "usb_host_hs",
1853 .class = &omap54xx_usb_host_hs_hwmod_class,
1854 .clkdm_name = "l3init_clkdm",
1855 /*
1856 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1857 * id: i660
1858 *
1859 * Description:
1860 * In the following configuration :
1861 * - USBHOST module is set to smart-idle mode
1862 * - PRCM asserts idle_req to the USBHOST module ( This typically
1863 * happens when the system is going to a low power mode : all ports
1864 * have been suspended, the master part of the USBHOST module has
1865 * entered the standby state, and SW has cut the functional clocks)
1866 * - an USBHOST interrupt occurs before the module is able to answer
1867 * idle_ack, typically a remote wakeup IRQ.
1868 * Then the USB HOST module will enter a deadlock situation where it
1869 * is no more accessible nor functional.
1870 *
1871 * Workaround:
1872 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1873 */
1874
1875 /*
1876 * Errata: USB host EHCI may stall when entering smart-standby mode
1877 * Id: i571
1878 *
1879 * Description:
1880 * When the USBHOST module is set to smart-standby mode, and when it is
1881 * ready to enter the standby state (i.e. all ports are suspended and
1882 * all attached devices are in suspend mode), then it can wrongly assert
1883 * the Mstandby signal too early while there are still some residual OCP
1884 * transactions ongoing. If this condition occurs, the internal state
1885 * machine may go to an undefined state and the USB link may be stuck
1886 * upon the next resume.
1887 *
1888 * Workaround:
1889 * Don't use smart standby; use only force standby,
1890 * hence HWMOD_SWSUP_MSTANDBY
1891 */
1892
1893 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1894 .main_clk = "l3init_60m_fclk",
1895 .prcm = {
1896 .omap4 = {
1897 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1898 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1899 .modulemode = MODULEMODE_SWCTRL,
1900 },
1901 },
1902 };
1903
1904 /*
1905 * 'usb_tll_hs' class
1906 * usb_tll_hs module is the adapter on the usb_host_hs ports
1907 */
1908
1909 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1910 .rev_offs = 0x0000,
1911 .sysc_offs = 0x0010,
1912 .syss_offs = 0x0014,
1913 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1914 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1915 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1916 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1917 .sysc_fields = &omap_hwmod_sysc_type1,
1918 };
1919
1920 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1921 .name = "usb_tll_hs",
1922 .sysc = &omap54xx_usb_tll_hs_sysc,
1923 };
1924
1925 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1926 .name = "usb_tll_hs",
1927 .class = &omap54xx_usb_tll_hs_hwmod_class,
1928 .clkdm_name = "l3init_clkdm",
1929 .main_clk = "l4_root_clk_div",
1930 .prcm = {
1931 .omap4 = {
1932 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1933 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1934 .modulemode = MODULEMODE_HWCTRL,
1935 },
1936 },
1937 };
1938
1939 /*
1940 * 'usb_otg_ss' class
1941 * 2.0 super speed (usb_otg_ss) controller
1942 */
1943
1944 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1945 .rev_offs = 0x0000,
1946 .sysc_offs = 0x0010,
1947 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1948 SYSC_HAS_SIDLEMODE),
1949 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1950 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1951 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1952 .sysc_fields = &omap_hwmod_sysc_type2,
1953 };
1954
1955 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1956 .name = "usb_otg_ss",
1957 .sysc = &omap54xx_usb_otg_ss_sysc,
1958 };
1959
1960 /* usb_otg_ss */
1961 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1962 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1963 };
1964
1965 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1966 .name = "usb_otg_ss",
1967 .class = &omap54xx_usb_otg_ss_hwmod_class,
1968 .clkdm_name = "l3init_clkdm",
1969 .flags = HWMOD_SWSUP_SIDLE,
1970 .main_clk = "dpll_core_h13x2_ck",
1971 .prcm = {
1972 .omap4 = {
1973 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1974 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1975 .modulemode = MODULEMODE_HWCTRL,
1976 },
1977 },
1978 .opt_clks = usb_otg_ss_opt_clks,
1979 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1980 };
1981
1982 /*
1983 * 'wd_timer' class
1984 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1985 * overflow condition
1986 */
1987
1988 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1989 .rev_offs = 0x0000,
1990 .sysc_offs = 0x0010,
1991 .syss_offs = 0x0014,
1992 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1993 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1994 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1995 SIDLE_SMART_WKUP),
1996 .sysc_fields = &omap_hwmod_sysc_type1,
1997 };
1998
1999 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
2000 .name = "wd_timer",
2001 .sysc = &omap54xx_wd_timer_sysc,
2002 .pre_shutdown = &omap2_wd_timer_disable,
2003 };
2004
2005 /* wd_timer2 */
2006 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
2007 .name = "wd_timer2",
2008 .class = &omap54xx_wd_timer_hwmod_class,
2009 .clkdm_name = "wkupaon_clkdm",
2010 .main_clk = "sys_32k_ck",
2011 .prcm = {
2012 .omap4 = {
2013 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2014 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2015 .modulemode = MODULEMODE_SWCTRL,
2016 },
2017 },
2018 };
2019
2020 /*
2021 * 'ocp2scp' class
2022 * bridge to transform ocp interface protocol to scp (serial control port)
2023 * protocol
2024 */
2025 /* ocp2scp3 */
2026 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2027 /* l4_cfg -> ocp2scp3 */
2028 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2029 .master = &omap54xx_l4_cfg_hwmod,
2030 .slave = &omap54xx_ocp2scp3_hwmod,
2031 .clk = "l4_root_clk_div",
2032 .user = OCP_USER_MPU | OCP_USER_SDMA,
2033 };
2034
2035 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2036 .name = "ocp2scp3",
2037 .class = &omap54xx_ocp2scp_hwmod_class,
2038 .clkdm_name = "l3init_clkdm",
2039 .prcm = {
2040 .omap4 = {
2041 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2042 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2043 .modulemode = MODULEMODE_HWCTRL,
2044 },
2045 },
2046 };
2047
2048 /*
2049 * 'sata' class
2050 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
2051 */
2052
2053 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2054 .sysc_offs = 0x0000,
2055 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2056 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2057 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2058 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2059 .sysc_fields = &omap_hwmod_sysc_type2,
2060 };
2061
2062 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2063 .name = "sata",
2064 .sysc = &omap54xx_sata_sysc,
2065 };
2066
2067 /* sata */
2068 static struct omap_hwmod omap54xx_sata_hwmod = {
2069 .name = "sata",
2070 .class = &omap54xx_sata_hwmod_class,
2071 .clkdm_name = "l3init_clkdm",
2072 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2073 .main_clk = "func_48m_fclk",
2074 .mpu_rt_idx = 1,
2075 .prcm = {
2076 .omap4 = {
2077 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2078 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2079 .modulemode = MODULEMODE_SWCTRL,
2080 },
2081 },
2082 };
2083
2084 /* l4_cfg -> sata */
2085 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2086 .master = &omap54xx_l4_cfg_hwmod,
2087 .slave = &omap54xx_sata_hwmod,
2088 .clk = "l3_iclk_div",
2089 .user = OCP_USER_MPU | OCP_USER_SDMA,
2090 };
2091
2092 /*
2093 * Interfaces
2094 */
2095
2096 /* l3_main_1 -> dmm */
2097 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
2098 .master = &omap54xx_l3_main_1_hwmod,
2099 .slave = &omap54xx_dmm_hwmod,
2100 .clk = "l3_iclk_div",
2101 .user = OCP_USER_SDMA,
2102 };
2103
2104 /* l3_main_3 -> l3_instr */
2105 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
2106 .master = &omap54xx_l3_main_3_hwmod,
2107 .slave = &omap54xx_l3_instr_hwmod,
2108 .clk = "l3_iclk_div",
2109 .user = OCP_USER_MPU | OCP_USER_SDMA,
2110 };
2111
2112 /* l3_main_2 -> l3_main_1 */
2113 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
2114 .master = &omap54xx_l3_main_2_hwmod,
2115 .slave = &omap54xx_l3_main_1_hwmod,
2116 .clk = "l3_iclk_div",
2117 .user = OCP_USER_MPU | OCP_USER_SDMA,
2118 };
2119
2120 /* l4_cfg -> l3_main_1 */
2121 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
2122 .master = &omap54xx_l4_cfg_hwmod,
2123 .slave = &omap54xx_l3_main_1_hwmod,
2124 .clk = "l3_iclk_div",
2125 .user = OCP_USER_MPU | OCP_USER_SDMA,
2126 };
2127
2128 /* l4_cfg -> mmu_dsp */
2129 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
2130 .master = &omap54xx_l4_cfg_hwmod,
2131 .slave = &omap54xx_mmu_dsp_hwmod,
2132 .clk = "l4_root_clk_div",
2133 .user = OCP_USER_MPU | OCP_USER_SDMA,
2134 };
2135
2136 /* mpu -> l3_main_1 */
2137 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
2138 .master = &omap54xx_mpu_hwmod,
2139 .slave = &omap54xx_l3_main_1_hwmod,
2140 .clk = "l3_iclk_div",
2141 .user = OCP_USER_MPU,
2142 };
2143
2144 /* l3_main_1 -> l3_main_2 */
2145 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
2146 .master = &omap54xx_l3_main_1_hwmod,
2147 .slave = &omap54xx_l3_main_2_hwmod,
2148 .clk = "l3_iclk_div",
2149 .user = OCP_USER_MPU,
2150 };
2151
2152 /* l4_cfg -> l3_main_2 */
2153 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
2154 .master = &omap54xx_l4_cfg_hwmod,
2155 .slave = &omap54xx_l3_main_2_hwmod,
2156 .clk = "l3_iclk_div",
2157 .user = OCP_USER_MPU | OCP_USER_SDMA,
2158 };
2159
2160 /* l3_main_2 -> mmu_ipu */
2161 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
2162 .master = &omap54xx_l3_main_2_hwmod,
2163 .slave = &omap54xx_mmu_ipu_hwmod,
2164 .clk = "l3_iclk_div",
2165 .user = OCP_USER_MPU | OCP_USER_SDMA,
2166 };
2167
2168 /* l3_main_1 -> l3_main_3 */
2169 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
2170 .master = &omap54xx_l3_main_1_hwmod,
2171 .slave = &omap54xx_l3_main_3_hwmod,
2172 .clk = "l3_iclk_div",
2173 .user = OCP_USER_MPU,
2174 };
2175
2176 /* l3_main_2 -> l3_main_3 */
2177 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
2178 .master = &omap54xx_l3_main_2_hwmod,
2179 .slave = &omap54xx_l3_main_3_hwmod,
2180 .clk = "l3_iclk_div",
2181 .user = OCP_USER_MPU | OCP_USER_SDMA,
2182 };
2183
2184 /* l4_cfg -> l3_main_3 */
2185 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
2186 .master = &omap54xx_l4_cfg_hwmod,
2187 .slave = &omap54xx_l3_main_3_hwmod,
2188 .clk = "l3_iclk_div",
2189 .user = OCP_USER_MPU | OCP_USER_SDMA,
2190 };
2191
2192 /* l3_main_1 -> l4_abe */
2193 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
2194 .master = &omap54xx_l3_main_1_hwmod,
2195 .slave = &omap54xx_l4_abe_hwmod,
2196 .clk = "abe_iclk",
2197 .user = OCP_USER_MPU | OCP_USER_SDMA,
2198 };
2199
2200 /* mpu -> l4_abe */
2201 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
2202 .master = &omap54xx_mpu_hwmod,
2203 .slave = &omap54xx_l4_abe_hwmod,
2204 .clk = "abe_iclk",
2205 .user = OCP_USER_MPU | OCP_USER_SDMA,
2206 };
2207
2208 /* l3_main_1 -> l4_cfg */
2209 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
2210 .master = &omap54xx_l3_main_1_hwmod,
2211 .slave = &omap54xx_l4_cfg_hwmod,
2212 .clk = "l4_root_clk_div",
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* l3_main_2 -> l4_per */
2217 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
2218 .master = &omap54xx_l3_main_2_hwmod,
2219 .slave = &omap54xx_l4_per_hwmod,
2220 .clk = "l4_root_clk_div",
2221 .user = OCP_USER_MPU | OCP_USER_SDMA,
2222 };
2223
2224 /* l3_main_1 -> l4_wkup */
2225 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
2226 .master = &omap54xx_l3_main_1_hwmod,
2227 .slave = &omap54xx_l4_wkup_hwmod,
2228 .clk = "wkupaon_iclk_mux",
2229 .user = OCP_USER_MPU | OCP_USER_SDMA,
2230 };
2231
2232 /* mpu -> mpu_private */
2233 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
2234 .master = &omap54xx_mpu_hwmod,
2235 .slave = &omap54xx_mpu_private_hwmod,
2236 .clk = "l3_iclk_div",
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2238 };
2239
2240 /* l4_wkup -> counter_32k */
2241 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
2242 .master = &omap54xx_l4_wkup_hwmod,
2243 .slave = &omap54xx_counter_32k_hwmod,
2244 .clk = "wkupaon_iclk_mux",
2245 .user = OCP_USER_MPU | OCP_USER_SDMA,
2246 };
2247
2248 /* l4_cfg -> dma_system */
2249 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
2250 .master = &omap54xx_l4_cfg_hwmod,
2251 .slave = &omap54xx_dma_system_hwmod,
2252 .clk = "l4_root_clk_div",
2253 .user = OCP_USER_MPU | OCP_USER_SDMA,
2254 };
2255
2256 /* l4_abe -> dmic */
2257 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
2258 .master = &omap54xx_l4_abe_hwmod,
2259 .slave = &omap54xx_dmic_hwmod,
2260 .clk = "abe_iclk",
2261 .user = OCP_USER_MPU,
2262 };
2263
2264 /* l3_main_2 -> dss */
2265 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2266 .master = &omap54xx_l3_main_2_hwmod,
2267 .slave = &omap54xx_dss_hwmod,
2268 .clk = "l3_iclk_div",
2269 .user = OCP_USER_MPU | OCP_USER_SDMA,
2270 };
2271
2272 /* l3_main_2 -> dss_dispc */
2273 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2274 .master = &omap54xx_l3_main_2_hwmod,
2275 .slave = &omap54xx_dss_dispc_hwmod,
2276 .clk = "l3_iclk_div",
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2278 };
2279
2280 /* l3_main_2 -> dss_dsi1_a */
2281 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2282 .master = &omap54xx_l3_main_2_hwmod,
2283 .slave = &omap54xx_dss_dsi1_a_hwmod,
2284 .clk = "l3_iclk_div",
2285 .user = OCP_USER_MPU | OCP_USER_SDMA,
2286 };
2287
2288 /* l3_main_2 -> dss_dsi1_c */
2289 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2290 .master = &omap54xx_l3_main_2_hwmod,
2291 .slave = &omap54xx_dss_dsi1_c_hwmod,
2292 .clk = "l3_iclk_div",
2293 .user = OCP_USER_MPU | OCP_USER_SDMA,
2294 };
2295
2296 /* l3_main_2 -> dss_hdmi */
2297 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2298 .master = &omap54xx_l3_main_2_hwmod,
2299 .slave = &omap54xx_dss_hdmi_hwmod,
2300 .clk = "l3_iclk_div",
2301 .user = OCP_USER_MPU | OCP_USER_SDMA,
2302 };
2303
2304 /* l3_main_2 -> dss_rfbi */
2305 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2306 .master = &omap54xx_l3_main_2_hwmod,
2307 .slave = &omap54xx_dss_rfbi_hwmod,
2308 .clk = "l3_iclk_div",
2309 .user = OCP_USER_MPU | OCP_USER_SDMA,
2310 };
2311
2312 /* mpu -> emif1 */
2313 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
2314 .master = &omap54xx_mpu_hwmod,
2315 .slave = &omap54xx_emif1_hwmod,
2316 .clk = "dpll_core_h11x2_ck",
2317 .user = OCP_USER_MPU | OCP_USER_SDMA,
2318 };
2319
2320 /* mpu -> emif2 */
2321 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
2322 .master = &omap54xx_mpu_hwmod,
2323 .slave = &omap54xx_emif2_hwmod,
2324 .clk = "dpll_core_h11x2_ck",
2325 .user = OCP_USER_MPU | OCP_USER_SDMA,
2326 };
2327
2328 /* l4_wkup -> gpio1 */
2329 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
2330 .master = &omap54xx_l4_wkup_hwmod,
2331 .slave = &omap54xx_gpio1_hwmod,
2332 .clk = "wkupaon_iclk_mux",
2333 .user = OCP_USER_MPU | OCP_USER_SDMA,
2334 };
2335
2336 /* l4_per -> gpio2 */
2337 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2338 .master = &omap54xx_l4_per_hwmod,
2339 .slave = &omap54xx_gpio2_hwmod,
2340 .clk = "l4_root_clk_div",
2341 .user = OCP_USER_MPU | OCP_USER_SDMA,
2342 };
2343
2344 /* l4_per -> gpio3 */
2345 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2346 .master = &omap54xx_l4_per_hwmod,
2347 .slave = &omap54xx_gpio3_hwmod,
2348 .clk = "l4_root_clk_div",
2349 .user = OCP_USER_MPU | OCP_USER_SDMA,
2350 };
2351
2352 /* l4_per -> gpio4 */
2353 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2354 .master = &omap54xx_l4_per_hwmod,
2355 .slave = &omap54xx_gpio4_hwmod,
2356 .clk = "l4_root_clk_div",
2357 .user = OCP_USER_MPU | OCP_USER_SDMA,
2358 };
2359
2360 /* l4_per -> gpio5 */
2361 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2362 .master = &omap54xx_l4_per_hwmod,
2363 .slave = &omap54xx_gpio5_hwmod,
2364 .clk = "l4_root_clk_div",
2365 .user = OCP_USER_MPU | OCP_USER_SDMA,
2366 };
2367
2368 /* l4_per -> gpio6 */
2369 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2370 .master = &omap54xx_l4_per_hwmod,
2371 .slave = &omap54xx_gpio6_hwmod,
2372 .clk = "l4_root_clk_div",
2373 .user = OCP_USER_MPU | OCP_USER_SDMA,
2374 };
2375
2376 /* l4_per -> gpio7 */
2377 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2378 .master = &omap54xx_l4_per_hwmod,
2379 .slave = &omap54xx_gpio7_hwmod,
2380 .clk = "l4_root_clk_div",
2381 .user = OCP_USER_MPU | OCP_USER_SDMA,
2382 };
2383
2384 /* l4_per -> gpio8 */
2385 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2386 .master = &omap54xx_l4_per_hwmod,
2387 .slave = &omap54xx_gpio8_hwmod,
2388 .clk = "l4_root_clk_div",
2389 .user = OCP_USER_MPU | OCP_USER_SDMA,
2390 };
2391
2392 /* l4_per -> i2c1 */
2393 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2394 .master = &omap54xx_l4_per_hwmod,
2395 .slave = &omap54xx_i2c1_hwmod,
2396 .clk = "l4_root_clk_div",
2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2398 };
2399
2400 /* l4_per -> i2c2 */
2401 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2402 .master = &omap54xx_l4_per_hwmod,
2403 .slave = &omap54xx_i2c2_hwmod,
2404 .clk = "l4_root_clk_div",
2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406 };
2407
2408 /* l4_per -> i2c3 */
2409 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2410 .master = &omap54xx_l4_per_hwmod,
2411 .slave = &omap54xx_i2c3_hwmod,
2412 .clk = "l4_root_clk_div",
2413 .user = OCP_USER_MPU | OCP_USER_SDMA,
2414 };
2415
2416 /* l4_per -> i2c4 */
2417 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2418 .master = &omap54xx_l4_per_hwmod,
2419 .slave = &omap54xx_i2c4_hwmod,
2420 .clk = "l4_root_clk_div",
2421 .user = OCP_USER_MPU | OCP_USER_SDMA,
2422 };
2423
2424 /* l4_per -> i2c5 */
2425 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2426 .master = &omap54xx_l4_per_hwmod,
2427 .slave = &omap54xx_i2c5_hwmod,
2428 .clk = "l4_root_clk_div",
2429 .user = OCP_USER_MPU | OCP_USER_SDMA,
2430 };
2431
2432 /* l4_wkup -> kbd */
2433 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2434 .master = &omap54xx_l4_wkup_hwmod,
2435 .slave = &omap54xx_kbd_hwmod,
2436 .clk = "wkupaon_iclk_mux",
2437 .user = OCP_USER_MPU | OCP_USER_SDMA,
2438 };
2439
2440 /* l4_cfg -> mailbox */
2441 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2442 .master = &omap54xx_l4_cfg_hwmod,
2443 .slave = &omap54xx_mailbox_hwmod,
2444 .clk = "l4_root_clk_div",
2445 .user = OCP_USER_MPU | OCP_USER_SDMA,
2446 };
2447
2448 /* l4_abe -> mcbsp1 */
2449 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2450 .master = &omap54xx_l4_abe_hwmod,
2451 .slave = &omap54xx_mcbsp1_hwmod,
2452 .clk = "abe_iclk",
2453 .user = OCP_USER_MPU,
2454 };
2455
2456 /* l4_abe -> mcbsp2 */
2457 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2458 .master = &omap54xx_l4_abe_hwmod,
2459 .slave = &omap54xx_mcbsp2_hwmod,
2460 .clk = "abe_iclk",
2461 .user = OCP_USER_MPU,
2462 };
2463
2464 /* l4_abe -> mcbsp3 */
2465 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2466 .master = &omap54xx_l4_abe_hwmod,
2467 .slave = &omap54xx_mcbsp3_hwmod,
2468 .clk = "abe_iclk",
2469 .user = OCP_USER_MPU,
2470 };
2471
2472 /* l4_abe -> mcpdm */
2473 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2474 .master = &omap54xx_l4_abe_hwmod,
2475 .slave = &omap54xx_mcpdm_hwmod,
2476 .clk = "abe_iclk",
2477 .user = OCP_USER_MPU,
2478 };
2479
2480 /* l4_per -> mcspi1 */
2481 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2482 .master = &omap54xx_l4_per_hwmod,
2483 .slave = &omap54xx_mcspi1_hwmod,
2484 .clk = "l4_root_clk_div",
2485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486 };
2487
2488 /* l4_per -> mcspi2 */
2489 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2490 .master = &omap54xx_l4_per_hwmod,
2491 .slave = &omap54xx_mcspi2_hwmod,
2492 .clk = "l4_root_clk_div",
2493 .user = OCP_USER_MPU | OCP_USER_SDMA,
2494 };
2495
2496 /* l4_per -> mcspi3 */
2497 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2498 .master = &omap54xx_l4_per_hwmod,
2499 .slave = &omap54xx_mcspi3_hwmod,
2500 .clk = "l4_root_clk_div",
2501 .user = OCP_USER_MPU | OCP_USER_SDMA,
2502 };
2503
2504 /* l4_per -> mcspi4 */
2505 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2506 .master = &omap54xx_l4_per_hwmod,
2507 .slave = &omap54xx_mcspi4_hwmod,
2508 .clk = "l4_root_clk_div",
2509 .user = OCP_USER_MPU | OCP_USER_SDMA,
2510 };
2511
2512 /* l4_per -> mmc1 */
2513 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2514 .master = &omap54xx_l4_per_hwmod,
2515 .slave = &omap54xx_mmc1_hwmod,
2516 .clk = "l3_iclk_div",
2517 .user = OCP_USER_MPU | OCP_USER_SDMA,
2518 };
2519
2520 /* l4_per -> mmc2 */
2521 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2522 .master = &omap54xx_l4_per_hwmod,
2523 .slave = &omap54xx_mmc2_hwmod,
2524 .clk = "l3_iclk_div",
2525 .user = OCP_USER_MPU | OCP_USER_SDMA,
2526 };
2527
2528 /* l4_per -> mmc3 */
2529 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2530 .master = &omap54xx_l4_per_hwmod,
2531 .slave = &omap54xx_mmc3_hwmod,
2532 .clk = "l4_root_clk_div",
2533 .user = OCP_USER_MPU | OCP_USER_SDMA,
2534 };
2535
2536 /* l4_per -> mmc4 */
2537 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2538 .master = &omap54xx_l4_per_hwmod,
2539 .slave = &omap54xx_mmc4_hwmod,
2540 .clk = "l4_root_clk_div",
2541 .user = OCP_USER_MPU | OCP_USER_SDMA,
2542 };
2543
2544 /* l4_per -> mmc5 */
2545 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2546 .master = &omap54xx_l4_per_hwmod,
2547 .slave = &omap54xx_mmc5_hwmod,
2548 .clk = "l4_root_clk_div",
2549 .user = OCP_USER_MPU | OCP_USER_SDMA,
2550 };
2551
2552 /* l4_cfg -> mpu */
2553 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2554 .master = &omap54xx_l4_cfg_hwmod,
2555 .slave = &omap54xx_mpu_hwmod,
2556 .clk = "l4_root_clk_div",
2557 .user = OCP_USER_MPU | OCP_USER_SDMA,
2558 };
2559
2560 /* l4_cfg -> spinlock */
2561 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2562 .master = &omap54xx_l4_cfg_hwmod,
2563 .slave = &omap54xx_spinlock_hwmod,
2564 .clk = "l4_root_clk_div",
2565 .user = OCP_USER_MPU | OCP_USER_SDMA,
2566 };
2567
2568 /* l4_cfg -> ocp2scp1 */
2569 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2570 .master = &omap54xx_l4_cfg_hwmod,
2571 .slave = &omap54xx_ocp2scp1_hwmod,
2572 .clk = "l4_root_clk_div",
2573 .user = OCP_USER_MPU | OCP_USER_SDMA,
2574 };
2575
2576 /* l4_wkup -> timer1 */
2577 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2578 .master = &omap54xx_l4_wkup_hwmod,
2579 .slave = &omap54xx_timer1_hwmod,
2580 .clk = "wkupaon_iclk_mux",
2581 .user = OCP_USER_MPU | OCP_USER_SDMA,
2582 };
2583
2584 /* l4_per -> timer2 */
2585 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2586 .master = &omap54xx_l4_per_hwmod,
2587 .slave = &omap54xx_timer2_hwmod,
2588 .clk = "l4_root_clk_div",
2589 .user = OCP_USER_MPU | OCP_USER_SDMA,
2590 };
2591
2592 /* l4_per -> timer3 */
2593 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2594 .master = &omap54xx_l4_per_hwmod,
2595 .slave = &omap54xx_timer3_hwmod,
2596 .clk = "l4_root_clk_div",
2597 .user = OCP_USER_MPU | OCP_USER_SDMA,
2598 };
2599
2600 /* l4_per -> timer4 */
2601 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2602 .master = &omap54xx_l4_per_hwmod,
2603 .slave = &omap54xx_timer4_hwmod,
2604 .clk = "l4_root_clk_div",
2605 .user = OCP_USER_MPU | OCP_USER_SDMA,
2606 };
2607
2608 /* l4_abe -> timer5 */
2609 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2610 .master = &omap54xx_l4_abe_hwmod,
2611 .slave = &omap54xx_timer5_hwmod,
2612 .clk = "abe_iclk",
2613 .user = OCP_USER_MPU,
2614 };
2615
2616 /* l4_abe -> timer6 */
2617 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2618 .master = &omap54xx_l4_abe_hwmod,
2619 .slave = &omap54xx_timer6_hwmod,
2620 .clk = "abe_iclk",
2621 .user = OCP_USER_MPU,
2622 };
2623
2624 /* l4_abe -> timer7 */
2625 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2626 .master = &omap54xx_l4_abe_hwmod,
2627 .slave = &omap54xx_timer7_hwmod,
2628 .clk = "abe_iclk",
2629 .user = OCP_USER_MPU,
2630 };
2631
2632 /* l4_abe -> timer8 */
2633 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2634 .master = &omap54xx_l4_abe_hwmod,
2635 .slave = &omap54xx_timer8_hwmod,
2636 .clk = "abe_iclk",
2637 .user = OCP_USER_MPU,
2638 };
2639
2640 /* l4_per -> timer9 */
2641 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2642 .master = &omap54xx_l4_per_hwmod,
2643 .slave = &omap54xx_timer9_hwmod,
2644 .clk = "l4_root_clk_div",
2645 .user = OCP_USER_MPU | OCP_USER_SDMA,
2646 };
2647
2648 /* l4_per -> timer10 */
2649 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2650 .master = &omap54xx_l4_per_hwmod,
2651 .slave = &omap54xx_timer10_hwmod,
2652 .clk = "l4_root_clk_div",
2653 .user = OCP_USER_MPU | OCP_USER_SDMA,
2654 };
2655
2656 /* l4_per -> timer11 */
2657 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2658 .master = &omap54xx_l4_per_hwmod,
2659 .slave = &omap54xx_timer11_hwmod,
2660 .clk = "l4_root_clk_div",
2661 .user = OCP_USER_MPU | OCP_USER_SDMA,
2662 };
2663
2664 /* l4_per -> uart1 */
2665 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2666 .master = &omap54xx_l4_per_hwmod,
2667 .slave = &omap54xx_uart1_hwmod,
2668 .clk = "l4_root_clk_div",
2669 .user = OCP_USER_MPU | OCP_USER_SDMA,
2670 };
2671
2672 /* l4_per -> uart2 */
2673 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2674 .master = &omap54xx_l4_per_hwmod,
2675 .slave = &omap54xx_uart2_hwmod,
2676 .clk = "l4_root_clk_div",
2677 .user = OCP_USER_MPU | OCP_USER_SDMA,
2678 };
2679
2680 /* l4_per -> uart3 */
2681 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2682 .master = &omap54xx_l4_per_hwmod,
2683 .slave = &omap54xx_uart3_hwmod,
2684 .clk = "l4_root_clk_div",
2685 .user = OCP_USER_MPU | OCP_USER_SDMA,
2686 };
2687
2688 /* l4_per -> uart4 */
2689 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2690 .master = &omap54xx_l4_per_hwmod,
2691 .slave = &omap54xx_uart4_hwmod,
2692 .clk = "l4_root_clk_div",
2693 .user = OCP_USER_MPU | OCP_USER_SDMA,
2694 };
2695
2696 /* l4_per -> uart5 */
2697 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2698 .master = &omap54xx_l4_per_hwmod,
2699 .slave = &omap54xx_uart5_hwmod,
2700 .clk = "l4_root_clk_div",
2701 .user = OCP_USER_MPU | OCP_USER_SDMA,
2702 };
2703
2704 /* l4_per -> uart6 */
2705 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2706 .master = &omap54xx_l4_per_hwmod,
2707 .slave = &omap54xx_uart6_hwmod,
2708 .clk = "l4_root_clk_div",
2709 .user = OCP_USER_MPU | OCP_USER_SDMA,
2710 };
2711
2712 /* l4_cfg -> usb_host_hs */
2713 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2714 .master = &omap54xx_l4_cfg_hwmod,
2715 .slave = &omap54xx_usb_host_hs_hwmod,
2716 .clk = "l3_iclk_div",
2717 .user = OCP_USER_MPU | OCP_USER_SDMA,
2718 };
2719
2720 /* l4_cfg -> usb_tll_hs */
2721 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2722 .master = &omap54xx_l4_cfg_hwmod,
2723 .slave = &omap54xx_usb_tll_hs_hwmod,
2724 .clk = "l4_root_clk_div",
2725 .user = OCP_USER_MPU | OCP_USER_SDMA,
2726 };
2727
2728 /* l4_cfg -> usb_otg_ss */
2729 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2730 .master = &omap54xx_l4_cfg_hwmod,
2731 .slave = &omap54xx_usb_otg_ss_hwmod,
2732 .clk = "dpll_core_h13x2_ck",
2733 .user = OCP_USER_MPU | OCP_USER_SDMA,
2734 };
2735
2736 /* l4_wkup -> wd_timer2 */
2737 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2738 .master = &omap54xx_l4_wkup_hwmod,
2739 .slave = &omap54xx_wd_timer2_hwmod,
2740 .clk = "wkupaon_iclk_mux",
2741 .user = OCP_USER_MPU | OCP_USER_SDMA,
2742 };
2743
2744 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2745 &omap54xx_l3_main_1__dmm,
2746 &omap54xx_l3_main_3__l3_instr,
2747 &omap54xx_l3_main_2__l3_main_1,
2748 &omap54xx_l4_cfg__l3_main_1,
2749 &omap54xx_mpu__l3_main_1,
2750 &omap54xx_l3_main_1__l3_main_2,
2751 &omap54xx_l4_cfg__l3_main_2,
2752 &omap54xx_l3_main_1__l3_main_3,
2753 &omap54xx_l3_main_2__l3_main_3,
2754 &omap54xx_l4_cfg__l3_main_3,
2755 &omap54xx_l3_main_1__l4_abe,
2756 &omap54xx_mpu__l4_abe,
2757 &omap54xx_l3_main_1__l4_cfg,
2758 &omap54xx_l3_main_2__l4_per,
2759 &omap54xx_l3_main_1__l4_wkup,
2760 &omap54xx_mpu__mpu_private,
2761 &omap54xx_l4_wkup__counter_32k,
2762 &omap54xx_l4_cfg__dma_system,
2763 &omap54xx_l4_abe__dmic,
2764 &omap54xx_l4_cfg__mmu_dsp,
2765 &omap54xx_l3_main_2__dss,
2766 &omap54xx_l3_main_2__dss_dispc,
2767 &omap54xx_l3_main_2__dss_dsi1_a,
2768 &omap54xx_l3_main_2__dss_dsi1_c,
2769 &omap54xx_l3_main_2__dss_hdmi,
2770 &omap54xx_l3_main_2__dss_rfbi,
2771 &omap54xx_mpu__emif1,
2772 &omap54xx_mpu__emif2,
2773 &omap54xx_l4_wkup__gpio1,
2774 &omap54xx_l4_per__gpio2,
2775 &omap54xx_l4_per__gpio3,
2776 &omap54xx_l4_per__gpio4,
2777 &omap54xx_l4_per__gpio5,
2778 &omap54xx_l4_per__gpio6,
2779 &omap54xx_l4_per__gpio7,
2780 &omap54xx_l4_per__gpio8,
2781 &omap54xx_l4_per__i2c1,
2782 &omap54xx_l4_per__i2c2,
2783 &omap54xx_l4_per__i2c3,
2784 &omap54xx_l4_per__i2c4,
2785 &omap54xx_l4_per__i2c5,
2786 &omap54xx_l3_main_2__mmu_ipu,
2787 &omap54xx_l4_wkup__kbd,
2788 &omap54xx_l4_cfg__mailbox,
2789 &omap54xx_l4_abe__mcbsp1,
2790 &omap54xx_l4_abe__mcbsp2,
2791 &omap54xx_l4_abe__mcbsp3,
2792 &omap54xx_l4_abe__mcpdm,
2793 &omap54xx_l4_per__mcspi1,
2794 &omap54xx_l4_per__mcspi2,
2795 &omap54xx_l4_per__mcspi3,
2796 &omap54xx_l4_per__mcspi4,
2797 &omap54xx_l4_per__mmc1,
2798 &omap54xx_l4_per__mmc2,
2799 &omap54xx_l4_per__mmc3,
2800 &omap54xx_l4_per__mmc4,
2801 &omap54xx_l4_per__mmc5,
2802 &omap54xx_l4_cfg__mpu,
2803 &omap54xx_l4_cfg__spinlock,
2804 &omap54xx_l4_cfg__ocp2scp1,
2805 &omap54xx_l4_wkup__timer1,
2806 &omap54xx_l4_per__timer2,
2807 &omap54xx_l4_per__timer3,
2808 &omap54xx_l4_per__timer4,
2809 &omap54xx_l4_abe__timer5,
2810 &omap54xx_l4_abe__timer6,
2811 &omap54xx_l4_abe__timer7,
2812 &omap54xx_l4_abe__timer8,
2813 &omap54xx_l4_per__timer9,
2814 &omap54xx_l4_per__timer10,
2815 &omap54xx_l4_per__timer11,
2816 &omap54xx_l4_per__uart1,
2817 &omap54xx_l4_per__uart2,
2818 &omap54xx_l4_per__uart3,
2819 &omap54xx_l4_per__uart4,
2820 &omap54xx_l4_per__uart5,
2821 &omap54xx_l4_per__uart6,
2822 &omap54xx_l4_cfg__usb_host_hs,
2823 &omap54xx_l4_cfg__usb_tll_hs,
2824 &omap54xx_l4_cfg__usb_otg_ss,
2825 &omap54xx_l4_wkup__wd_timer2,
2826 &omap54xx_l4_cfg__ocp2scp3,
2827 &omap54xx_l4_cfg__sata,
2828 NULL,
2829 };
2830
2831 int __init omap54xx_hwmod_init(void)
2832 {
2833 omap_hwmod_init();
2834 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2835 }
CRIS linux kernel tree