arch/arm64/include/asm/module.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_MODULE_H
  17 #define __ASM_MODULE_H
  18
  19 #include <asm-generic/module.h>
  20
  21 #define MODULE_ARCH_VERMAGIC    "aarch64"
  22
  23 #ifdef CONFIG_ARM64_MODULE_PLTS
  24 struct mod_plt_sec {
  25         struct elf64_shdr       *plt;
  26         int                     plt_num_entries;
  27         int                     plt_max_entries;
  28 };
  29
  30 struct mod_arch_specific {
  31         struct mod_plt_sec      core;
  32         struct mod_plt_sec      init;
  33
  34         /* for CONFIG_DYNAMIC_FTRACE */
  35         struct plt_entry        *ftrace_trampoline;
  36 };
  37 #endif
  38
  39 u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela,
  40                           Elf64_Sym *sym);
  41
  42 #ifdef CONFIG_RANDOMIZE_BASE
  43 extern u64 module_alloc_base;
  44 #else
  45 #define module_alloc_base       ((u64)_etext - MODULES_VSIZE)
  46 #endif
  47
  48 struct plt_entry {
  49         /*
  50          * A program that conforms to the AArch64 Procedure Call Standard
  51          * (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or
  52          * IP1 (x17) may be inserted at any branch instruction that is
  53          * exposed to a relocation that supports long branches. Since that
  54          * is exactly what we are dealing with here, we are free to use x16
  55          * as a scratch register in the PLT veneers.
  56          */
  57         __le32  mov0;   /* movn x16, #0x....                    */
  58         __le32  mov1;   /* movk x16, #0x...., lsl #16           */
  59         __le32  mov2;   /* movk x16, #0x...., lsl #32           */
  60         __le32  br;     /* br   x16                             */
  61 };
  62
  63 static inline struct plt_entry get_plt_entry(u64 val)
  64 {
  65         /*
  66          * MOVK/MOVN/MOVZ opcode:
  67          * +--------+------------+--------+-----------+-------------+---------+
  68          * | sf[31] | opc[30:29] | 100101 | hw[22:21] | imm16[20:5] | Rd[4:0] |
  69          * +--------+------------+--------+-----------+-------------+---------+
  70          *
  71          * Rd     := 0x10 (x16)
  72          * hw     := 0b00 (no shift), 0b01 (lsl #16), 0b10 (lsl #32)
  73          * opc    := 0b11 (MOVK), 0b00 (MOVN), 0b10 (MOVZ)
  74          * sf     := 1 (64-bit variant)
  75          */
  76         return (struct plt_entry){
  77                 cpu_to_le32(0x92800010 | (((~val      ) & 0xffff)) << 5),
  78                 cpu_to_le32(0xf2a00010 | ((( val >> 16) & 0xffff)) << 5),
  79                 cpu_to_le32(0xf2c00010 | ((( val >> 32) & 0xffff)) << 5),
  80                 cpu_to_le32(0xd61f0200)
  81         };
  82 }
  83
  84 static inline bool plt_entries_equal(const struct plt_entry *a,
  85                                      const struct plt_entry *b)
  86 {
  87         return a->mov0 == b->mov0 &&
  88                a->mov1 == b->mov1 &&
  89                a->mov2 == b->mov2;
  90 }
  91
  92 #endif /* __ASM_MODULE_H */