1 // SPDX-License-Identifier: GPL-2.0
44 compatible = "simple-bus";
45 model = "tms320c6472";
50 core_pic: interrupt-controller {
51 compatible = "ti,c64x+core-pic";
53 #interrupt-cells = <1>;
56 megamod_pic: interrupt-controller@1800000 {
57 compatible = "ti,c64x+megamod-pic";
59 #interrupt-cells = <1>;
60 reg = <0x1800000 0x1000>;
61 interrupt-parent = <&core_pic>;
64 cache-controller@1840000 {
65 compatible = "ti,c64x+cache";
66 reg = <0x01840000 0x8400>;
69 timer0: timer@25e0000 {
70 compatible = "ti,c64x+timer64";
71 ti,core-mask = < 0x01 >;
72 reg = <0x25e0000 0x40>;
75 timer1: timer@25f0000 {
76 compatible = "ti,c64x+timer64";
77 ti,core-mask = < 0x02 >;
78 reg = <0x25f0000 0x40>;
81 timer2: timer@2600000 {
82 compatible = "ti,c64x+timer64";
83 ti,core-mask = < 0x04 >;
84 reg = <0x2600000 0x40>;
87 timer3: timer@2610000 {
88 compatible = "ti,c64x+timer64";
89 ti,core-mask = < 0x08 >;
90 reg = <0x2610000 0x40>;
93 timer4: timer@2620000 {
94 compatible = "ti,c64x+timer64";
95 ti,core-mask = < 0x10 >;
96 reg = <0x2620000 0x40>;
99 timer5: timer@2630000 {
100 compatible = "ti,c64x+timer64";
101 ti,core-mask = < 0x20 >;
102 reg = <0x2630000 0x40>;
105 clock-controller@29a0000 {
106 compatible = "ti,c6472-pll", "ti,c64x+pll";
107 reg = <0x029a0000 0x200>;
108 ti,c64x+pll-bypass-delay = <200>;
109 ti,c64x+pll-reset-delay = <12000>;
110 ti,c64x+pll-lock-delay = <80000>;
113 device-state-controller@2a80000 {
114 compatible = "ti,c64x+dscr";
115 reg = <0x02a80000 0x1000>;
117 ti,dscr-devstat = <0>;
118 ti,dscr-silicon-rev = <0x70c 16 0xff>;
120 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
123 ti,dscr-rmii-resets = <0x208 1
126 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
130 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
132 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;