arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __intr_vect_defs_h
   3 #define __intr_vect_defs_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           ../../inst/intr_vect/rtl/guinness/ivmask.config.r
   8  *     id:           ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
   9  *     last modfied: Mon Apr 11 16:08:03 2005
  10  *
  11  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
  12  *      id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
  13  * Any changes here will be lost.
  14  *
  15  * -*- buffer-read-only: t -*-
  16  */
  17 /* Main access macros */
  18 #ifndef REG_RD
  19 #define REG_RD( scope, inst, reg ) \
  20   REG_READ( reg_##scope##_##reg, \
  21             (inst) + REG_RD_ADDR_##scope##_##reg )
  22 #endif
  23
  24 #ifndef REG_WR
  25 #define REG_WR( scope, inst, reg, val ) \
  26   REG_WRITE( reg_##scope##_##reg, \
  27              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  28 #endif
  29
  30 #ifndef REG_RD_VECT
  31 #define REG_RD_VECT( scope, inst, reg, index ) \
  32   REG_READ( reg_##scope##_##reg, \
  33             (inst) + REG_RD_ADDR_##scope##_##reg + \
  34             (index) * STRIDE_##scope##_##reg )
  35 #endif
  36
  37 #ifndef REG_WR_VECT
  38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  39   REG_WRITE( reg_##scope##_##reg, \
  40              (inst) + REG_WR_ADDR_##scope##_##reg + \
  41              (index) * STRIDE_##scope##_##reg, (val) )
  42 #endif
  43
  44 #ifndef REG_RD_INT
  45 #define REG_RD_INT( scope, inst, reg ) \
  46   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  47 #endif
  48
  49 #ifndef REG_WR_INT
  50 #define REG_WR_INT( scope, inst, reg, val ) \
  51   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  52 #endif
  53
  54 #ifndef REG_RD_INT_VECT
  55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  56   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  57             (index) * STRIDE_##scope##_##reg )
  58 #endif
  59
  60 #ifndef REG_WR_INT_VECT
  61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  62   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  63              (index) * STRIDE_##scope##_##reg, (val) )
  64 #endif
  65
  66 #ifndef REG_TYPE_CONV
  67 #define REG_TYPE_CONV( type, orgtype, val ) \
  68   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  69 #endif
  70
  71 #ifndef reg_page_size
  72 #define reg_page_size 8192
  73 #endif
  74
  75 #ifndef REG_ADDR
  76 #define REG_ADDR( scope, inst, reg ) \
  77   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  78 #endif
  79
  80 #ifndef REG_ADDR_VECT
  81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  82   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  83     (index) * STRIDE_##scope##_##reg )
  84 #endif
  85
  86 /* C-code for register scope intr_vect */
  87
  88 #define STRIDE_intr_vect_rw_mask 0
  89 /* Register rw_mask, scope intr_vect, type rw */
  90 typedef struct {
  91   unsigned int memarb  : 1;
  92   unsigned int gen_io  : 1;
  93   unsigned int iop0    : 1;
  94   unsigned int iop1    : 1;
  95   unsigned int iop2    : 1;
  96   unsigned int iop3    : 1;
  97   unsigned int dma0    : 1;
  98   unsigned int dma1    : 1;
  99   unsigned int dma2    : 1;
 100   unsigned int dma3    : 1;
 101   unsigned int dma4    : 1;
 102   unsigned int dma5    : 1;
 103   unsigned int dma6    : 1;
 104   unsigned int dma7    : 1;
 105   unsigned int dma8    : 1;
 106   unsigned int dma9    : 1;
 107   unsigned int ata     : 1;
 108   unsigned int sser0   : 1;
 109   unsigned int sser1   : 1;
 110   unsigned int ser0    : 1;
 111   unsigned int ser1    : 1;
 112   unsigned int ser2    : 1;
 113   unsigned int ser3    : 1;
 114   unsigned int p21     : 1;
 115   unsigned int eth0    : 1;
 116   unsigned int eth1    : 1;
 117   unsigned int timer0  : 1;
 118   unsigned int bif_arb : 1;
 119   unsigned int bif_dma : 1;
 120   unsigned int ext     : 1;
 121   unsigned int dummy1  : 2;
 122 } reg_intr_vect_rw_mask;
 123 #define REG_RD_ADDR_intr_vect_rw_mask 0
 124 #define REG_WR_ADDR_intr_vect_rw_mask 0
 125
 126 #define STRIDE_intr_vect_r_vect 0
 127 /* Register r_vect, scope intr_vect, type r */
 128 typedef struct {
 129   unsigned int memarb  : 1;
 130   unsigned int gen_io  : 1;
 131   unsigned int iop0    : 1;
 132   unsigned int iop1    : 1;
 133   unsigned int iop2    : 1;
 134   unsigned int iop3    : 1;
 135   unsigned int dma0    : 1;
 136   unsigned int dma1    : 1;
 137   unsigned int dma2    : 1;
 138   unsigned int dma3    : 1;
 139   unsigned int dma4    : 1;
 140   unsigned int dma5    : 1;
 141   unsigned int dma6    : 1;
 142   unsigned int dma7    : 1;
 143   unsigned int dma8    : 1;
 144   unsigned int dma9    : 1;
 145   unsigned int ata     : 1;
 146   unsigned int sser0   : 1;
 147   unsigned int sser1   : 1;
 148   unsigned int ser0    : 1;
 149   unsigned int ser1    : 1;
 150   unsigned int ser2    : 1;
 151   unsigned int ser3    : 1;
 152   unsigned int p21     : 1;
 153   unsigned int eth0    : 1;
 154   unsigned int eth1    : 1;
 155   unsigned int timer   : 1;
 156   unsigned int bif_arb : 1;
 157   unsigned int bif_dma : 1;
 158   unsigned int ext     : 1;
 159   unsigned int dummy1  : 2;
 160 } reg_intr_vect_r_vect;
 161 #define REG_RD_ADDR_intr_vect_r_vect 4
 162
 163 #define STRIDE_intr_vect_r_masked_vect 0
 164 /* Register r_masked_vect, scope intr_vect, type r */
 165 typedef struct {
 166   unsigned int memarb  : 1;
 167   unsigned int gen_io  : 1;
 168   unsigned int iop0    : 1;
 169   unsigned int iop1    : 1;
 170   unsigned int iop2    : 1;
 171   unsigned int iop3    : 1;
 172   unsigned int dma0    : 1;
 173   unsigned int dma1    : 1;
 174   unsigned int dma2    : 1;
 175   unsigned int dma3    : 1;
 176   unsigned int dma4    : 1;
 177   unsigned int dma5    : 1;
 178   unsigned int dma6    : 1;
 179   unsigned int dma7    : 1;
 180   unsigned int dma8    : 1;
 181   unsigned int dma9    : 1;
 182   unsigned int ata     : 1;
 183   unsigned int sser0   : 1;
 184   unsigned int sser1   : 1;
 185   unsigned int ser0    : 1;
 186   unsigned int ser1    : 1;
 187   unsigned int ser2    : 1;
 188   unsigned int ser3    : 1;
 189   unsigned int p21     : 1;
 190   unsigned int eth0    : 1;
 191   unsigned int eth1    : 1;
 192   unsigned int timer   : 1;
 193   unsigned int bif_arb : 1;
 194   unsigned int bif_dma : 1;
 195   unsigned int ext     : 1;
 196   unsigned int dummy1  : 2;
 197 } reg_intr_vect_r_masked_vect;
 198 #define REG_RD_ADDR_intr_vect_r_masked_vect 8
 199
 200 /* Register r_nmi, scope intr_vect, type r */
 201 typedef struct {
 202   unsigned int ext      : 1;
 203   unsigned int watchdog : 1;
 204   unsigned int dummy1   : 30;
 205 } reg_intr_vect_r_nmi;
 206 #define REG_RD_ADDR_intr_vect_r_nmi 12
 207
 208 /* Register r_guru, scope intr_vect, type r */
 209 typedef struct {
 210   unsigned int jtag : 1;
 211   unsigned int dummy1 : 31;
 212 } reg_intr_vect_r_guru;
 213 #define REG_RD_ADDR_intr_vect_r_guru 16
 214
 215 /* Register rw_ipi, scope intr_vect, type rw */
 216 typedef struct
 217 {
 218   unsigned int vector;
 219 } reg_intr_vect_rw_ipi;
 220 #define REG_RD_ADDR_intr_vect_rw_ipi 20
 221 #define REG_WR_ADDR_intr_vect_rw_ipi 20
 222
 223 /* Constants */
 224 enum {
 225   regk_intr_vect_off                       = 0x00000000,
 226   regk_intr_vect_on                        = 0x00000001,
 227   regk_intr_vect_rw_mask_default           = 0x00000000
 228 };
 229 #endif /* __intr_vect_defs_h */