arch/x86/include/asm/mce.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_MCE_H
   3 #define _ASM_X86_MCE_H
   4
   5 #include <uapi/asm/mce.h>
   6
   7 /*
   8  * Machine Check support for x86
   9  */
  10
  11 /* MCG_CAP register defines */
  12 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  13 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  14 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  15 #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  16 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  17 #define MCG_EXT_CNT_SHIFT       16
  18 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  19 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  20 #define MCG_ELOG_P              (1ULL<<26)   /* Extended error log supported */
  21 #define MCG_LMCE_P              (1ULL<<27)   /* Local machine check supported */
  22
  23 /* MCG_STATUS register defines */
  24 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  25 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  26 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  27 #define MCG_STATUS_LMCES (1ULL<<3)   /* LMCE signaled */
  28
  29 /* MCG_EXT_CTL register defines */
  30 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
  31
  32 /* MCi_STATUS register defines */
  33 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  34 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  35 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  36 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  37 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  38 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  39 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  40 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  41 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  42
  43 /* AMD-specific bits */
  44 #define MCI_STATUS_TCC          (1ULL<<55)  /* Task context corrupt */
  45 #define MCI_STATUS_SYNDV        (1ULL<<53)  /* synd reg. valid */
  46 #define MCI_STATUS_DEFERRED     (1ULL<<44)  /* uncorrected error, deferred exception */
  47 #define MCI_STATUS_POISON       (1ULL<<43)  /* access poisonous data */
  48
  49 /*
  50  * McaX field if set indicates a given bank supports MCA extensions:
  51  *  - Deferred error interrupt type is specifiable by bank.
  52  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
  53  *    But should not be used to determine MSR numbers.
  54  *  - TCC bit is present in MCx_STATUS.
  55  */
  56 #define MCI_CONFIG_MCAX         0x1
  57 #define MCI_IPID_MCATYPE        0xFFFF0000
  58 #define MCI_IPID_HWID           0xFFF
  59
  60 /*
  61  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
  62  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
  63  * errors to indicate that errors are being filtered by hardware.
  64  * We should mask out bit 12 when looking for specific signatures
  65  * of uncorrected errors - so the F bit is deliberately skipped
  66  * in this #define.
  67  */
  68 #define MCACOD            0xefff     /* MCA Error Code */
  69
  70 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
  71 #define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
  72 #define MCACOD_SCRUBMSK 0xeff0  /* Skip bit 12 ('F' bit) */
  73 #define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
  74 #define MCACOD_DATA     0x0134  /* Data Load */
  75 #define MCACOD_INSTR    0x0150  /* Instruction Fetch */
  76
  77 /* MCi_MISC register defines */
  78 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
  79 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
  80 #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
  81 #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
  82 #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
  83 #define  MCI_MISC_ADDR_MEM      3       /* memory address */
  84 #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
  85
  86 /* CTL2 register defines */
  87 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
  88 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  89
  90 #define MCJ_CTX_MASK            3
  91 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  92 #define MCJ_CTX_RANDOM          0    /* inject context: random */
  93 #define MCJ_CTX_PROCESS         0x1  /* inject context: process */
  94 #define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
  95 #define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
  96 #define MCJ_EXCEPTION           0x8  /* raise as exception */
  97 #define MCJ_IRQ_BROADCAST       0x10 /* do IRQ broadcasting */
  98
  99 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
 100
 101 #define MCE_LOG_LEN 32
 102 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
 103
 104 /* AMD Scalable MCA */
 105 #define MSR_AMD64_SMCA_MC0_CTL          0xc0002000
 106 #define MSR_AMD64_SMCA_MC0_STATUS       0xc0002001
 107 #define MSR_AMD64_SMCA_MC0_ADDR         0xc0002002
 108 #define MSR_AMD64_SMCA_MC0_MISC0        0xc0002003
 109 #define MSR_AMD64_SMCA_MC0_CONFIG       0xc0002004
 110 #define MSR_AMD64_SMCA_MC0_IPID         0xc0002005
 111 #define MSR_AMD64_SMCA_MC0_SYND         0xc0002006
 112 #define MSR_AMD64_SMCA_MC0_DESTAT       0xc0002008
 113 #define MSR_AMD64_SMCA_MC0_DEADDR       0xc0002009
 114 #define MSR_AMD64_SMCA_MC0_MISC1        0xc000200a
 115 #define MSR_AMD64_SMCA_MCx_CTL(x)       (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
 116 #define MSR_AMD64_SMCA_MCx_STATUS(x)    (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
 117 #define MSR_AMD64_SMCA_MCx_ADDR(x)      (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
 118 #define MSR_AMD64_SMCA_MCx_MISC(x)      (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
 119 #define MSR_AMD64_SMCA_MCx_CONFIG(x)    (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
 120 #define MSR_AMD64_SMCA_MCx_IPID(x)      (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
 121 #define MSR_AMD64_SMCA_MCx_SYND(x)      (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
 122 #define MSR_AMD64_SMCA_MCx_DESTAT(x)    (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
 123 #define MSR_AMD64_SMCA_MCx_DEADDR(x)    (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
 124 #define MSR_AMD64_SMCA_MCx_MISCy(x, y)  ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
 125
 126 /*
 127  * This structure contains all data related to the MCE log.  Also
 128  * carries a signature to make it easier to find from external
 129  * debugging tools.  Each entry is only valid when its finished flag
 130  * is set.
 131  */
 132 struct mce_log_buffer {
 133         char signature[12]; /* "MACHINECHECK" */
 134         unsigned len;       /* = MCE_LOG_LEN */
 135         unsigned next;
 136         unsigned flags;
 137         unsigned recordlen;     /* length of struct mce */
 138         struct mce entry[MCE_LOG_LEN];
 139 };
 140
 141 struct mca_config {
 142         bool dont_log_ce;
 143         bool cmci_disabled;
 144         bool lmce_disabled;
 145         bool ignore_ce;
 146         bool disabled;
 147         bool ser;
 148         bool recovery;
 149         bool bios_cmci_threshold;
 150         u8 banks;
 151         s8 bootlog;
 152         int tolerant;
 153         int monarch_timeout;
 154         int panic_timeout;
 155         u32 rip_msr;
 156 };
 157
 158 struct mce_vendor_flags {
 159         /*
 160          * Indicates that overflow conditions are not fatal, when set.
 161          */
 162         __u64 overflow_recov    : 1,
 163
 164         /*
 165          * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
 166          * Recovery. It indicates support for data poisoning in HW and deferred
 167          * error interrupts.
 168          */
 169               succor            : 1,
 170
 171         /*
 172          * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
 173          * the register space for each MCA bank and also increases number of
 174          * banks. Also, to accommodate the new banks and registers, the MCA
 175          * register space is moved to a new MSR range.
 176          */
 177               smca              : 1,
 178
 179               __reserved_0      : 61;
 180 };
 181
 182 struct mca_msr_regs {
 183         u32 (*ctl)      (int bank);
 184         u32 (*status)   (int bank);
 185         u32 (*addr)     (int bank);
 186         u32 (*misc)     (int bank);
 187 };
 188
 189 extern struct mce_vendor_flags mce_flags;
 190
 191 extern struct mca_msr_regs msr_ops;
 192
 193 enum mce_notifier_prios {
 194         MCE_PRIO_FIRST          = INT_MAX,
 195         MCE_PRIO_SRAO           = INT_MAX - 1,
 196         MCE_PRIO_EXTLOG         = INT_MAX - 2,
 197         MCE_PRIO_NFIT           = INT_MAX - 3,
 198         MCE_PRIO_EDAC           = INT_MAX - 4,
 199         MCE_PRIO_MCELOG         = 1,
 200         MCE_PRIO_LOWEST         = 0,
 201 };
 202
 203 extern void mce_register_decode_chain(struct notifier_block *nb);
 204 extern void mce_unregister_decode_chain(struct notifier_block *nb);
 205
 206 #include <linux/percpu.h>
 207 #include <linux/atomic.h>
 208
 209 extern int mce_p5_enabled;
 210
 211 #ifdef CONFIG_X86_MCE
 212 int mcheck_init(void);
 213 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 214 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
 215 void mcheck_vendor_init_severity(void);
 216 #else
 217 static inline int mcheck_init(void) { return 0; }
 218 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 219 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
 220 static inline void mcheck_vendor_init_severity(void) {}
 221 #endif
 222
 223 #ifdef CONFIG_X86_ANCIENT_MCE
 224 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 225 void winchip_mcheck_init(struct cpuinfo_x86 *c);
 226 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 227 #else
 228 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 229 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 230 static inline void enable_p5_mce(void) {}
 231 #endif
 232
 233 void mce_setup(struct mce *m);
 234 void mce_log(struct mce *m);
 235 DECLARE_PER_CPU(struct device *, mce_device);
 236
 237 /*
 238  * Maximum banks number.
 239  * This is the limit of the current register layout on
 240  * Intel CPUs.
 241  */
 242 #define MAX_NR_BANKS 32
 243
 244 #ifdef CONFIG_X86_MCE_INTEL
 245 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 246 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
 247 void cmci_clear(void);
 248 void cmci_reenable(void);
 249 void cmci_rediscover(void);
 250 void cmci_recheck(void);
 251 #else
 252 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 253 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
 254 static inline void cmci_clear(void) {}
 255 static inline void cmci_reenable(void) {}
 256 static inline void cmci_rediscover(void) {}
 257 static inline void cmci_recheck(void) {}
 258 #endif
 259
 260 #ifdef CONFIG_X86_MCE_AMD
 261 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 262 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
 263 #else
 264 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 265 static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
 266 #endif
 267
 268 int mce_available(struct cpuinfo_x86 *c);
 269 bool mce_is_memory_error(struct mce *m);
 270
 271 DECLARE_PER_CPU(unsigned, mce_exception_count);
 272 DECLARE_PER_CPU(unsigned, mce_poll_count);
 273
 274 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 275 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 276
 277 enum mcp_flags {
 278         MCP_TIMESTAMP   = BIT(0),       /* log time stamp */
 279         MCP_UC          = BIT(1),       /* log uncorrected errors */
 280         MCP_DONTLOG     = BIT(2),       /* only clear, don't log */
 281 };
 282 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 283
 284 int mce_notify_irq(void);
 285
 286 DECLARE_PER_CPU(struct mce, injectm);
 287
 288 /* Disable CMCI/polling for MCA bank claimed by firmware */
 289 extern void mce_disable_bank(int bank);
 290
 291 /*
 292  * Exception handler
 293  */
 294
 295 /* Call the installed machine check handler for this CPU setup. */
 296 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 297 void do_machine_check(struct pt_regs *, long);
 298
 299 /*
 300  * Threshold handler
 301  */
 302 extern void (*mce_threshold_vector)(void);
 303
 304 /* Deferred error interrupt handler */
 305 extern void (*deferred_error_int_vector)(void);
 306
 307 /*
 308  * Thermal handler
 309  */
 310
 311 void intel_init_thermal(struct cpuinfo_x86 *c);
 312
 313 /* Interrupt Handler for core thermal thresholds */
 314 extern int (*platform_thermal_notify)(__u64 msr_val);
 315
 316 /* Interrupt Handler for package thermal thresholds */
 317 extern int (*platform_thermal_package_notify)(__u64 msr_val);
 318
 319 /* Callback support of rate control, return true, if
 320  * callback has rate control */
 321 extern bool (*platform_thermal_package_rate_control)(void);
 322
 323 #ifdef CONFIG_X86_THERMAL_VECTOR
 324 extern void mcheck_intel_therm_init(void);
 325 #else
 326 static inline void mcheck_intel_therm_init(void) { }
 327 #endif
 328
 329 /*
 330  * Used by APEI to report memory error via /dev/mcelog
 331  */
 332
 333 struct cper_sec_mem_err;
 334 extern void apei_mce_report_mem_error(int corrected,
 335                                       struct cper_sec_mem_err *mem_err);
 336
 337 /*
 338  * Enumerate new IP types and HWID values in AMD processors which support
 339  * Scalable MCA.
 340  */
 341 #ifdef CONFIG_X86_MCE_AMD
 342
 343 /* These may be used by multiple smca_hwid_mcatypes */
 344 enum smca_bank_types {
 345         SMCA_LS = 0,    /* Load Store */
 346         SMCA_IF,        /* Instruction Fetch */
 347         SMCA_L2_CACHE,  /* L2 Cache */
 348         SMCA_DE,        /* Decoder Unit */
 349         SMCA_EX,        /* Execution Unit */
 350         SMCA_FP,        /* Floating Point */
 351         SMCA_L3_CACHE,  /* L3 Cache */
 352         SMCA_CS,        /* Coherent Slave */
 353         SMCA_PIE,       /* Power, Interrupts, etc. */
 354         SMCA_UMC,       /* Unified Memory Controller */
 355         SMCA_PB,        /* Parameter Block */
 356         SMCA_PSP,       /* Platform Security Processor */
 357         SMCA_SMU,       /* System Management Unit */
 358         N_SMCA_BANK_TYPES
 359 };
 360
 361 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
 362
 363 struct smca_hwid {
 364         unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
 365         u32 hwid_mcatype;       /* (hwid,mcatype) tuple */
 366         u32 xec_bitmap;         /* Bitmap of valid ExtErrorCodes; current max is 21. */
 367         u8 count;               /* Number of instances. */
 368 };
 369
 370 struct smca_bank {
 371         struct smca_hwid *hwid;
 372         u32 id;                 /* Value of MCA_IPID[InstanceId]. */
 373         u8 sysfs_id;            /* Value used for sysfs name. */
 374 };
 375
 376 extern struct smca_bank smca_banks[MAX_NR_BANKS];
 377
 378 extern const char *smca_get_long_name(enum smca_bank_types t);
 379 extern bool amd_mce_is_memory_error(struct mce *m);
 380
 381 extern int mce_threshold_create_device(unsigned int cpu);
 382 extern int mce_threshold_remove_device(unsigned int cpu);
 383
 384 #else
 385
 386 static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
 387 static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
 388 static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
 389
 390 #endif
 391
 392 #endif /* _ASM_X86_MCE_H */