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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / ata / ahci.c
blob355a95a83a3405abd73a4b5d4ded9df48e8f0e38
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
51 #include "ahci.h"
52
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
55
56 enum {
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
62 };
63
64 enum board_ids {
65 /* board IDs by feature in alphabetical order */
66 board_ahci,
67 board_ahci_ign_iferr,
68 board_ahci_mobile,
69 board_ahci_nomsi,
70 board_ahci_noncq,
71 board_ahci_nosntf,
72 board_ahci_yes_fbs,
73
74 /* board IDs for specific chipsets in alphabetical order */
75 board_ahci_avn,
76 board_ahci_mcp65,
77 board_ahci_mcp77,
78 board_ahci_mcp89,
79 board_ahci_mv,
80 board_ahci_sb600,
81 board_ahci_sb700, /* for SB700 and SB800 */
82 board_ahci_vt8251,
83
84 /* aliases */
85 board_ahci_mcp_linux = board_ahci_mcp65,
86 board_ahci_mcp67 = board_ahci_mcp65,
87 board_ahci_mcp73 = board_ahci_mcp65,
88 board_ahci_mcp79 = board_ahci_mcp77,
89 };
90
91 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
92 static void ahci_remove_one(struct pci_dev *dev);
93 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
96 unsigned long deadline);
97 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
98 static bool is_mcp89_apple(struct pci_dev *pdev);
99 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
100 unsigned long deadline);
101 #ifdef CONFIG_PM
102 static int ahci_pci_device_runtime_suspend(struct device *dev);
103 static int ahci_pci_device_runtime_resume(struct device *dev);
104 #ifdef CONFIG_PM_SLEEP
105 static int ahci_pci_device_suspend(struct device *dev);
106 static int ahci_pci_device_resume(struct device *dev);
107 #endif
108 #endif /* CONFIG_PM */
109
110 static struct scsi_host_template ahci_sht = {
111 AHCI_SHT("ahci"),
112 };
113
114 static struct ata_port_operations ahci_vt8251_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_vt8251_hardreset,
117 };
118
119 static struct ata_port_operations ahci_p5wdh_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_p5wdh_hardreset,
122 };
123
124 static struct ata_port_operations ahci_avn_ops = {
125 .inherits = &ahci_ops,
126 .hardreset = ahci_avn_hardreset,
127 };
128
129 static const struct ata_port_info ahci_port_info[] = {
130 /* by features */
131 [board_ahci] = {
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_ign_iferr] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_mobile] = {
145 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_nomsi] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_noncq] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_nosntf] = {
166 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172 [board_ahci_yes_fbs] = {
173 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
174 .flags = AHCI_FLAG_COMMON,
175 .pio_mask = ATA_PIO4,
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &ahci_ops,
178 },
179 /* by chipsets */
180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
186 [board_ahci_mcp65] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
194 [board_ahci_mcp77] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp89] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mv] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_sb600] = {
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
224 },
225 [board_ahci_sb700] = { /* for SB700 and SB800 */
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_vt8251] = {
233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_vt8251_ops,
238 },
239 };
240
241 static const struct pci_device_id ahci_pci_tbl[] = {
242 /* Intel */
243 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
244 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
245 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
246 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
247 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
248 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
249 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
250 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
251 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
252 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
253 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
254 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
255 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
256 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
257 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
258 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
259 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
260 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
261 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
262 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
263 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
265 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
266 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
267 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
268 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
270 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
271 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
272 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
273 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
274 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
275 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
276 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
277 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
278 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
279 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
280 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
281 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
282 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
304 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
305 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
306 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
307 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
308 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
309 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
310 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
311 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
312 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
313 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
314 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
315 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
316 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
317 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
318 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
319 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
320 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
321 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
322 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
323 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
324 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
325 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
326 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
327 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
328 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
329 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
330 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
331 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
332 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
333 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
334 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
335 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
336 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
337 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
339 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
356 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
357 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
358 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
359 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
360 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
361 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
364 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
365 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
366 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
367 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
368 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
369 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
370 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
371 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
372 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
373 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
374 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
375 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
376 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
377 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
378 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
379 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
380 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
381 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
382 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
383 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
384 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
385 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
386 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
387 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
389 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
390 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
391 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
392 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
393 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
394 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
395 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
396 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
397 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
398 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
399 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
400 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
401 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
402
403 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
404 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
405 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
406 /* JMicron 362B and 362C have an AHCI function with IDE class code */
407 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
408 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
409 /* May need to update quirk_jmicron_async_suspend() for additions */
410
411 /* ATI */
412 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
413 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
414 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
415 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
416 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
417 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
418 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
419
420 /* AMD */
421 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
422 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
423 /* AMD is using RAID class only for ahci controllers */
424 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
425 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
426
427 /* VIA */
428 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
429 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
430
431 /* NVIDIA */
432 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
436 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
437 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
438 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
439 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
440 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
448 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
449 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
460 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
461 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
462 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
463 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
464 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
465 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
466 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
467 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
468 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
502 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
503 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
504 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
507 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
508 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
509 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
510 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
511 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
512 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
513 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
514 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
515 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
516
517 /* SiS */
518 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
519 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
520 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
521
522 /* ST Microelectronics */
523 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
524
525 /* Marvell */
526 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
527 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
529 .class = PCI_CLASS_STORAGE_SATA_AHCI,
530 .class_mask = 0xffffff,
531 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
532 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
533 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
534 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
535 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
536 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
538 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
540 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
542 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
544 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
545 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
546 .driver_data = board_ahci_yes_fbs },
547 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
548 .driver_data = board_ahci_yes_fbs },
549 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
550 .driver_data = board_ahci_yes_fbs },
551 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
552 .driver_data = board_ahci_yes_fbs },
553 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
554 .driver_data = board_ahci_yes_fbs },
555
556 /* Promise */
557 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
558 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
559
560 /* Asmedia */
561 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
562 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
563 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
564 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
565 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
566 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
567
568 /*
569 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
570 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
571 */
572 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
573 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
574
575 /* Enmotus */
576 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
577
578 /* Generic, PCI class code for AHCI */
579 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
580 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
581
582 { } /* terminate list */
583 };
584
585 static const struct dev_pm_ops ahci_pci_pm_ops = {
586 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
587 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
588 ahci_pci_device_runtime_resume, NULL)
589 };
590
591 static struct pci_driver ahci_pci_driver = {
592 .name = DRV_NAME,
593 .id_table = ahci_pci_tbl,
594 .probe = ahci_init_one,
595 .remove = ahci_remove_one,
596 .driver = {
597 .pm = &ahci_pci_pm_ops,
598 },
599 };
600
601 #if IS_ENABLED(CONFIG_PATA_MARVELL)
602 static int marvell_enable;
603 #else
604 static int marvell_enable = 1;
605 #endif
606 module_param(marvell_enable, int, 0644);
607 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
608
609 static int mobile_lpm_policy = CONFIG_SATA_MOBILE_LPM_POLICY;
610 module_param(mobile_lpm_policy, int, 0644);
611 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
612
613 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
614 struct ahci_host_priv *hpriv)
615 {
616 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
617 dev_info(&pdev->dev, "JMB361 has only one port\n");
618 hpriv->force_port_map = 1;
619 }
620
621 /*
622 * Temporary Marvell 6145 hack: PATA port presence
623 * is asserted through the standard AHCI port
624 * presence register, as bit 4 (counting from 0)
625 */
626 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
627 if (pdev->device == 0x6121)
628 hpriv->mask_port_map = 0x3;
629 else
630 hpriv->mask_port_map = 0xf;
631 dev_info(&pdev->dev,
632 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
633 }
634
635 ahci_save_initial_config(&pdev->dev, hpriv);
636 }
637
638 static int ahci_pci_reset_controller(struct ata_host *host)
639 {
640 struct pci_dev *pdev = to_pci_dev(host->dev);
641 int rc;
642
643 rc = ahci_reset_controller(host);
644 if (rc)
645 return rc;
646
647 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
648 struct ahci_host_priv *hpriv = host->private_data;
649 u16 tmp16;
650
651 /* configure PCS */
652 pci_read_config_word(pdev, 0x92, &tmp16);
653 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
654 tmp16 |= hpriv->port_map;
655 pci_write_config_word(pdev, 0x92, tmp16);
656 }
657 }
658
659 return 0;
660 }
661
662 static void ahci_pci_init_controller(struct ata_host *host)
663 {
664 struct ahci_host_priv *hpriv = host->private_data;
665 struct pci_dev *pdev = to_pci_dev(host->dev);
666 void __iomem *port_mmio;
667 u32 tmp;
668 int mv;
669
670 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
671 if (pdev->device == 0x6121)
672 mv = 2;
673 else
674 mv = 4;
675 port_mmio = __ahci_port_base(host, mv);
676
677 writel(0, port_mmio + PORT_IRQ_MASK);
678
679 /* clear port IRQ */
680 tmp = readl(port_mmio + PORT_IRQ_STAT);
681 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
682 if (tmp)
683 writel(tmp, port_mmio + PORT_IRQ_STAT);
684 }
685
686 ahci_init_controller(host);
687 }
688
689 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
690 unsigned long deadline)
691 {
692 struct ata_port *ap = link->ap;
693 struct ahci_host_priv *hpriv = ap->host->private_data;
694 bool online;
695 int rc;
696
697 DPRINTK("ENTER\n");
698
699 ahci_stop_engine(ap);
700
701 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
702 deadline, &online, NULL);
703
704 hpriv->start_engine(ap);
705
706 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
707
708 /* vt8251 doesn't clear BSY on signature FIS reception,
709 * request follow-up softreset.
710 */
711 return online ? -EAGAIN : rc;
712 }
713
714 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
715 unsigned long deadline)
716 {
717 struct ata_port *ap = link->ap;
718 struct ahci_port_priv *pp = ap->private_data;
719 struct ahci_host_priv *hpriv = ap->host->private_data;
720 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
721 struct ata_taskfile tf;
722 bool online;
723 int rc;
724
725 ahci_stop_engine(ap);
726
727 /* clear D2H reception area to properly wait for D2H FIS */
728 ata_tf_init(link->device, &tf);
729 tf.command = ATA_BUSY;
730 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
731
732 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
733 deadline, &online, NULL);
734
735 hpriv->start_engine(ap);
736
737 /* The pseudo configuration device on SIMG4726 attached to
738 * ASUS P5W-DH Deluxe doesn't send signature FIS after
739 * hardreset if no device is attached to the first downstream
740 * port && the pseudo device locks up on SRST w/ PMP==0. To
741 * work around this, wait for !BSY only briefly. If BSY isn't
742 * cleared, perform CLO and proceed to IDENTIFY (achieved by
743 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
744 *
745 * Wait for two seconds. Devices attached to downstream port
746 * which can't process the following IDENTIFY after this will
747 * have to be reset again. For most cases, this should
748 * suffice while making probing snappish enough.
749 */
750 if (online) {
751 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
752 ahci_check_ready);
753 if (rc)
754 ahci_kick_engine(ap);
755 }
756 return rc;
757 }
758
759 /*
760 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
761 *
762 * It has been observed with some SSDs that the timing of events in the
763 * link synchronization phase can leave the port in a state that can not
764 * be recovered by a SATA-hard-reset alone. The failing signature is
765 * SStatus.DET stuck at 1 ("Device presence detected but Phy
766 * communication not established"). It was found that unloading and
767 * reloading the driver when this problem occurs allows the drive
768 * connection to be recovered (DET advanced to 0x3). The critical
769 * component of reloading the driver is that the port state machines are
770 * reset by bouncing "port enable" in the AHCI PCS configuration
771 * register. So, reproduce that effect by bouncing a port whenever we
772 * see DET==1 after a reset.
773 */
774 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
775 unsigned long deadline)
776 {
777 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
778 struct ata_port *ap = link->ap;
779 struct ahci_port_priv *pp = ap->private_data;
780 struct ahci_host_priv *hpriv = ap->host->private_data;
781 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
782 unsigned long tmo = deadline - jiffies;
783 struct ata_taskfile tf;
784 bool online;
785 int rc, i;
786
787 DPRINTK("ENTER\n");
788
789 ahci_stop_engine(ap);
790
791 for (i = 0; i < 2; i++) {
792 u16 val;
793 u32 sstatus;
794 int port = ap->port_no;
795 struct ata_host *host = ap->host;
796 struct pci_dev *pdev = to_pci_dev(host->dev);
797
798 /* clear D2H reception area to properly wait for D2H FIS */
799 ata_tf_init(link->device, &tf);
800 tf.command = ATA_BUSY;
801 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
802
803 rc = sata_link_hardreset(link, timing, deadline, &online,
804 ahci_check_ready);
805
806 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
807 (sstatus & 0xf) != 1)
808 break;
809
810 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
811 port);
812
813 pci_read_config_word(pdev, 0x92, &val);
814 val &= ~(1 << port);
815 pci_write_config_word(pdev, 0x92, val);
816 ata_msleep(ap, 1000);
817 val |= 1 << port;
818 pci_write_config_word(pdev, 0x92, val);
819 deadline += tmo;
820 }
821
822 hpriv->start_engine(ap);
823
824 if (online)
825 *class = ahci_dev_classify(ap);
826
827 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
828 return rc;
829 }
830
831
832 #ifdef CONFIG_PM
833 static void ahci_pci_disable_interrupts(struct ata_host *host)
834 {
835 struct ahci_host_priv *hpriv = host->private_data;
836 void __iomem *mmio = hpriv->mmio;
837 u32 ctl;
838
839 /* AHCI spec rev1.1 section 8.3.3:
840 * Software must disable interrupts prior to requesting a
841 * transition of the HBA to D3 state.
842 */
843 ctl = readl(mmio + HOST_CTL);
844 ctl &= ~HOST_IRQ_EN;
845 writel(ctl, mmio + HOST_CTL);
846 readl(mmio + HOST_CTL); /* flush */
847 }
848
849 static int ahci_pci_device_runtime_suspend(struct device *dev)
850 {
851 struct pci_dev *pdev = to_pci_dev(dev);
852 struct ata_host *host = pci_get_drvdata(pdev);
853
854 ahci_pci_disable_interrupts(host);
855 return 0;
856 }
857
858 static int ahci_pci_device_runtime_resume(struct device *dev)
859 {
860 struct pci_dev *pdev = to_pci_dev(dev);
861 struct ata_host *host = pci_get_drvdata(pdev);
862 int rc;
863
864 rc = ahci_pci_reset_controller(host);
865 if (rc)
866 return rc;
867 ahci_pci_init_controller(host);
868 return 0;
869 }
870
871 #ifdef CONFIG_PM_SLEEP
872 static int ahci_pci_device_suspend(struct device *dev)
873 {
874 struct pci_dev *pdev = to_pci_dev(dev);
875 struct ata_host *host = pci_get_drvdata(pdev);
876 struct ahci_host_priv *hpriv = host->private_data;
877
878 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
879 dev_err(&pdev->dev,
880 "BIOS update required for suspend/resume\n");
881 return -EIO;
882 }
883
884 ahci_pci_disable_interrupts(host);
885 return ata_host_suspend(host, PMSG_SUSPEND);
886 }
887
888 static int ahci_pci_device_resume(struct device *dev)
889 {
890 struct pci_dev *pdev = to_pci_dev(dev);
891 struct ata_host *host = pci_get_drvdata(pdev);
892 int rc;
893
894 /* Apple BIOS helpfully mangles the registers on resume */
895 if (is_mcp89_apple(pdev))
896 ahci_mcp89_apple_enable(pdev);
897
898 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
899 rc = ahci_pci_reset_controller(host);
900 if (rc)
901 return rc;
902
903 ahci_pci_init_controller(host);
904 }
905
906 ata_host_resume(host);
907
908 return 0;
909 }
910 #endif
911
912 #endif /* CONFIG_PM */
913
914 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
915 {
916 int rc;
917
918 /*
919 * If the device fixup already set the dma_mask to some non-standard
920 * value, don't extend it here. This happens on STA2X11, for example.
921 */
922 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
923 return 0;
924
925 if (using_dac &&
926 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
927 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
928 if (rc) {
929 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
930 if (rc) {
931 dev_err(&pdev->dev,
932 "64-bit DMA enable failed\n");
933 return rc;
934 }
935 }
936 } else {
937 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
938 if (rc) {
939 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
940 return rc;
941 }
942 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
943 if (rc) {
944 dev_err(&pdev->dev,
945 "32-bit consistent DMA enable failed\n");
946 return rc;
947 }
948 }
949 return 0;
950 }
951
952 static void ahci_pci_print_info(struct ata_host *host)
953 {
954 struct pci_dev *pdev = to_pci_dev(host->dev);
955 u16 cc;
956 const char *scc_s;
957
958 pci_read_config_word(pdev, 0x0a, &cc);
959 if (cc == PCI_CLASS_STORAGE_IDE)
960 scc_s = "IDE";
961 else if (cc == PCI_CLASS_STORAGE_SATA)
962 scc_s = "SATA";
963 else if (cc == PCI_CLASS_STORAGE_RAID)
964 scc_s = "RAID";
965 else
966 scc_s = "unknown";
967
968 ahci_print_info(host, scc_s);
969 }
970
971 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
972 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
973 * support PMP and the 4726 either directly exports the device
974 * attached to the first downstream port or acts as a hardware storage
975 * controller and emulate a single ATA device (can be RAID 0/1 or some
976 * other configuration).
977 *
978 * When there's no device attached to the first downstream port of the
979 * 4726, "Config Disk" appears, which is a pseudo ATA device to
980 * configure the 4726. However, ATA emulation of the device is very
981 * lame. It doesn't send signature D2H Reg FIS after the initial
982 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
983 *
984 * The following function works around the problem by always using
985 * hardreset on the port and not depending on receiving signature FIS
986 * afterward. If signature FIS isn't received soon, ATA class is
987 * assumed without follow-up softreset.
988 */
989 static void ahci_p5wdh_workaround(struct ata_host *host)
990 {
991 static const struct dmi_system_id sysids[] = {
992 {
993 .ident = "P5W DH Deluxe",
994 .matches = {
995 DMI_MATCH(DMI_SYS_VENDOR,
996 "ASUSTEK COMPUTER INC"),
997 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
998 },
999 },
1000 { }
1001 };
1002 struct pci_dev *pdev = to_pci_dev(host->dev);
1003
1004 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1005 dmi_check_system(sysids)) {
1006 struct ata_port *ap = host->ports[1];
1007
1008 dev_info(&pdev->dev,
1009 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1010
1011 ap->ops = &ahci_p5wdh_ops;
1012 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1013 }
1014 }
1015
1016 /*
1017 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1018 * booting in BIOS compatibility mode. We restore the registers but not ID.
1019 */
1020 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1021 {
1022 u32 val;
1023
1024 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1025
1026 pci_read_config_dword(pdev, 0xf8, &val);
1027 val |= 1 << 0x1b;
1028 /* the following changes the device ID, but appears not to affect function */
1029 /* val = (val & ~0xf0000000) | 0x80000000; */
1030 pci_write_config_dword(pdev, 0xf8, val);
1031
1032 pci_read_config_dword(pdev, 0x54c, &val);
1033 val |= 1 << 0xc;
1034 pci_write_config_dword(pdev, 0x54c, val);
1035
1036 pci_read_config_dword(pdev, 0x4a4, &val);
1037 val &= 0xff;
1038 val |= 0x01060100;
1039 pci_write_config_dword(pdev, 0x4a4, val);
1040
1041 pci_read_config_dword(pdev, 0x54c, &val);
1042 val &= ~(1 << 0xc);
1043 pci_write_config_dword(pdev, 0x54c, val);
1044
1045 pci_read_config_dword(pdev, 0xf8, &val);
1046 val &= ~(1 << 0x1b);
1047 pci_write_config_dword(pdev, 0xf8, val);
1048 }
1049
1050 static bool is_mcp89_apple(struct pci_dev *pdev)
1051 {
1052 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1053 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1054 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1055 pdev->subsystem_device == 0xcb89;
1056 }
1057
1058 /* only some SB600 ahci controllers can do 64bit DMA */
1059 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1060 {
1061 static const struct dmi_system_id sysids[] = {
1062 /*
1063 * The oldest version known to be broken is 0901 and
1064 * working is 1501 which was released on 2007-10-26.
1065 * Enable 64bit DMA on 1501 and anything newer.
1066 *
1067 * Please read bko#9412 for more info.
1068 */
1069 {
1070 .ident = "ASUS M2A-VM",
1071 .matches = {
1072 DMI_MATCH(DMI_BOARD_VENDOR,
1073 "ASUSTeK Computer INC."),
1074 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1075 },
1076 .driver_data = "20071026", /* yyyymmdd */
1077 },
1078 /*
1079 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1080 * support 64bit DMA.
1081 *
1082 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1083 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1084 * This spelling mistake was fixed in BIOS version 1.5, so
1085 * 1.5 and later have the Manufacturer as
1086 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1087 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1088 *
1089 * BIOS versions earlier than 1.9 had a Board Product Name
1090 * DMI field of "MS-7376". This was changed to be
1091 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1092 * match on DMI_BOARD_NAME of "MS-7376".
1093 */
1094 {
1095 .ident = "MSI K9A2 Platinum",
1096 .matches = {
1097 DMI_MATCH(DMI_BOARD_VENDOR,
1098 "MICRO-STAR INTER"),
1099 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1100 },
1101 },
1102 /*
1103 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1104 * 64bit DMA.
1105 *
1106 * This board also had the typo mentioned above in the
1107 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1108 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1109 */
1110 {
1111 .ident = "MSI K9AGM2",
1112 .matches = {
1113 DMI_MATCH(DMI_BOARD_VENDOR,
1114 "MICRO-STAR INTER"),
1115 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1116 },
1117 },
1118 /*
1119 * All BIOS versions for the Asus M3A support 64bit DMA.
1120 * (all release versions from 0301 to 1206 were tested)
1121 */
1122 {
1123 .ident = "ASUS M3A",
1124 .matches = {
1125 DMI_MATCH(DMI_BOARD_VENDOR,
1126 "ASUSTeK Computer INC."),
1127 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1128 },
1129 },
1130 { }
1131 };
1132 const struct dmi_system_id *match;
1133 int year, month, date;
1134 char buf[9];
1135
1136 match = dmi_first_match(sysids);
1137 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1138 !match)
1139 return false;
1140
1141 if (!match->driver_data)
1142 goto enable_64bit;
1143
1144 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1145 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1146
1147 if (strcmp(buf, match->driver_data) >= 0)
1148 goto enable_64bit;
1149 else {
1150 dev_warn(&pdev->dev,
1151 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1152 match->ident);
1153 return false;
1154 }
1155
1156 enable_64bit:
1157 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1158 return true;
1159 }
1160
1161 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1162 {
1163 static const struct dmi_system_id broken_systems[] = {
1164 {
1165 .ident = "HP Compaq nx6310",
1166 .matches = {
1167 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1168 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1169 },
1170 /* PCI slot number of the controller */
1171 .driver_data = (void *)0x1FUL,
1172 },
1173 {
1174 .ident = "HP Compaq 6720s",
1175 .matches = {
1176 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1177 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1178 },
1179 /* PCI slot number of the controller */
1180 .driver_data = (void *)0x1FUL,
1181 },
1182
1183 { } /* terminate list */
1184 };
1185 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1186
1187 if (dmi) {
1188 unsigned long slot = (unsigned long)dmi->driver_data;
1189 /* apply the quirk only to on-board controllers */
1190 return slot == PCI_SLOT(pdev->devfn);
1191 }
1192
1193 return false;
1194 }
1195
1196 static bool ahci_broken_suspend(struct pci_dev *pdev)
1197 {
1198 static const struct dmi_system_id sysids[] = {
1199 /*
1200 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1201 * to the harddisk doesn't become online after
1202 * resuming from STR. Warn and fail suspend.
1203 *
1204 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1205 *
1206 * Use dates instead of versions to match as HP is
1207 * apparently recycling both product and version
1208 * strings.
1209 *
1210 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1211 */
1212 {
1213 .ident = "dv4",
1214 .matches = {
1215 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1216 DMI_MATCH(DMI_PRODUCT_NAME,
1217 "HP Pavilion dv4 Notebook PC"),
1218 },
1219 .driver_data = "20090105", /* F.30 */
1220 },
1221 {
1222 .ident = "dv5",
1223 .matches = {
1224 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1225 DMI_MATCH(DMI_PRODUCT_NAME,
1226 "HP Pavilion dv5 Notebook PC"),
1227 },
1228 .driver_data = "20090506", /* F.16 */
1229 },
1230 {
1231 .ident = "dv6",
1232 .matches = {
1233 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1234 DMI_MATCH(DMI_PRODUCT_NAME,
1235 "HP Pavilion dv6 Notebook PC"),
1236 },
1237 .driver_data = "20090423", /* F.21 */
1238 },
1239 {
1240 .ident = "HDX18",
1241 .matches = {
1242 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1243 DMI_MATCH(DMI_PRODUCT_NAME,
1244 "HP HDX18 Notebook PC"),
1245 },
1246 .driver_data = "20090430", /* F.23 */
1247 },
1248 /*
1249 * Acer eMachines G725 has the same problem. BIOS
1250 * V1.03 is known to be broken. V3.04 is known to
1251 * work. Between, there are V1.06, V2.06 and V3.03
1252 * that we don't have much idea about. For now,
1253 * blacklist anything older than V3.04.
1254 *
1255 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1256 */
1257 {
1258 .ident = "G725",
1259 .matches = {
1260 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1261 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1262 },
1263 .driver_data = "20091216", /* V3.04 */
1264 },
1265 { } /* terminate list */
1266 };
1267 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1268 int year, month, date;
1269 char buf[9];
1270
1271 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1272 return false;
1273
1274 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1275 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1276
1277 return strcmp(buf, dmi->driver_data) < 0;
1278 }
1279
1280 static bool ahci_broken_online(struct pci_dev *pdev)
1281 {
1282 #define ENCODE_BUSDEVFN(bus, slot, func) \
1283 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1284 static const struct dmi_system_id sysids[] = {
1285 /*
1286 * There are several gigabyte boards which use
1287 * SIMG5723s configured as hardware RAID. Certain
1288 * 5723 firmware revisions shipped there keep the link
1289 * online but fail to answer properly to SRST or
1290 * IDENTIFY when no device is attached downstream
1291 * causing libata to retry quite a few times leading
1292 * to excessive detection delay.
1293 *
1294 * As these firmwares respond to the second reset try
1295 * with invalid device signature, considering unknown
1296 * sig as offline works around the problem acceptably.
1297 */
1298 {
1299 .ident = "EP45-DQ6",
1300 .matches = {
1301 DMI_MATCH(DMI_BOARD_VENDOR,
1302 "Gigabyte Technology Co., Ltd."),
1303 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1304 },
1305 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1306 },
1307 {
1308 .ident = "EP45-DS5",
1309 .matches = {
1310 DMI_MATCH(DMI_BOARD_VENDOR,
1311 "Gigabyte Technology Co., Ltd."),
1312 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1313 },
1314 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1315 },
1316 { } /* terminate list */
1317 };
1318 #undef ENCODE_BUSDEVFN
1319 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1320 unsigned int val;
1321
1322 if (!dmi)
1323 return false;
1324
1325 val = (unsigned long)dmi->driver_data;
1326
1327 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1328 }
1329
1330 static bool ahci_broken_devslp(struct pci_dev *pdev)
1331 {
1332 /* device with broken DEVSLP but still showing SDS capability */
1333 static const struct pci_device_id ids[] = {
1334 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1335 {}
1336 };
1337
1338 return pci_match_id(ids, pdev);
1339 }
1340
1341 #ifdef CONFIG_ATA_ACPI
1342 static void ahci_gtf_filter_workaround(struct ata_host *host)
1343 {
1344 static const struct dmi_system_id sysids[] = {
1345 /*
1346 * Aspire 3810T issues a bunch of SATA enable commands
1347 * via _GTF including an invalid one and one which is
1348 * rejected by the device. Among the successful ones
1349 * is FPDMA non-zero offset enable which when enabled
1350 * only on the drive side leads to NCQ command
1351 * failures. Filter it out.
1352 */
1353 {
1354 .ident = "Aspire 3810T",
1355 .matches = {
1356 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1357 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1358 },
1359 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1360 },
1361 { }
1362 };
1363 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1364 unsigned int filter;
1365 int i;
1366
1367 if (!dmi)
1368 return;
1369
1370 filter = (unsigned long)dmi->driver_data;
1371 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1372 filter, dmi->ident);
1373
1374 for (i = 0; i < host->n_ports; i++) {
1375 struct ata_port *ap = host->ports[i];
1376 struct ata_link *link;
1377 struct ata_device *dev;
1378
1379 ata_for_each_link(link, ap, EDGE)
1380 ata_for_each_dev(dev, link, ALL)
1381 dev->gtf_filter |= filter;
1382 }
1383 }
1384 #else
1385 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1386 {}
1387 #endif
1388
1389 /*
1390 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1391 * as DUMMY, or detected but eventually get a "link down" and never get up
1392 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1393 * port_map may hold a value of 0x00.
1394 *
1395 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1396 * and can significantly reduce the occurrence of the problem.
1397 *
1398 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1399 */
1400 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1401 struct pci_dev *pdev)
1402 {
1403 static const struct dmi_system_id sysids[] = {
1404 {
1405 .ident = "Acer Switch Alpha 12",
1406 .matches = {
1407 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1408 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1409 },
1410 },
1411 { }
1412 };
1413
1414 if (dmi_check_system(sysids)) {
1415 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1416 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1417 hpriv->port_map = 0x7;
1418 hpriv->cap = 0xC734FF02;
1419 }
1420 }
1421 }
1422
1423 #ifdef CONFIG_ARM64
1424 /*
1425 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1426 * Workaround is to make sure all pending IRQs are served before leaving
1427 * handler.
1428 */
1429 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1430 {
1431 struct ata_host *host = dev_instance;
1432 struct ahci_host_priv *hpriv;
1433 unsigned int rc = 0;
1434 void __iomem *mmio;
1435 u32 irq_stat, irq_masked;
1436 unsigned int handled = 1;
1437
1438 VPRINTK("ENTER\n");
1439 hpriv = host->private_data;
1440 mmio = hpriv->mmio;
1441 irq_stat = readl(mmio + HOST_IRQ_STAT);
1442 if (!irq_stat)
1443 return IRQ_NONE;
1444
1445 do {
1446 irq_masked = irq_stat & hpriv->port_map;
1447 spin_lock(&host->lock);
1448 rc = ahci_handle_port_intr(host, irq_masked);
1449 if (!rc)
1450 handled = 0;
1451 writel(irq_stat, mmio + HOST_IRQ_STAT);
1452 irq_stat = readl(mmio + HOST_IRQ_STAT);
1453 spin_unlock(&host->lock);
1454 } while (irq_stat);
1455 VPRINTK("EXIT\n");
1456
1457 return IRQ_RETVAL(handled);
1458 }
1459 #endif
1460
1461 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1462 struct ahci_host_priv *hpriv)
1463 {
1464 int i, count = 0;
1465 u32 cap;
1466
1467 /*
1468 * Check if this device might have remapped nvme devices.
1469 */
1470 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1471 pci_resource_len(pdev, bar) < SZ_512K ||
1472 bar != AHCI_PCI_BAR_STANDARD ||
1473 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1474 return;
1475
1476 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1477 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1478 if ((cap & (1 << i)) == 0)
1479 continue;
1480 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1481 != PCI_CLASS_STORAGE_EXPRESS)
1482 continue;
1483
1484 /* We've found a remapped device */
1485 count++;
1486 }
1487
1488 if (!count)
1489 return;
1490
1491 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1492 dev_warn(&pdev->dev,
1493 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1494
1495 /*
1496 * Don't rely on the msi-x capability in the remap case,
1497 * share the legacy interrupt across ahci and remapped devices.
1498 */
1499 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1500 }
1501
1502 static int ahci_get_irq_vector(struct ata_host *host, int port)
1503 {
1504 return pci_irq_vector(to_pci_dev(host->dev), port);
1505 }
1506
1507 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1508 struct ahci_host_priv *hpriv)
1509 {
1510 int nvec;
1511
1512 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1513 return -ENODEV;
1514
1515 /*
1516 * If number of MSIs is less than number of ports then Sharing Last
1517 * Message mode could be enforced. In this case assume that advantage
1518 * of multipe MSIs is negated and use single MSI mode instead.
1519 */
1520 if (n_ports > 1) {
1521 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1522 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1523 if (nvec > 0) {
1524 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1525 hpriv->get_irq_vector = ahci_get_irq_vector;
1526 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1527 return nvec;
1528 }
1529
1530 /*
1531 * Fallback to single MSI mode if the controller
1532 * enforced MRSM mode.
1533 */
1534 printk(KERN_INFO
1535 "ahci: MRSM is on, fallback to single MSI\n");
1536 pci_free_irq_vectors(pdev);
1537 }
1538 }
1539
1540 /*
1541 * If the host is not capable of supporting per-port vectors, fall
1542 * back to single MSI before finally attempting single MSI-X.
1543 */
1544 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1545 if (nvec == 1)
1546 return nvec;
1547 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1548 }
1549
1550 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1551 {
1552 unsigned int board_id = ent->driver_data;
1553 struct ata_port_info pi = ahci_port_info[board_id];
1554 const struct ata_port_info *ppi[] = { &pi, NULL };
1555 struct device *dev = &pdev->dev;
1556 struct ahci_host_priv *hpriv;
1557 struct ata_host *host;
1558 int n_ports, i, rc;
1559 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1560
1561 VPRINTK("ENTER\n");
1562
1563 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1564
1565 ata_print_version_once(&pdev->dev, DRV_VERSION);
1566
1567 /* The AHCI driver can only drive the SATA ports, the PATA driver
1568 can drive them all so if both drivers are selected make sure
1569 AHCI stays out of the way */
1570 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1571 return -ENODEV;
1572
1573 /* Apple BIOS on MCP89 prevents us using AHCI */
1574 if (is_mcp89_apple(pdev))
1575 ahci_mcp89_apple_enable(pdev);
1576
1577 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1578 * At the moment, we can only use the AHCI mode. Let the users know
1579 * that for SAS drives they're out of luck.
1580 */
1581 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1582 dev_info(&pdev->dev,
1583 "PDC42819 can only drive SATA devices with this driver\n");
1584
1585 /* Some devices use non-standard BARs */
1586 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1587 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1588 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1589 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1590 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1591 if (pdev->device == 0xa01c)
1592 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1593 if (pdev->device == 0xa084)
1594 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1595 }
1596
1597 /* acquire resources */
1598 rc = pcim_enable_device(pdev);
1599 if (rc)
1600 return rc;
1601
1602 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1603 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1604 u8 map;
1605
1606 /* ICH6s share the same PCI ID for both piix and ahci
1607 * modes. Enabling ahci mode while MAP indicates
1608 * combined mode is a bad idea. Yield to ata_piix.
1609 */
1610 pci_read_config_byte(pdev, ICH_MAP, &map);
1611 if (map & 0x3) {
1612 dev_info(&pdev->dev,
1613 "controller is in combined mode, can't enable AHCI mode\n");
1614 return -ENODEV;
1615 }
1616 }
1617
1618 /* AHCI controllers often implement SFF compatible interface.
1619 * Grab all PCI BARs just in case.
1620 */
1621 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1622 if (rc == -EBUSY)
1623 pcim_pin_device(pdev);
1624 if (rc)
1625 return rc;
1626
1627 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1628 if (!hpriv)
1629 return -ENOMEM;
1630 hpriv->flags |= (unsigned long)pi.private_data;
1631
1632 /* MCP65 revision A1 and A2 can't do MSI */
1633 if (board_id == board_ahci_mcp65 &&
1634 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1635 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1636
1637 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1638 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1639 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1640
1641 /* only some SB600s can do 64bit DMA */
1642 if (ahci_sb600_enable_64bit(pdev))
1643 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1644
1645 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1646
1647 /* detect remapped nvme devices */
1648 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1649
1650 /* must set flag prior to save config in order to take effect */
1651 if (ahci_broken_devslp(pdev))
1652 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1653
1654 #ifdef CONFIG_ARM64
1655 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1656 hpriv->irq_handler = ahci_thunderx_irq_handler;
1657 #endif
1658
1659 /* save initial config */
1660 ahci_pci_save_initial_config(pdev, hpriv);
1661
1662 /* prepare host */
1663 if (hpriv->cap & HOST_CAP_NCQ) {
1664 pi.flags |= ATA_FLAG_NCQ;
1665 /*
1666 * Auto-activate optimization is supposed to be
1667 * supported on all AHCI controllers indicating NCQ
1668 * capability, but it seems to be broken on some
1669 * chipsets including NVIDIAs.
1670 */
1671 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1672 pi.flags |= ATA_FLAG_FPDMA_AA;
1673
1674 /*
1675 * All AHCI controllers should be forward-compatible
1676 * with the new auxiliary field. This code should be
1677 * conditionalized if any buggy AHCI controllers are
1678 * encountered.
1679 */
1680 pi.flags |= ATA_FLAG_FPDMA_AUX;
1681 }
1682
1683 if (hpriv->cap & HOST_CAP_PMP)
1684 pi.flags |= ATA_FLAG_PMP;
1685
1686 ahci_set_em_messages(hpriv, &pi);
1687
1688 if (ahci_broken_system_poweroff(pdev)) {
1689 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1690 dev_info(&pdev->dev,
1691 "quirky BIOS, skipping spindown on poweroff\n");
1692 }
1693
1694 if (ahci_broken_suspend(pdev)) {
1695 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1696 dev_warn(&pdev->dev,
1697 "BIOS update required for suspend/resume\n");
1698 }
1699
1700 if (ahci_broken_online(pdev)) {
1701 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1702 dev_info(&pdev->dev,
1703 "online status unreliable, applying workaround\n");
1704 }
1705
1706
1707 /* Acer SA5-271 workaround modifies private_data */
1708 acer_sa5_271_workaround(hpriv, pdev);
1709
1710 /* CAP.NP sometimes indicate the index of the last enabled
1711 * port, at other times, that of the last possible port, so
1712 * determining the maximum port number requires looking at
1713 * both CAP.NP and port_map.
1714 */
1715 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1716
1717 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1718 if (!host)
1719 return -ENOMEM;
1720 host->private_data = hpriv;
1721
1722 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1723 /* legacy intx interrupts */
1724 pci_intx(pdev, 1);
1725 }
1726 hpriv->irq = pci_irq_vector(pdev, 0);
1727
1728 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1729 host->flags |= ATA_HOST_PARALLEL_SCAN;
1730 else
1731 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1732
1733 if (pi.flags & ATA_FLAG_EM)
1734 ahci_reset_em(host);
1735
1736 for (i = 0; i < host->n_ports; i++) {
1737 struct ata_port *ap = host->ports[i];
1738
1739 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1740 ata_port_pbar_desc(ap, ahci_pci_bar,
1741 0x100 + ap->port_no * 0x80, "port");
1742
1743 /* set enclosure management message type */
1744 if (ap->flags & ATA_FLAG_EM)
1745 ap->em_message_type = hpriv->em_msg_type;
1746
1747 if ((hpriv->flags & AHCI_HFLAG_IS_MOBILE) &&
1748 mobile_lpm_policy >= ATA_LPM_UNKNOWN &&
1749 mobile_lpm_policy <= ATA_LPM_MIN_POWER)
1750 ap->target_lpm_policy = mobile_lpm_policy;
1751
1752 /* disabled/not-implemented port */
1753 if (!(hpriv->port_map & (1 << i)))
1754 ap->ops = &ata_dummy_port_ops;
1755 }
1756
1757 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1758 ahci_p5wdh_workaround(host);
1759
1760 /* apply gtf filter quirk */
1761 ahci_gtf_filter_workaround(host);
1762
1763 /* initialize adapter */
1764 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1765 if (rc)
1766 return rc;
1767
1768 rc = ahci_pci_reset_controller(host);
1769 if (rc)
1770 return rc;
1771
1772 ahci_pci_init_controller(host);
1773 ahci_pci_print_info(host);
1774
1775 pci_set_master(pdev);
1776
1777 rc = ahci_host_activate(host, &ahci_sht);
1778 if (rc)
1779 return rc;
1780
1781 pm_runtime_put_noidle(&pdev->dev);
1782 return 0;
1783 }
1784
1785 static void ahci_remove_one(struct pci_dev *pdev)
1786 {
1787 pm_runtime_get_noresume(&pdev->dev);
1788 ata_pci_remove_one(pdev);
1789 }
1790
1791 module_pci_driver(ahci_pci_driver);
1792
1793 MODULE_AUTHOR("Jeff Garzik");
1794 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1795 MODULE_LICENSE("GPL");
1796 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1797 MODULE_VERSION(DRV_VERSION);
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