drivers/crypto/cavium/cpt/cptpf.h

   1 /*
   2  * Copyright (C) 2016 Cavium, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CPTPF_H
  10 #define __CPTPF_H
  11
  12 #include "cpt_common.h"
  13
  14 #define CSR_DELAY 30
  15 #define CPT_MAX_CORE_GROUPS 8
  16 #define CPT_MAX_SE_CORES 10
  17 #define CPT_MAX_AE_CORES 6
  18 #define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES)
  19 #define CPT_MAX_VF_NUM 16
  20 #define CPT_PF_MSIX_VECTORS 3
  21 #define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a))
  22 #define CPT_UCODE_VERSION_SZ 32
  23 struct cpt_device;
  24
  25 struct microcode {
  26         u8 is_mc_valid;
  27         u8 is_ae;
  28         u8 group;
  29         u8 num_cores;
  30         u32 code_size;
  31         u64 core_mask;
  32         u8 version[CPT_UCODE_VERSION_SZ];
  33         /* Base info */
  34         dma_addr_t phys_base;
  35         void *code;
  36 };
  37
  38 struct cpt_vf_info {
  39         u8 state;
  40         u8 priority;
  41         u8 id;
  42         u32 qlen;
  43 };
  44
  45 /**
  46  * cpt device structure
  47  */
  48 struct cpt_device {
  49         u16 flags;      /* Flags to hold device status bits */
  50         u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */
  51         struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */
  52
  53         void __iomem *reg_base; /* Register start address */
  54         struct pci_dev *pdev; /* pci device handle */
  55
  56         struct microcode mcode[CPT_MAX_CORE_GROUPS];
  57         u8 next_mc_idx; /* next microcode index */
  58         u8 next_group;
  59         u8 max_se_cores;
  60         u8 max_ae_cores;
  61 };
  62
  63 void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
  64 #endif /* __CPTPF_H */