drivers/crypto/chelsio/chcr_core.h

   1 /*
   2  * This file is part of the Chelsio T6 Crypto driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  *
  34  */
  35
  36 #ifndef __CHCR_CORE_H__
  37 #define __CHCR_CORE_H__
  38
  39 #include <crypto/algapi.h>
  40 #include "t4_hw.h"
  41 #include "cxgb4.h"
  42 #include "t4_msg.h"
  43 #include "cxgb4_uld.h"
  44
  45 #define DRV_MODULE_NAME "chcr"
  46 #define DRV_VERSION "1.0.0.0"
  47
  48 #define MAX_PENDING_REQ_TO_HW 20
  49 #define CHCR_TEST_RESPONSE_TIMEOUT 1000
  50
  51 #define PAD_ERROR_BIT           1
  52 #define CHK_PAD_ERR_BIT(x)      (((x) >> PAD_ERROR_BIT) & 1)
  53
  54 #define MAC_ERROR_BIT           0
  55 #define CHK_MAC_ERR_BIT(x)      (((x) >> MAC_ERROR_BIT) & 1)
  56 #define MAX_SALT                4
  57 #define WR_MIN_LEN (sizeof(struct chcr_wr) + \
  58                     sizeof(struct cpl_rx_phys_dsgl) + \
  59                     sizeof(struct ulptx_sgl))
  60
  61 #define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)
  62
  63 struct uld_ctx;
  64
  65 struct _key_ctx {
  66         __be32 ctx_hdr;
  67         u8 salt[MAX_SALT];
  68         __be64 reserverd;
  69         unsigned char key[0];
  70 };
  71
  72 struct chcr_wr {
  73         struct fw_crypto_lookaside_wr wreq;
  74         struct ulp_txpkt ulptx;
  75         struct ulptx_idata sc_imm;
  76         struct cpl_tx_sec_pdu sec_cpl;
  77         struct _key_ctx key_ctx;
  78 };
  79
  80 struct chcr_dev {
  81         spinlock_t lock_chcr_dev;
  82         struct uld_ctx *u_ctx;
  83         unsigned char tx_channel_id;
  84         unsigned char rx_channel_id;
  85 };
  86
  87 struct uld_ctx {
  88         struct list_head entry;
  89         struct cxgb4_lld_info lldi;
  90         struct chcr_dev *dev;
  91 };
  92
  93 struct chcr_ipsec_req {
  94         struct ulp_txpkt ulptx;
  95         struct ulptx_idata sc_imm;
  96         struct cpl_tx_sec_pdu sec_cpl;
  97         struct _key_ctx key_ctx;
  98 };
  99
 100 struct chcr_ipsec_wr {
 101         struct fw_ulptx_wr wreq;
 102         struct chcr_ipsec_req req;
 103 };
 104
 105 struct ipsec_sa_entry {
 106         int hmac_ctrl;
 107         unsigned int enckey_len;
 108         unsigned int kctx_len;
 109         unsigned int authsize;
 110         __be32 key_ctx_hdr;
 111         char salt[MAX_SALT];
 112         char key[2 * AES_MAX_KEY_SIZE];
 113 };
 114
 115 /*
 116  *      sgl_len - calculates the size of an SGL of the given capacity
 117  *      @n: the number of SGL entries
 118  *      Calculates the number of flits needed for a scatter/gather list that
 119  *      can hold the given number of entries.
 120  */
 121 static inline unsigned int sgl_len(unsigned int n)
 122 {
 123         n--;
 124         return (3 * n) / 2 + (n & 1) + 2;
 125 }
 126
 127 struct uld_ctx *assign_chcr_device(void);
 128 int chcr_send_wr(struct sk_buff *skb);
 129 int start_crypto(void);
 130 int stop_crypto(void);
 131 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
 132                         const struct pkt_gl *pgl);
 133 int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev);
 134 int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
 135                      int err);
 136 int chcr_ipsec_xmit(struct sk_buff *skb, struct net_device *dev);
 137 void chcr_add_xfrmops(const struct cxgb4_lld_info *lld);
 138 #endif /* __CHCR_CORE_H__ */