?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / edac / i82975x_edac.c
blob892815eaa97b9191080fc688f6a80a2026751b50
1 /*
2 * Intel 82975X Memory Controller kernel module
3 * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
4 * (C) 2007 jetzbroadband (http://jetzbroadband.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Arvind R.
9 * Copied from i82875p_edac.c source:
10 */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_module.h"
18
19 #define EDAC_MOD_STR "i82975x_edac"
20
21 #define i82975x_printk(level, fmt, arg...) \
22 edac_printk(level, "i82975x", fmt, ##arg)
23
24 #define i82975x_mc_printk(mci, level, fmt, arg...) \
25 edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
26
27 #ifndef PCI_DEVICE_ID_INTEL_82975_0
28 #define PCI_DEVICE_ID_INTEL_82975_0 0x277c
29 #endif /* PCI_DEVICE_ID_INTEL_82975_0 */
30
31 #define I82975X_NR_DIMMS 8
32 #define I82975X_NR_CSROWS(nr_chans) (I82975X_NR_DIMMS / (nr_chans))
33
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
36 *
37 * 31:7 128 byte cache-line address
38 * 6:1 reserved
39 * 0 0: CH0; 1: CH1
40 */
41
42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
43 *
44 * 7:0 DRAM ECC Syndrome
45 */
46
47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
48 * 0h: Processor Memory Reads
49 * 1h:7h reserved
50 * More - See Page 65 of Intel DocSheet.
51 */
52
53 #define I82975X_ERRSTS 0xc8 /* Error Status Register (16b)
54 *
55 * 15:12 reserved
56 * 11 Thermal Sensor Event
57 * 10 reserved
58 * 9 non-DRAM lock error (ndlock)
59 * 8 Refresh Timeout
60 * 7:2 reserved
61 * 1 ECC UE (multibit DRAM error)
62 * 0 ECC CE (singlebit DRAM error)
63 */
64
65 /* Error Reporting is supported by 3 mechanisms:
66 1. DMI SERR generation ( ERRCMD )
67 2. SMI DMI generation ( SMICMD )
68 3. SCI DMI generation ( SCICMD )
69 NOTE: Only ONE of the three must be enabled
70 */
71 #define I82975X_ERRCMD 0xca /* Error Command (16b)
72 *
73 * 15:12 reserved
74 * 11 Thermal Sensor Event
75 * 10 reserved
76 * 9 non-DRAM lock error (ndlock)
77 * 8 Refresh Timeout
78 * 7:2 reserved
79 * 1 ECC UE (multibit DRAM error)
80 * 0 ECC CE (singlebit DRAM error)
81 */
82
83 #define I82975X_SMICMD 0xcc /* Error Command (16b)
84 *
85 * 15:2 reserved
86 * 1 ECC UE (multibit DRAM error)
87 * 0 ECC CE (singlebit DRAM error)
88 */
89
90 #define I82975X_SCICMD 0xce /* Error Command (16b)
91 *
92 * 15:2 reserved
93 * 1 ECC UE (multibit DRAM error)
94 * 0 ECC CE (singlebit DRAM error)
95 */
96
97 #define I82975X_XEAP 0xfc /* Extended Dram Error Address Pointer (8b)
98 *
99 * 7:1 reserved
100 * 0 Bit32 of the Dram Error Address
101 */
102
103 #define I82975X_MCHBAR 0x44 /*
104 *
105 * 31:14 Base Addr of 16K memory-mapped
106 * configuration space
107 * 13:1 reserverd
108 * 0 mem-mapped config space enable
109 */
110
111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
112 /* Intel 82975x memory mapped register space */
113
114 #define I82975X_DRB_SHIFT 25 /* fixed 32MiB grain */
115
116 #define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8)
117 *
118 * 7 set to 1 in highest DRB of
119 * channel if 4GB in ch.
120 * 6:2 upper boundary of rank in
121 * 32MB grains
122 * 1:0 set to 0
123 */
124 #define I82975X_DRB_CH0R0 0x100
125 #define I82975X_DRB_CH0R1 0x101
126 #define I82975X_DRB_CH0R2 0x102
127 #define I82975X_DRB_CH0R3 0x103
128 #define I82975X_DRB_CH1R0 0x180
129 #define I82975X_DRB_CH1R1 0x181
130 #define I82975X_DRB_CH1R2 0x182
131 #define I82975X_DRB_CH1R3 0x183
132
133
134 #define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8)
135 * defines the PAGE SIZE to be used
136 * for the rank
137 * 7 reserved
138 * 6:4 row attr of odd rank, i.e. 1
139 * 3 reserved
140 * 2:0 row attr of even rank, i.e. 0
141 *
142 * 000 = unpopulated
143 * 001 = reserved
144 * 010 = 4KiB
145 * 011 = 8KiB
146 * 100 = 16KiB
147 * others = reserved
148 */
149 #define I82975X_DRA_CH0R01 0x108
150 #define I82975X_DRA_CH0R23 0x109
151 #define I82975X_DRA_CH1R01 0x188
152 #define I82975X_DRA_CH1R23 0x189
153
154
155 #define I82975X_BNKARC 0x10e /* Type of device in each rank - Bank Arch (16b)
156 *
157 * 15:8 reserved
158 * 7:6 Rank 3 architecture
159 * 5:4 Rank 2 architecture
160 * 3:2 Rank 1 architecture
161 * 1:0 Rank 0 architecture
162 *
163 * 00 => 4 banks
164 * 01 => 8 banks
165 */
166 #define I82975X_C0BNKARC 0x10e
167 #define I82975X_C1BNKARC 0x18e
168
169
170
171 #define I82975X_DRC 0x120 /* DRAM Controller Mode0 (32b)
172 *
173 * 31:30 reserved
174 * 29 init complete
175 * 28:11 reserved, according to Intel
176 * 22:21 number of channels
177 * 00=1 01=2 in 82875
178 * seems to be ECC mode
179 * bits in 82975 in Asus
180 * P5W
181 * 19:18 Data Integ Mode
182 * 00=none 01=ECC in 82875
183 * 10:8 refresh mode
184 * 7 reserved
185 * 6:4 mode select
186 * 3:2 reserved
187 * 1:0 DRAM type 10=Second Revision
188 * DDR2 SDRAM
189 * 00, 01, 11 reserved
190 */
191 #define I82975X_DRC_CH0M0 0x120
192 #define I82975X_DRC_CH1M0 0x1A0
193
194
195 #define I82975X_DRC_M1 0x124 /* DRAM Controller Mode1 (32b)
196 * 31 0=Standard Address Map
197 * 1=Enhanced Address Map
198 * 30:0 reserved
199 */
200
201 #define I82975X_DRC_CH0M1 0x124
202 #define I82975X_DRC_CH1M1 0x1A4
203
204 enum i82975x_chips {
205 I82975X = 0,
206 };
207
208 struct i82975x_pvt {
209 void __iomem *mch_window;
210 };
211
212 struct i82975x_dev_info {
213 const char *ctl_name;
214 };
215
216 struct i82975x_error_info {
217 u16 errsts;
218 u32 eap;
219 u8 des;
220 u8 derrsyn;
221 u16 errsts2;
222 u8 chan; /* the channel is bit 0 of EAP */
223 u8 xeap; /* extended eap bit */
224 };
225
226 static const struct i82975x_dev_info i82975x_devs[] = {
227 [I82975X] = {
228 .ctl_name = "i82975x"
229 },
230 };
231
232 static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
233 * already registered driver
234 */
235
236 static int i82975x_registered = 1;
237
238 static void i82975x_get_error_info(struct mem_ctl_info *mci,
239 struct i82975x_error_info *info)
240 {
241 struct pci_dev *pdev;
242
243 pdev = to_pci_dev(mci->pdev);
244
245 /*
246 * This is a mess because there is no atomic way to read all the
247 * registers at once and the registers can transition from CE being
248 * overwritten by UE.
249 */
250 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
251 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
252 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
253 pci_read_config_byte(pdev, I82975X_DES, &info->des);
254 pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
255 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
256
257 pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
258
259 /*
260 * If the error is the same then we can for both reads then
261 * the first set of reads is valid. If there is a change then
262 * there is a CE no info and the second set of reads is valid
263 * and should be UE info.
264 */
265 if (!(info->errsts2 & 0x0003))
266 return;
267
268 if ((info->errsts ^ info->errsts2) & 0x0003) {
269 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
270 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
271 pci_read_config_byte(pdev, I82975X_DES, &info->des);
272 pci_read_config_byte(pdev, I82975X_DERRSYN,
273 &info->derrsyn);
274 }
275 }
276
277 static int i82975x_process_error_info(struct mem_ctl_info *mci,
278 struct i82975x_error_info *info, int handle_errors)
279 {
280 int row, chan;
281 unsigned long offst, page;
282
283 if (!(info->errsts2 & 0x0003))
284 return 0;
285
286 if (!handle_errors)
287 return 1;
288
289 if ((info->errsts ^ info->errsts2) & 0x0003) {
290 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
291 -1, -1, -1, "UE overwrote CE", "");
292 info->errsts = info->errsts2;
293 }
294
295 page = (unsigned long) info->eap;
296 page >>= 1;
297 if (info->xeap & 1)
298 page |= 0x80000000;
299 page >>= (PAGE_SHIFT - 1);
300 row = edac_mc_find_csrow_by_page(mci, page);
301
302 if (row == -1) {
303 i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n"
304 "\tXEAP=%u\n"
305 "\t EAP=0x%08x\n"
306 "\tPAGE=0x%08x\n",
307 (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
308 return 0;
309 }
310 chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1;
311 offst = info->eap
312 & ((1 << PAGE_SHIFT) -
313 (1 << mci->csrows[row]->channels[chan]->dimm->grain));
314
315 if (info->errsts & 0x0002)
316 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
317 page, offst, 0,
318 row, -1, -1,
319 "i82975x UE", "");
320 else
321 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
322 page, offst, info->derrsyn,
323 row, chan ? chan : 0, -1,
324 "i82975x CE", "");
325
326 return 1;
327 }
328
329 static void i82975x_check(struct mem_ctl_info *mci)
330 {
331 struct i82975x_error_info info;
332
333 edac_dbg(1, "MC%d\n", mci->mc_idx);
334 i82975x_get_error_info(mci, &info);
335 i82975x_process_error_info(mci, &info, 1);
336 }
337
338 /* Return 1 if dual channel mode is active. Else return 0. */
339 static int dual_channel_active(void __iomem *mch_window)
340 {
341 /*
342 * We treat interleaved-symmetric configuration as dual-channel - EAP's
343 * bit-0 giving the channel of the error location.
344 *
345 * All other configurations are treated as single channel - the EAP's
346 * bit-0 will resolve ok in symmetric area of mixed
347 * (symmetric/asymmetric) configurations
348 */
349 u8 drb[4][2];
350 int row;
351 int dualch;
352
353 for (dualch = 1, row = 0; dualch && (row < 4); row++) {
354 drb[row][0] = readb(mch_window + I82975X_DRB + row);
355 drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
356 dualch = dualch && (drb[row][0] == drb[row][1]);
357 }
358 return dualch;
359 }
360
361 static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
362 {
363 /*
364 * ECC is possible on i92975x ONLY with DEV_X8
365 */
366 return DEV_X8;
367 }
368
369 static void i82975x_init_csrows(struct mem_ctl_info *mci,
370 struct pci_dev *pdev, void __iomem *mch_window)
371 {
372 struct csrow_info *csrow;
373 unsigned long last_cumul_size;
374 u8 value;
375 u32 cumul_size, nr_pages;
376 int index, chan;
377 struct dimm_info *dimm;
378 enum dev_type dtype;
379
380 last_cumul_size = 0;
381
382 /*
383 * 82875 comment:
384 * The dram row boundary (DRB) reg values are boundary address
385 * for each DRAM row with a granularity of 32 or 64MB (single/dual
386 * channel operation). DRB regs are cumulative; therefore DRB7 will
387 * contain the total memory contained in all rows.
388 *
389 */
390
391 for (index = 0; index < mci->nr_csrows; index++) {
392 csrow = mci->csrows[index];
393
394 value = readb(mch_window + I82975X_DRB + index +
395 ((index >= 4) ? 0x80 : 0));
396 cumul_size = value;
397 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
398 /*
399 * Adjust cumul_size w.r.t number of channels
400 *
401 */
402 if (csrow->nr_channels > 1)
403 cumul_size <<= 1;
404 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
405
406 nr_pages = cumul_size - last_cumul_size;
407 if (!nr_pages)
408 continue;
409
410 /*
411 * Initialise dram labels
412 * index values:
413 * [0-7] for single-channel; i.e. csrow->nr_channels = 1
414 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2
415 */
416 dtype = i82975x_dram_type(mch_window, index);
417 for (chan = 0; chan < csrow->nr_channels; chan++) {
418 dimm = mci->csrows[index]->channels[chan]->dimm;
419
420 dimm->nr_pages = nr_pages / csrow->nr_channels;
421
422 snprintf(csrow->channels[chan]->dimm->label, EDAC_MC_LABEL_LEN, "DIMM %c%d",
423 (chan == 0) ? 'A' : 'B',
424 index);
425 dimm->grain = 1 << 7; /* 128Byte cache-line resolution */
426 dimm->dtype = i82975x_dram_type(mch_window, index);
427 dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
428 dimm->edac_mode = EDAC_SECDED; /* only supported */
429 }
430
431 csrow->first_page = last_cumul_size;
432 csrow->last_page = cumul_size - 1;
433 last_cumul_size = cumul_size;
434 }
435 }
436
437 /* #define i82975x_DEBUG_IOMEM */
438
439 #ifdef i82975x_DEBUG_IOMEM
440 static void i82975x_print_dram_timings(void __iomem *mch_window)
441 {
442 /*
443 * The register meanings are from Intel specs;
444 * (shows 13-5-5-5 for 800-DDR2)
445 * Asus P5W Bios reports 15-5-4-4
446 * What's your religion?
447 */
448 static const int caslats[4] = { 5, 4, 3, 6 };
449 u32 dtreg[2];
450
451 dtreg[0] = readl(mch_window + 0x114);
452 dtreg[1] = readl(mch_window + 0x194);
453 i82975x_printk(KERN_INFO, "DRAM Timings : Ch0 Ch1\n"
454 " RAS Active Min = %d %d\n"
455 " CAS latency = %d %d\n"
456 " RAS to CAS = %d %d\n"
457 " RAS precharge = %d %d\n",
458 (dtreg[0] >> 19 ) & 0x0f,
459 (dtreg[1] >> 19) & 0x0f,
460 caslats[(dtreg[0] >> 8) & 0x03],
461 caslats[(dtreg[1] >> 8) & 0x03],
462 ((dtreg[0] >> 4) & 0x07) + 2,
463 ((dtreg[1] >> 4) & 0x07) + 2,
464 (dtreg[0] & 0x07) + 2,
465 (dtreg[1] & 0x07) + 2
466 );
467
468 }
469 #endif
470
471 static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
472 {
473 int rc = -ENODEV;
474 struct mem_ctl_info *mci;
475 struct edac_mc_layer layers[2];
476 struct i82975x_pvt *pvt;
477 void __iomem *mch_window;
478 u32 mchbar;
479 u32 drc[2];
480 struct i82975x_error_info discard;
481 int chans;
482 #ifdef i82975x_DEBUG_IOMEM
483 u8 c0drb[4];
484 u8 c1drb[4];
485 #endif
486
487 edac_dbg(0, "\n");
488
489 pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
490 if (!(mchbar & 1)) {
491 edac_dbg(3, "failed, MCHBAR disabled!\n");
492 goto fail0;
493 }
494 mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */
495 mch_window = ioremap_nocache(mchbar, 0x1000);
496 if (!mch_window) {
497 edac_dbg(3, "error ioremapping MCHBAR!\n");
498 goto fail0;
499 }
500
501 #ifdef i82975x_DEBUG_IOMEM
502 i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
503 mchbar, mch_window);
504
505 c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
506 c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
507 c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
508 c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
509 c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
510 c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
511 c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
512 c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
513 i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
514 i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
515 i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
516 i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
517 i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
518 i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
519 i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
520 i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
521 #endif
522
523 drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
524 drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
525 #ifdef i82975x_DEBUG_IOMEM
526 i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
527 ((drc[0] >> 21) & 3) == 1 ?
528 "ECC enabled" : "ECC disabled");
529 i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
530 ((drc[1] >> 21) & 3) == 1 ?
531 "ECC enabled" : "ECC disabled");
532
533 i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
534 readw(mch_window + I82975X_C0BNKARC));
535 i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
536 readw(mch_window + I82975X_C1BNKARC));
537 i82975x_print_dram_timings(mch_window);
538 goto fail1;
539 #endif
540 if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
541 i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
542 goto fail1;
543 }
544
545 chans = dual_channel_active(mch_window) + 1;
546
547 /* assuming only one controller, index thus is 0 */
548 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
549 layers[0].size = I82975X_NR_DIMMS;
550 layers[0].is_virt_csrow = true;
551 layers[1].type = EDAC_MC_LAYER_CHANNEL;
552 layers[1].size = I82975X_NR_CSROWS(chans);
553 layers[1].is_virt_csrow = false;
554 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
555 if (!mci) {
556 rc = -ENOMEM;
557 goto fail1;
558 }
559
560 edac_dbg(3, "init mci\n");
561 mci->pdev = &pdev->dev;
562 mci->mtype_cap = MEM_FLAG_DDR2;
563 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
564 mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
565 mci->mod_name = EDAC_MOD_STR;
566 mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
567 mci->dev_name = pci_name(pdev);
568 mci->edac_check = i82975x_check;
569 mci->ctl_page_to_phys = NULL;
570 edac_dbg(3, "init pvt\n");
571 pvt = (struct i82975x_pvt *) mci->pvt_info;
572 pvt->mch_window = mch_window;
573 i82975x_init_csrows(mci, pdev, mch_window);
574 mci->scrub_mode = SCRUB_HW_SRC;
575 i82975x_get_error_info(mci, &discard); /* clear counters */
576
577 /* finalize this instance of memory controller with edac core */
578 if (edac_mc_add_mc(mci)) {
579 edac_dbg(3, "failed edac_mc_add_mc()\n");
580 goto fail2;
581 }
582
583 /* get this far and it's successful */
584 edac_dbg(3, "success\n");
585 return 0;
586
587 fail2:
588 edac_mc_free(mci);
589
590 fail1:
591 iounmap(mch_window);
592 fail0:
593 return rc;
594 }
595
596 /* returns count (>= 0), or negative on error */
597 static int i82975x_init_one(struct pci_dev *pdev,
598 const struct pci_device_id *ent)
599 {
600 int rc;
601
602 edac_dbg(0, "\n");
603
604 if (pci_enable_device(pdev) < 0)
605 return -EIO;
606
607 rc = i82975x_probe1(pdev, ent->driver_data);
608
609 if (mci_pdev == NULL)
610 mci_pdev = pci_dev_get(pdev);
611
612 return rc;
613 }
614
615 static void i82975x_remove_one(struct pci_dev *pdev)
616 {
617 struct mem_ctl_info *mci;
618 struct i82975x_pvt *pvt;
619
620 edac_dbg(0, "\n");
621
622 mci = edac_mc_del_mc(&pdev->dev);
623 if (mci == NULL)
624 return;
625
626 pvt = mci->pvt_info;
627 if (pvt->mch_window)
628 iounmap( pvt->mch_window );
629
630 edac_mc_free(mci);
631 }
632
633 static const struct pci_device_id i82975x_pci_tbl[] = {
634 {
635 PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
636 I82975X
637 },
638 {
639 0,
640 } /* 0 terminated list. */
641 };
642
643 MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
644
645 static struct pci_driver i82975x_driver = {
646 .name = EDAC_MOD_STR,
647 .probe = i82975x_init_one,
648 .remove = i82975x_remove_one,
649 .id_table = i82975x_pci_tbl,
650 };
651
652 static int __init i82975x_init(void)
653 {
654 int pci_rc;
655
656 edac_dbg(3, "\n");
657
658 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
659 opstate_init();
660
661 pci_rc = pci_register_driver(&i82975x_driver);
662 if (pci_rc < 0)
663 goto fail0;
664
665 if (mci_pdev == NULL) {
666 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
667 PCI_DEVICE_ID_INTEL_82975_0, NULL);
668
669 if (!mci_pdev) {
670 edac_dbg(0, "i82975x pci_get_device fail\n");
671 pci_rc = -ENODEV;
672 goto fail1;
673 }
674
675 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
676
677 if (pci_rc < 0) {
678 edac_dbg(0, "i82975x init fail\n");
679 pci_rc = -ENODEV;
680 goto fail1;
681 }
682 }
683
684 return 0;
685
686 fail1:
687 pci_unregister_driver(&i82975x_driver);
688
689 fail0:
690 pci_dev_put(mci_pdev);
691 return pci_rc;
692 }
693
694 static void __exit i82975x_exit(void)
695 {
696 edac_dbg(3, "\n");
697
698 pci_unregister_driver(&i82975x_driver);
699
700 if (!i82975x_registered) {
701 i82975x_remove_one(mci_pdev);
702 pci_dev_put(mci_pdev);
703 }
704 }
705
706 module_init(i82975x_init);
707 module_exit(i82975x_exit);
708
709 MODULE_LICENSE("GPL");
710 MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
711 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
712
713 module_param(edac_op_state, int, 0444);
714 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
CRIS linux kernel tree