drivers/edac/pnd2_edac.h

   1 /*
   2  * Register bitfield descriptions for Pondicherry2 memory controller.
   3  *
   4  * Copyright (c) 2016, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #ifndef _PND2_REGS_H
  17 #define _PND2_REGS_H
  18
  19 struct b_cr_touud_lo_pci {
  20         u32     lock : 1;
  21         u32     reserved_1 : 19;
  22         u32     touud : 12;
  23 };
  24
  25 #define b_cr_touud_lo_pci_port 0x4c
  26 #define b_cr_touud_lo_pci_offset 0xa8
  27 #define b_cr_touud_lo_pci_r_opcode 0x04
  28
  29 struct b_cr_touud_hi_pci {
  30         u32     touud : 7;
  31         u32     reserved_0 : 25;
  32 };
  33
  34 #define b_cr_touud_hi_pci_port 0x4c
  35 #define b_cr_touud_hi_pci_offset 0xac
  36 #define b_cr_touud_hi_pci_r_opcode 0x04
  37
  38 struct b_cr_tolud_pci {
  39         u32     lock : 1;
  40         u32     reserved_0 : 19;
  41         u32     tolud : 12;
  42 };
  43
  44 #define b_cr_tolud_pci_port 0x4c
  45 #define b_cr_tolud_pci_offset 0xbc
  46 #define b_cr_tolud_pci_r_opcode 0x04
  47
  48 struct b_cr_mchbar_lo_pci {
  49         u32 enable : 1;
  50         u32 pad_3_1 : 3;
  51         u32 pad_14_4: 11;
  52         u32 base: 17;
  53 };
  54
  55 struct b_cr_mchbar_hi_pci {
  56         u32 base : 7;
  57         u32 pad_31_7 : 25;
  58 };
  59
  60 /* Symmetric region */
  61 struct b_cr_slice_channel_hash {
  62         u64     slice_1_disabled : 1;
  63         u64     hvm_mode : 1;
  64         u64     interleave_mode : 2;
  65         u64     slice_0_mem_disabled : 1;
  66         u64     reserved_0 : 1;
  67         u64     slice_hash_mask : 14;
  68         u64     reserved_1 : 11;
  69         u64     enable_pmi_dual_data_mode : 1;
  70         u64     ch_1_disabled : 1;
  71         u64     reserved_2 : 1;
  72         u64     sym_slice0_channel_enabled : 2;
  73         u64     sym_slice1_channel_enabled : 2;
  74         u64     ch_hash_mask : 14;
  75         u64     reserved_3 : 11;
  76         u64     lock : 1;
  77 };
  78
  79 #define b_cr_slice_channel_hash_port 0x4c
  80 #define b_cr_slice_channel_hash_offset 0x4c58
  81 #define b_cr_slice_channel_hash_r_opcode 0x06
  82
  83 struct b_cr_mot_out_base_mchbar {
  84         u32     reserved_0 : 14;
  85         u32     mot_out_base : 15;
  86         u32     reserved_1 : 1;
  87         u32     tr_en : 1;
  88         u32     imr_en : 1;
  89 };
  90
  91 #define b_cr_mot_out_base_mchbar_port 0x4c
  92 #define b_cr_mot_out_base_mchbar_offset 0x6af0
  93 #define b_cr_mot_out_base_mchbar_r_opcode 0x00
  94
  95 struct b_cr_mot_out_mask_mchbar {
  96         u32     reserved_0 : 14;
  97         u32     mot_out_mask : 15;
  98         u32     reserved_1 : 1;
  99         u32     ia_iwb_en : 1;
 100         u32     gt_iwb_en : 1;
 101 };
 102
 103 #define b_cr_mot_out_mask_mchbar_port 0x4c
 104 #define b_cr_mot_out_mask_mchbar_offset 0x6af4
 105 #define b_cr_mot_out_mask_mchbar_r_opcode 0x00
 106
 107 struct b_cr_asym_mem_region0_mchbar {
 108         u32     pad : 4;
 109         u32     slice0_asym_base : 11;
 110         u32     pad_18_15 : 4;
 111         u32     slice0_asym_limit : 11;
 112         u32     slice0_asym_channel_select : 1;
 113         u32     slice0_asym_enable : 1;
 114 };
 115
 116 #define b_cr_asym_mem_region0_mchbar_port 0x4c
 117 #define b_cr_asym_mem_region0_mchbar_offset 0x6e40
 118 #define b_cr_asym_mem_region0_mchbar_r_opcode 0x00
 119
 120 struct b_cr_asym_mem_region1_mchbar {
 121         u32     pad : 4;
 122         u32     slice1_asym_base : 11;
 123         u32     pad_18_15 : 4;
 124         u32     slice1_asym_limit : 11;
 125         u32     slice1_asym_channel_select : 1;
 126         u32     slice1_asym_enable : 1;
 127 };
 128
 129 #define b_cr_asym_mem_region1_mchbar_port 0x4c
 130 #define b_cr_asym_mem_region1_mchbar_offset 0x6e44
 131 #define b_cr_asym_mem_region1_mchbar_r_opcode 0x00
 132
 133 /* Some bit fields moved in above two structs on Denverton */
 134 struct b_cr_asym_mem_region_denverton {
 135         u32     pad : 4;
 136         u32     slice_asym_base : 8;
 137         u32     pad_19_12 : 8;
 138         u32     slice_asym_limit : 8;
 139         u32     pad_28_30 : 3;
 140         u32     slice_asym_enable : 1;
 141 };
 142
 143 struct b_cr_asym_2way_mem_region_mchbar {
 144         u32     pad : 2;
 145         u32     asym_2way_intlv_mode : 2;
 146         u32     asym_2way_base : 11;
 147         u32     pad_16_15 : 2;
 148         u32     asym_2way_limit : 11;
 149         u32     pad_30_28 : 3;
 150         u32     asym_2way_interleave_enable : 1;
 151 };
 152
 153 #define b_cr_asym_2way_mem_region_mchbar_port 0x4c
 154 #define b_cr_asym_2way_mem_region_mchbar_offset 0x6e50
 155 #define b_cr_asym_2way_mem_region_mchbar_r_opcode 0x00
 156
 157 /* Apollo Lake d-unit */
 158
 159 struct d_cr_drp0 {
 160         u32     rken0 : 1;
 161         u32     rken1 : 1;
 162         u32     ddmen : 1;
 163         u32     rsvd3 : 1;
 164         u32     dwid : 2;
 165         u32     dden : 3;
 166         u32     rsvd13_9 : 5;
 167         u32     rsien : 1;
 168         u32     bahen : 1;
 169         u32     rsvd18_16 : 3;
 170         u32     caswizzle : 2;
 171         u32     eccen : 1;
 172         u32     dramtype : 3;
 173         u32     blmode : 3;
 174         u32     addrdec : 2;
 175         u32     dramdevice_pr : 2;
 176 };
 177
 178 #define d_cr_drp0_offset 0x1400
 179 #define d_cr_drp0_r_opcode 0x00
 180
 181 /* Denverton d-unit */
 182
 183 struct d_cr_dsch {
 184         u32     ch0en : 1;
 185         u32     ch1en : 1;
 186         u32     ddr4en : 1;
 187         u32     coldwake : 1;
 188         u32     newbypdis : 1;
 189         u32     chan_width : 1;
 190         u32     rsvd6_6 : 1;
 191         u32     ooodis : 1;
 192         u32     rsvd18_8 : 11;
 193         u32     ic : 1;
 194         u32     rsvd31_20 : 12;
 195 };
 196
 197 #define d_cr_dsch_port 0x16
 198 #define d_cr_dsch_offset 0x0
 199 #define d_cr_dsch_r_opcode 0x0
 200
 201 struct d_cr_ecc_ctrl {
 202         u32     eccen : 1;
 203         u32     rsvd31_1 : 31;
 204 };
 205
 206 #define d_cr_ecc_ctrl_offset 0x180
 207 #define d_cr_ecc_ctrl_r_opcode 0x0
 208
 209 struct d_cr_drp {
 210         u32     rken0 : 1;
 211         u32     rken1 : 1;
 212         u32     rken2 : 1;
 213         u32     rken3 : 1;
 214         u32     dimmdwid0 : 2;
 215         u32     dimmdden0 : 2;
 216         u32     dimmdwid1 : 2;
 217         u32     dimmdden1 : 2;
 218         u32     rsvd15_12 : 4;
 219         u32     dimmflip : 1;
 220         u32     rsvd31_17 : 15;
 221 };
 222
 223 #define d_cr_drp_offset 0x158
 224 #define d_cr_drp_r_opcode 0x0
 225
 226 struct d_cr_dmap {
 227         u32     ba0 : 5;
 228         u32     ba1 : 5;
 229         u32     bg0 : 5; /* if ddr3, ba2 = bg0 */
 230         u32     bg1 : 5; /* if ddr3, ba3 = bg1 */
 231         u32     rs0 : 5;
 232         u32     rs1 : 5;
 233         u32     rsvd : 2;
 234 };
 235
 236 #define d_cr_dmap_offset 0x174
 237 #define d_cr_dmap_r_opcode 0x0
 238
 239 struct d_cr_dmap1 {
 240         u32     ca11 : 6;
 241         u32     bxor : 1;
 242         u32     rsvd : 25;
 243 };
 244
 245 #define d_cr_dmap1_offset 0xb4
 246 #define d_cr_dmap1_r_opcode 0x0
 247
 248 struct d_cr_dmap2 {
 249         u32     row0 : 5;
 250         u32     row1 : 5;
 251         u32     row2 : 5;
 252         u32     row3 : 5;
 253         u32     row4 : 5;
 254         u32     row5 : 5;
 255         u32     rsvd : 2;
 256 };
 257
 258 #define d_cr_dmap2_offset 0x148
 259 #define d_cr_dmap2_r_opcode 0x0
 260
 261 struct d_cr_dmap3 {
 262         u32     row6 : 5;
 263         u32     row7 : 5;
 264         u32     row8 : 5;
 265         u32     row9 : 5;
 266         u32     row10 : 5;
 267         u32     row11 : 5;
 268         u32     rsvd : 2;
 269 };
 270
 271 #define d_cr_dmap3_offset 0x14c
 272 #define d_cr_dmap3_r_opcode 0x0
 273
 274 struct d_cr_dmap4 {
 275         u32     row12 : 5;
 276         u32     row13 : 5;
 277         u32     row14 : 5;
 278         u32     row15 : 5;
 279         u32     row16 : 5;
 280         u32     row17 : 5;
 281         u32     rsvd : 2;
 282 };
 283
 284 #define d_cr_dmap4_offset 0x150
 285 #define d_cr_dmap4_r_opcode 0x0
 286
 287 struct d_cr_dmap5 {
 288         u32     ca3 : 4;
 289         u32     ca4 : 4;
 290         u32     ca5 : 4;
 291         u32     ca6 : 4;
 292         u32     ca7 : 4;
 293         u32     ca8 : 4;
 294         u32     ca9 : 4;
 295         u32     rsvd : 4;
 296 };
 297
 298 #define d_cr_dmap5_offset 0x154
 299 #define d_cr_dmap5_r_opcode 0x0
 300
 301 #endif /* _PND2_REGS_H */