?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / gpio / gpio-stmpe.c
blobf8d7d1cd8488ebe0a905b15ce69870003018ac06
1 /*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
13 #include <linux/of.h>
14 #include <linux/mfd/stmpe.h>
15 #include <linux/seq_file.h>
16 #include <linux/bitops.h>
17
18 /*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22 enum { REG_RE, REG_FE, REG_IE };
23
24 enum { LSB, CSB, MSB };
25
26 #define CACHE_NR_REGS 3
27 /* No variant has more than 24 GPIOs */
28 #define CACHE_NR_BANKS (24 / 8)
29
30 struct stmpe_gpio {
31 struct gpio_chip chip;
32 struct stmpe *stmpe;
33 struct device *dev;
34 struct mutex irq_lock;
35 u32 norequest_mask;
36 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39 };
40
41 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42 {
43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
44 struct stmpe *stmpe = stmpe_gpio->stmpe;
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
46 u8 mask = BIT(offset % 8);
47 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
53 return !!(ret & mask);
54 }
55
56 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57 {
58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
59 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
61 u8 reg = stmpe->regs[which + (offset / 8)];
62 u8 mask = BIT(offset % 8);
63
64 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
72 }
73
74 static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76 {
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
80 u8 mask = BIT(offset % 8);
81 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 return !(ret & mask);
88 }
89
90 static int stmpe_gpio_direction_output(struct gpio_chip *chip,
91 unsigned offset, int val)
92 {
93 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
94 struct stmpe *stmpe = stmpe_gpio->stmpe;
95 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
96 u8 mask = BIT(offset % 8);
97
98 stmpe_gpio_set(chip, offset, val);
99
100 return stmpe_set_bits(stmpe, reg, mask, mask);
101 }
102
103 static int stmpe_gpio_direction_input(struct gpio_chip *chip,
104 unsigned offset)
105 {
106 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
107 struct stmpe *stmpe = stmpe_gpio->stmpe;
108 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
109 u8 mask = BIT(offset % 8);
110
111 return stmpe_set_bits(stmpe, reg, mask, 0);
112 }
113
114 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
115 {
116 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
117 struct stmpe *stmpe = stmpe_gpio->stmpe;
118
119 if (stmpe_gpio->norequest_mask & BIT(offset))
120 return -EINVAL;
121
122 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
123 }
124
125 static const struct gpio_chip template_chip = {
126 .label = "stmpe",
127 .owner = THIS_MODULE,
128 .get_direction = stmpe_gpio_get_direction,
129 .direction_input = stmpe_gpio_direction_input,
130 .get = stmpe_gpio_get,
131 .direction_output = stmpe_gpio_direction_output,
132 .set = stmpe_gpio_set,
133 .request = stmpe_gpio_request,
134 .can_sleep = true,
135 };
136
137 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
138 {
139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
141 int offset = d->hwirq;
142 int regoffset = offset / 8;
143 int mask = BIT(offset % 8);
144
145 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
146 return -EINVAL;
147
148 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
149 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
150 stmpe_gpio->stmpe->partnum == STMPE1600)
151 return 0;
152
153 if (type & IRQ_TYPE_EDGE_RISING)
154 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
155 else
156 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
157
158 if (type & IRQ_TYPE_EDGE_FALLING)
159 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
160 else
161 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
162
163 return 0;
164 }
165
166 static void stmpe_gpio_irq_lock(struct irq_data *d)
167 {
168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
170
171 mutex_lock(&stmpe_gpio->irq_lock);
172 }
173
174 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
175 {
176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
177 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
178 struct stmpe *stmpe = stmpe_gpio->stmpe;
179 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
180 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
181 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
182 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
183 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
184 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
185 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
186 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
187 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
188 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
189 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
190 };
191 int i, j;
192
193 /*
194 * STMPE1600: to be able to get IRQ from pins,
195 * a read must be done on GPMR register, or a write in
196 * GPSR or GPCR registers
197 */
198 if (stmpe->partnum == STMPE1600) {
199 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
200 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
201 }
202
203 for (i = 0; i < CACHE_NR_REGS; i++) {
204 /* STMPE801 and STMPE1600 don't have RE and FE registers */
205 if ((stmpe->partnum == STMPE801 ||
206 stmpe->partnum == STMPE1600) &&
207 (i != REG_IE))
208 continue;
209
210 for (j = 0; j < num_banks; j++) {
211 u8 old = stmpe_gpio->oldregs[i][j];
212 u8 new = stmpe_gpio->regs[i][j];
213
214 if (new == old)
215 continue;
216
217 stmpe_gpio->oldregs[i][j] = new;
218 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
219 }
220 }
221
222 mutex_unlock(&stmpe_gpio->irq_lock);
223 }
224
225 static void stmpe_gpio_irq_mask(struct irq_data *d)
226 {
227 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
228 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
229 int offset = d->hwirq;
230 int regoffset = offset / 8;
231 int mask = BIT(offset % 8);
232
233 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
234 }
235
236 static void stmpe_gpio_irq_unmask(struct irq_data *d)
237 {
238 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
239 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
240 int offset = d->hwirq;
241 int regoffset = offset / 8;
242 int mask = BIT(offset % 8);
243
244 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
245 }
246
247 static void stmpe_dbg_show_one(struct seq_file *s,
248 struct gpio_chip *gc,
249 unsigned offset, unsigned gpio)
250 {
251 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
252 struct stmpe *stmpe = stmpe_gpio->stmpe;
253 const char *label = gpiochip_is_requested(gc, offset);
254 bool val = !!stmpe_gpio_get(gc, offset);
255 u8 bank = offset / 8;
256 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
257 u8 mask = BIT(offset % 8);
258 int ret;
259 u8 dir;
260
261 ret = stmpe_reg_read(stmpe, dir_reg);
262 if (ret < 0)
263 return;
264 dir = !!(ret & mask);
265
266 if (dir) {
267 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
268 gpio, label ?: "(none)",
269 val ? "hi" : "lo");
270 } else {
271 u8 edge_det_reg;
272 u8 rise_reg;
273 u8 fall_reg;
274 u8 irqen_reg;
275
276 static const char * const edge_det_values[] = {
277 "edge-inactive",
278 "edge-asserted",
279 "not-supported"
280 };
281 static const char * const rise_values[] = {
282 "no-rising-edge-detection",
283 "rising-edge-detection",
284 "not-supported"
285 };
286 static const char * const fall_values[] = {
287 "no-falling-edge-detection",
288 "falling-edge-detection",
289 "not-supported"
290 };
291 #define NOT_SUPPORTED_IDX 2
292 u8 edge_det = NOT_SUPPORTED_IDX;
293 u8 rise = NOT_SUPPORTED_IDX;
294 u8 fall = NOT_SUPPORTED_IDX;
295 bool irqen;
296
297 switch (stmpe->partnum) {
298 case STMPE610:
299 case STMPE811:
300 case STMPE1601:
301 case STMPE2401:
302 case STMPE2403:
303 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
304 ret = stmpe_reg_read(stmpe, edge_det_reg);
305 if (ret < 0)
306 return;
307 edge_det = !!(ret & mask);
308 /* fall through */
309 case STMPE1801:
310 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
311 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
312
313 ret = stmpe_reg_read(stmpe, rise_reg);
314 if (ret < 0)
315 return;
316 rise = !!(ret & mask);
317 ret = stmpe_reg_read(stmpe, fall_reg);
318 if (ret < 0)
319 return;
320 fall = !!(ret & mask);
321 /* fall through */
322 case STMPE801:
323 case STMPE1600:
324 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
325 break;
326
327 default:
328 return;
329 }
330
331 ret = stmpe_reg_read(stmpe, irqen_reg);
332 if (ret < 0)
333 return;
334 irqen = !!(ret & mask);
335
336 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
337 gpio, label ?: "(none)",
338 val ? "hi" : "lo",
339 edge_det_values[edge_det],
340 irqen ? "IRQ-enabled" : "IRQ-disabled",
341 rise_values[rise],
342 fall_values[fall]);
343 }
344 }
345
346 static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
347 {
348 unsigned i;
349 unsigned gpio = gc->base;
350
351 for (i = 0; i < gc->ngpio; i++, gpio++) {
352 stmpe_dbg_show_one(s, gc, i, gpio);
353 seq_putc(s, '\n');
354 }
355 }
356
357 static struct irq_chip stmpe_gpio_irq_chip = {
358 .name = "stmpe-gpio",
359 .irq_bus_lock = stmpe_gpio_irq_lock,
360 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
361 .irq_mask = stmpe_gpio_irq_mask,
362 .irq_unmask = stmpe_gpio_irq_unmask,
363 .irq_set_type = stmpe_gpio_irq_set_type,
364 };
365
366 static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
367 {
368 struct stmpe_gpio *stmpe_gpio = dev;
369 struct stmpe *stmpe = stmpe_gpio->stmpe;
370 u8 statmsbreg;
371 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
372 u8 status[num_banks];
373 int ret;
374 int i;
375
376 /*
377 * the stmpe_block_read() call below, imposes to set statmsbreg
378 * with the register located at the lowest address. As STMPE1600
379 * variant is the only one which respect registers address's order
380 * (LSB regs located at lowest address than MSB ones) whereas all
381 * the others have a registers layout with MSB located before the
382 * LSB regs.
383 */
384 if (stmpe->partnum == STMPE1600)
385 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
386 else
387 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
388
389 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
390 if (ret < 0)
391 return IRQ_NONE;
392
393 for (i = 0; i < num_banks; i++) {
394 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
395 num_banks - i - 1;
396 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
397 unsigned int stat = status[i];
398
399 stat &= enabled;
400 if (!stat)
401 continue;
402
403 while (stat) {
404 int bit = __ffs(stat);
405 int line = bank * 8 + bit;
406 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
407 line);
408
409 handle_nested_irq(child_irq);
410 stat &= ~BIT(bit);
411 }
412
413 /*
414 * interrupt status register write has no effect on
415 * 801/1801/1600, bits are cleared when read.
416 * Edge detect register is not present on 801/1600/1801
417 */
418 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
419 stmpe->partnum != STMPE1801) {
420 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
421 stmpe_reg_write(stmpe,
422 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
423 status[i]);
424 }
425 }
426
427 return IRQ_HANDLED;
428 }
429
430 static int stmpe_gpio_probe(struct platform_device *pdev)
431 {
432 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
433 struct device_node *np = pdev->dev.of_node;
434 struct stmpe_gpio *stmpe_gpio;
435 int ret, irq;
436
437 stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
438 if (!stmpe_gpio)
439 return -ENOMEM;
440
441 mutex_init(&stmpe_gpio->irq_lock);
442
443 stmpe_gpio->dev = &pdev->dev;
444 stmpe_gpio->stmpe = stmpe;
445 stmpe_gpio->chip = template_chip;
446 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
447 stmpe_gpio->chip.parent = &pdev->dev;
448 stmpe_gpio->chip.of_node = np;
449 stmpe_gpio->chip.base = -1;
450
451 if (IS_ENABLED(CONFIG_DEBUG_FS))
452 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
453
454 of_property_read_u32(np, "st,norequest-mask",
455 &stmpe_gpio->norequest_mask);
456 if (stmpe_gpio->norequest_mask)
457 stmpe_gpio->chip.irq.need_valid_mask = true;
458
459 irq = platform_get_irq(pdev, 0);
460 if (irq < 0)
461 dev_info(&pdev->dev,
462 "device configured in no-irq mode: "
463 "irqs are not available\n");
464
465 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
466 if (ret)
467 goto out_free;
468
469 ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
470 if (ret) {
471 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
472 goto out_disable;
473 }
474
475 if (irq > 0) {
476 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
477 stmpe_gpio_irq, IRQF_ONESHOT,
478 "stmpe-gpio", stmpe_gpio);
479 if (ret) {
480 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
481 goto out_disable;
482 }
483 if (stmpe_gpio->norequest_mask) {
484 int i;
485
486 /* Forbid unused lines to be mapped as IRQs */
487 for (i = 0; i < sizeof(u32); i++)
488 if (stmpe_gpio->norequest_mask & BIT(i))
489 clear_bit(i, stmpe_gpio->chip.irq.valid_mask);
490 }
491 ret = gpiochip_irqchip_add_nested(&stmpe_gpio->chip,
492 &stmpe_gpio_irq_chip,
493 0,
494 handle_simple_irq,
495 IRQ_TYPE_NONE);
496 if (ret) {
497 dev_err(&pdev->dev,
498 "could not connect irqchip to gpiochip\n");
499 goto out_disable;
500 }
501
502 gpiochip_set_nested_irqchip(&stmpe_gpio->chip,
503 &stmpe_gpio_irq_chip,
504 irq);
505 }
506
507 platform_set_drvdata(pdev, stmpe_gpio);
508
509 return 0;
510
511 out_disable:
512 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
513 gpiochip_remove(&stmpe_gpio->chip);
514 out_free:
515 kfree(stmpe_gpio);
516 return ret;
517 }
518
519 static struct platform_driver stmpe_gpio_driver = {
520 .driver = {
521 .suppress_bind_attrs = true,
522 .name = "stmpe-gpio",
523 },
524 .probe = stmpe_gpio_probe,
525 };
526
527 static int __init stmpe_gpio_init(void)
528 {
529 return platform_driver_register(&stmpe_gpio_driver);
530 }
531 subsys_initcall(stmpe_gpio_init);
CRIS linux kernel tree