drivers/gpu/drm/radeon/radeon_mode.h

   1 /*
   2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   3  *                VA Linux Systems Inc., Fremont, California.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Original Authors:
  25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26  *
  27  * Kernel port Author: Dave Airlie
  28  */
  29
  30 #ifndef RADEON_MODE_H
  31 #define RADEON_MODE_H
  32
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drm_encoder.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_fixed.h>
  39 #include <drm/drm_crtc_helper.h>
  40 #include <linux/i2c.h>
  41 #include <linux/i2c-algo-bit.h>
  42
  43 struct radeon_bo;
  44 struct radeon_device;
  45
  46 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
  47 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
  48 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
  49 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
  50
  51 #define RADEON_MAX_HPD_PINS 7
  52 #define RADEON_MAX_CRTCS 6
  53 #define RADEON_MAX_AFMT_BLOCKS 7
  54
  55 enum radeon_rmx_type {
  56         RMX_OFF,
  57         RMX_FULL,
  58         RMX_CENTER,
  59         RMX_ASPECT
  60 };
  61
  62 enum radeon_tv_std {
  63         TV_STD_NTSC,
  64         TV_STD_PAL,
  65         TV_STD_PAL_M,
  66         TV_STD_PAL_60,
  67         TV_STD_NTSC_J,
  68         TV_STD_SCART_PAL,
  69         TV_STD_SECAM,
  70         TV_STD_PAL_CN,
  71         TV_STD_PAL_N,
  72 };
  73
  74 enum radeon_underscan_type {
  75         UNDERSCAN_OFF,
  76         UNDERSCAN_ON,
  77         UNDERSCAN_AUTO,
  78 };
  79
  80 enum radeon_hpd_id {
  81         RADEON_HPD_1 = 0,
  82         RADEON_HPD_2,
  83         RADEON_HPD_3,
  84         RADEON_HPD_4,
  85         RADEON_HPD_5,
  86         RADEON_HPD_6,
  87         RADEON_HPD_NONE = 0xff,
  88 };
  89
  90 enum radeon_output_csc {
  91         RADEON_OUTPUT_CSC_BYPASS = 0,
  92         RADEON_OUTPUT_CSC_TVRGB = 1,
  93         RADEON_OUTPUT_CSC_YCBCR601 = 2,
  94         RADEON_OUTPUT_CSC_YCBCR709 = 3,
  95 };
  96
  97 #define RADEON_MAX_I2C_BUS 16
  98
  99 /* radeon gpio-based i2c
 100  * 1. "mask" reg and bits
 101  *    grabs the gpio pins for software use
 102  *    0=not held  1=held
 103  * 2. "a" reg and bits
 104  *    output pin value
 105  *    0=low 1=high
 106  * 3. "en" reg and bits
 107  *    sets the pin direction
 108  *    0=input 1=output
 109  * 4. "y" reg and bits
 110  *    input pin value
 111  *    0=low 1=high
 112  */
 113 struct radeon_i2c_bus_rec {
 114         bool valid;
 115         /* id used by atom */
 116         uint8_t i2c_id;
 117         /* id used by atom */
 118         enum radeon_hpd_id hpd;
 119         /* can be used with hw i2c engine */
 120         bool hw_capable;
 121         /* uses multi-media i2c engine */
 122         bool mm_i2c;
 123         /* regs and bits */
 124         uint32_t mask_clk_reg;
 125         uint32_t mask_data_reg;
 126         uint32_t a_clk_reg;
 127         uint32_t a_data_reg;
 128         uint32_t en_clk_reg;
 129         uint32_t en_data_reg;
 130         uint32_t y_clk_reg;
 131         uint32_t y_data_reg;
 132         uint32_t mask_clk_mask;
 133         uint32_t mask_data_mask;
 134         uint32_t a_clk_mask;
 135         uint32_t a_data_mask;
 136         uint32_t en_clk_mask;
 137         uint32_t en_data_mask;
 138         uint32_t y_clk_mask;
 139         uint32_t y_data_mask;
 140 };
 141
 142 struct radeon_tmds_pll {
 143     uint32_t freq;
 144     uint32_t value;
 145 };
 146
 147 #define RADEON_MAX_BIOS_CONNECTOR 16
 148
 149 /* pll flags */
 150 #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
 151 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
 152 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
 153 #define RADEON_PLL_LEGACY               (1 << 3)
 154 #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
 155 #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
 156 #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
 157 #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
 158 #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
 159 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 160 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
 161 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 162 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
 163 #define RADEON_PLL_IS_LCD               (1 << 13)
 164 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
 165
 166 struct radeon_pll {
 167         /* reference frequency */
 168         uint32_t reference_freq;
 169
 170         /* fixed dividers */
 171         uint32_t reference_div;
 172         uint32_t post_div;
 173
 174         /* pll in/out limits */
 175         uint32_t pll_in_min;
 176         uint32_t pll_in_max;
 177         uint32_t pll_out_min;
 178         uint32_t pll_out_max;
 179         uint32_t lcd_pll_out_min;
 180         uint32_t lcd_pll_out_max;
 181         uint32_t best_vco;
 182
 183         /* divider limits */
 184         uint32_t min_ref_div;
 185         uint32_t max_ref_div;
 186         uint32_t min_post_div;
 187         uint32_t max_post_div;
 188         uint32_t min_feedback_div;
 189         uint32_t max_feedback_div;
 190         uint32_t min_frac_feedback_div;
 191         uint32_t max_frac_feedback_div;
 192
 193         /* flags for the current clock */
 194         uint32_t flags;
 195
 196         /* pll id */
 197         uint32_t id;
 198 };
 199
 200 struct radeon_i2c_chan {
 201         struct i2c_adapter adapter;
 202         struct drm_device *dev;
 203         struct i2c_algo_bit_data bit;
 204         struct radeon_i2c_bus_rec rec;
 205         struct drm_dp_aux aux;
 206         bool has_aux;
 207         struct mutex mutex;
 208 };
 209
 210 /* mostly for macs, but really any system without connector tables */
 211 enum radeon_connector_table {
 212         CT_NONE = 0,
 213         CT_GENERIC,
 214         CT_IBOOK,
 215         CT_POWERBOOK_EXTERNAL,
 216         CT_POWERBOOK_INTERNAL,
 217         CT_POWERBOOK_VGA,
 218         CT_MINI_EXTERNAL,
 219         CT_MINI_INTERNAL,
 220         CT_IMAC_G5_ISIGHT,
 221         CT_EMAC,
 222         CT_RN50_POWER,
 223         CT_MAC_X800,
 224         CT_MAC_G5_9600,
 225         CT_SAM440EP,
 226         CT_MAC_G4_SILVER
 227 };
 228
 229 enum radeon_dvo_chip {
 230         DVO_SIL164,
 231         DVO_SIL1178,
 232 };
 233
 234 struct radeon_fbdev;
 235
 236 struct radeon_afmt {
 237         bool enabled;
 238         int offset;
 239         bool last_buffer_filled_status;
 240         int id;
 241 };
 242
 243 struct radeon_mode_info {
 244         struct atom_context *atom_context;
 245         struct card_info *atom_card_info;
 246         enum radeon_connector_table connector_table;
 247         bool mode_config_initialized;
 248         struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
 249         struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
 250         /* DVI-I properties */
 251         struct drm_property *coherent_mode_property;
 252         /* DAC enable load detect */
 253         struct drm_property *load_detect_property;
 254         /* TV standard */
 255         struct drm_property *tv_std_property;
 256         /* legacy TMDS PLL detect */
 257         struct drm_property *tmds_pll_property;
 258         /* underscan */
 259         struct drm_property *underscan_property;
 260         struct drm_property *underscan_hborder_property;
 261         struct drm_property *underscan_vborder_property;
 262         /* audio */
 263         struct drm_property *audio_property;
 264         /* FMT dithering */
 265         struct drm_property *dither_property;
 266         /* Output CSC */
 267         struct drm_property *output_csc_property;
 268         /* hardcoded DFP edid from BIOS */
 269         struct edid *bios_hardcoded_edid;
 270         int bios_hardcoded_edid_size;
 271
 272         /* pointer to fbdev info structure */
 273         struct radeon_fbdev *rfbdev;
 274         /* firmware flags */
 275         u16 firmware_flags;
 276         /* pointer to backlight encoder */
 277         struct radeon_encoder *bl_encoder;
 278
 279         /* bitmask for active encoder frontends */
 280         uint32_t active_encoders;
 281 };
 282
 283 #define RADEON_MAX_BL_LEVEL 0xFF
 284
 285 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 286
 287 struct radeon_backlight_privdata {
 288         struct radeon_encoder *encoder;
 289         uint8_t negative;
 290 };
 291
 292 #endif
 293
 294 #define MAX_H_CODE_TIMING_LEN 32
 295 #define MAX_V_CODE_TIMING_LEN 32
 296
 297 /* need to store these as reading
 298    back code tables is excessive */
 299 struct radeon_tv_regs {
 300         uint32_t tv_uv_adr;
 301         uint32_t timing_cntl;
 302         uint32_t hrestart;
 303         uint32_t vrestart;
 304         uint32_t frestart;
 305         uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
 306         uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
 307 };
 308
 309 struct radeon_atom_ss {
 310         uint16_t percentage;
 311         uint16_t percentage_divider;
 312         uint8_t type;
 313         uint16_t step;
 314         uint8_t delay;
 315         uint8_t range;
 316         uint8_t refdiv;
 317         /* asic_ss */
 318         uint16_t rate;
 319         uint16_t amount;
 320 };
 321
 322 enum radeon_flip_status {
 323         RADEON_FLIP_NONE,
 324         RADEON_FLIP_PENDING,
 325         RADEON_FLIP_SUBMITTED
 326 };
 327
 328 struct radeon_crtc {
 329         struct drm_crtc base;
 330         int crtc_id;
 331         u16 lut_r[256], lut_g[256], lut_b[256];
 332         bool enabled;
 333         bool can_tile;
 334         bool cursor_out_of_bounds;
 335         uint32_t crtc_offset;
 336         struct drm_gem_object *cursor_bo;
 337         uint64_t cursor_addr;
 338         int cursor_x;
 339         int cursor_y;
 340         int cursor_hot_x;
 341         int cursor_hot_y;
 342         int cursor_width;
 343         int cursor_height;
 344         int max_cursor_width;
 345         int max_cursor_height;
 346         uint32_t legacy_display_base_addr;
 347         enum radeon_rmx_type rmx_type;
 348         u8 h_border;
 349         u8 v_border;
 350         fixed20_12 vsc;
 351         fixed20_12 hsc;
 352         struct drm_display_mode native_mode;
 353         int pll_id;
 354         /* page flipping */
 355         struct workqueue_struct *flip_queue;
 356         struct radeon_flip_work *flip_work;
 357         enum radeon_flip_status flip_status;
 358         /* pll sharing */
 359         struct radeon_atom_ss ss;
 360         bool ss_enabled;
 361         u32 adjusted_clock;
 362         int bpc;
 363         u32 pll_reference_div;
 364         u32 pll_post_div;
 365         u32 pll_flags;
 366         struct drm_encoder *encoder;
 367         struct drm_connector *connector;
 368         /* for dpm */
 369         u32 line_time;
 370         u32 wm_low;
 371         u32 wm_high;
 372         u32 lb_vblank_lead_lines;
 373         struct drm_display_mode hw_mode;
 374         enum radeon_output_csc output_csc;
 375 };
 376
 377 struct radeon_encoder_primary_dac {
 378         /* legacy primary dac */
 379         uint32_t ps2_pdac_adj;
 380 };
 381
 382 struct radeon_encoder_lvds {
 383         /* legacy lvds */
 384         uint16_t panel_vcc_delay;
 385         uint8_t  panel_pwr_delay;
 386         uint8_t  panel_digon_delay;
 387         uint8_t  panel_blon_delay;
 388         uint16_t panel_ref_divider;
 389         uint8_t  panel_post_divider;
 390         uint16_t panel_fb_divider;
 391         bool     use_bios_dividers;
 392         uint32_t lvds_gen_cntl;
 393         /* panel mode */
 394         struct drm_display_mode native_mode;
 395         struct backlight_device *bl_dev;
 396         int      dpms_mode;
 397         uint8_t  backlight_level;
 398 };
 399
 400 struct radeon_encoder_tv_dac {
 401         /* legacy tv dac */
 402         uint32_t ps2_tvdac_adj;
 403         uint32_t ntsc_tvdac_adj;
 404         uint32_t pal_tvdac_adj;
 405
 406         int               h_pos;
 407         int               v_pos;
 408         int               h_size;
 409         int               supported_tv_stds;
 410         bool              tv_on;
 411         enum radeon_tv_std tv_std;
 412         struct radeon_tv_regs tv;
 413 };
 414
 415 struct radeon_encoder_int_tmds {
 416         /* legacy int tmds */
 417         struct radeon_tmds_pll tmds_pll[4];
 418 };
 419
 420 struct radeon_encoder_ext_tmds {
 421         /* tmds over dvo */
 422         struct radeon_i2c_chan *i2c_bus;
 423         uint8_t slave_addr;
 424         enum radeon_dvo_chip dvo_chip;
 425 };
 426
 427 /* spread spectrum */
 428 struct radeon_encoder_atom_dig {
 429         bool linkb;
 430         /* atom dig */
 431         bool coherent_mode;
 432         int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
 433         /* atom lvds/edp */
 434         uint32_t lcd_misc;
 435         uint16_t panel_pwr_delay;
 436         uint32_t lcd_ss_id;
 437         /* panel mode */
 438         struct drm_display_mode native_mode;
 439         struct backlight_device *bl_dev;
 440         int dpms_mode;
 441         uint8_t backlight_level;
 442         int panel_mode;
 443         struct radeon_afmt *afmt;
 444         struct r600_audio_pin *pin;
 445         int active_mst_links;
 446 };
 447
 448 struct radeon_encoder_atom_dac {
 449         enum radeon_tv_std tv_std;
 450 };
 451
 452 struct radeon_encoder_mst {
 453         int crtc;
 454         struct radeon_encoder *primary;
 455         struct radeon_connector *connector;
 456         struct drm_dp_mst_port *port;
 457         int pbn;
 458         int fe;
 459         bool fe_from_be;
 460         bool enc_active;
 461 };
 462
 463 struct radeon_encoder {
 464         struct drm_encoder base;
 465         uint32_t encoder_enum;
 466         uint32_t encoder_id;
 467         uint32_t devices;
 468         uint32_t active_device;
 469         uint32_t flags;
 470         uint32_t pixel_clock;
 471         enum radeon_rmx_type rmx_type;
 472         enum radeon_underscan_type underscan_type;
 473         uint32_t underscan_hborder;
 474         uint32_t underscan_vborder;
 475         struct drm_display_mode native_mode;
 476         void *enc_priv;
 477         int audio_polling_active;
 478         bool is_ext_encoder;
 479         u16 caps;
 480         struct radeon_audio_funcs *audio;
 481         enum radeon_output_csc output_csc;
 482         bool can_mst;
 483         uint32_t offset;
 484         bool is_mst_encoder;
 485         /* front end for this mst encoder */
 486 };
 487
 488 struct radeon_connector_atom_dig {
 489         uint32_t igp_lane_info;
 490         /* displayport */
 491         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 492         u8 dp_sink_type;
 493         int dp_clock;
 494         int dp_lane_count;
 495         bool edp_on;
 496         bool is_mst;
 497 };
 498
 499 struct radeon_gpio_rec {
 500         bool valid;
 501         u8 id;
 502         u32 reg;
 503         u32 mask;
 504         u32 shift;
 505 };
 506
 507 struct radeon_hpd {
 508         enum radeon_hpd_id hpd;
 509         u8 plugged_state;
 510         struct radeon_gpio_rec gpio;
 511 };
 512
 513 struct radeon_router {
 514         u32 router_id;
 515         struct radeon_i2c_bus_rec i2c_info;
 516         u8 i2c_addr;
 517         /* i2c mux */
 518         bool ddc_valid;
 519         u8 ddc_mux_type;
 520         u8 ddc_mux_control_pin;
 521         u8 ddc_mux_state;
 522         /* clock/data mux */
 523         bool cd_valid;
 524         u8 cd_mux_type;
 525         u8 cd_mux_control_pin;
 526         u8 cd_mux_state;
 527 };
 528
 529 enum radeon_connector_audio {
 530         RADEON_AUDIO_DISABLE = 0,
 531         RADEON_AUDIO_ENABLE = 1,
 532         RADEON_AUDIO_AUTO = 2
 533 };
 534
 535 enum radeon_connector_dither {
 536         RADEON_FMT_DITHER_DISABLE = 0,
 537         RADEON_FMT_DITHER_ENABLE = 1,
 538 };
 539
 540 struct stream_attribs {
 541         uint16_t fe;
 542         uint16_t slots;
 543 };
 544
 545 struct radeon_connector {
 546         struct drm_connector base;
 547         uint32_t connector_id;
 548         uint32_t devices;
 549         struct radeon_i2c_chan *ddc_bus;
 550         /* some systems have an hdmi and vga port with a shared ddc line */
 551         bool shared_ddc;
 552         bool use_digital;
 553         /* we need to mind the EDID between detect
 554            and get modes due to analog/digital/tvencoder */
 555         struct edid *edid;
 556         void *con_priv;
 557         bool dac_load_detect;
 558         bool detected_by_load; /* if the connection status was determined by load */
 559         bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
 560         uint16_t connector_object_id;
 561         struct radeon_hpd hpd;
 562         struct radeon_router router;
 563         struct radeon_i2c_chan *router_bus;
 564         enum radeon_connector_audio audio;
 565         enum radeon_connector_dither dither;
 566         int pixelclock_for_modeset;
 567         bool is_mst_connector;
 568         struct radeon_connector *mst_port;
 569         struct drm_dp_mst_port *port;
 570         struct drm_dp_mst_topology_mgr mst_mgr;
 571
 572         struct radeon_encoder *mst_encoder;
 573         struct stream_attribs cur_stream_attribs[6];
 574         int enabled_attribs;
 575 };
 576
 577 struct radeon_framebuffer {
 578         struct drm_framebuffer base;
 579         struct drm_gem_object *obj;
 580 };
 581
 582 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
 583                                 ((em) == ATOM_ENCODER_MODE_DP_MST))
 584
 585 struct atom_clock_dividers {
 586         u32 post_div;
 587         union {
 588                 struct {
 589 #ifdef __BIG_ENDIAN
 590                         u32 reserved : 6;
 591                         u32 whole_fb_div : 12;
 592                         u32 frac_fb_div : 14;
 593 #else
 594                         u32 frac_fb_div : 14;
 595                         u32 whole_fb_div : 12;
 596                         u32 reserved : 6;
 597 #endif
 598                 };
 599                 u32 fb_div;
 600         };
 601         u32 ref_div;
 602         bool enable_post_div;
 603         bool enable_dithen;
 604         u32 vco_mode;
 605         u32 real_clock;
 606         /* added for CI */
 607         u32 post_divider;
 608         u32 flags;
 609 };
 610
 611 struct atom_mpll_param {
 612         union {
 613                 struct {
 614 #ifdef __BIG_ENDIAN
 615                         u32 reserved : 8;
 616                         u32 clkfrac : 12;
 617                         u32 clkf : 12;
 618 #else
 619                         u32 clkf : 12;
 620                         u32 clkfrac : 12;
 621                         u32 reserved : 8;
 622 #endif
 623                 };
 624                 u32 fb_div;
 625         };
 626         u32 post_div;
 627         u32 bwcntl;
 628         u32 dll_speed;
 629         u32 vco_mode;
 630         u32 yclk_sel;
 631         u32 qdr;
 632         u32 half_rate;
 633 };
 634
 635 #define MEM_TYPE_GDDR5  0x50
 636 #define MEM_TYPE_GDDR4  0x40
 637 #define MEM_TYPE_GDDR3  0x30
 638 #define MEM_TYPE_DDR2   0x20
 639 #define MEM_TYPE_GDDR1  0x10
 640 #define MEM_TYPE_DDR3   0xb0
 641 #define MEM_TYPE_MASK   0xf0
 642
 643 struct atom_memory_info {
 644         u8 mem_vendor;
 645         u8 mem_type;
 646 };
 647
 648 #define MAX_AC_TIMING_ENTRIES 16
 649
 650 struct atom_memory_clock_range_table
 651 {
 652         u8 num_entries;
 653         u8 rsv[3];
 654         u32 mclk[MAX_AC_TIMING_ENTRIES];
 655 };
 656
 657 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
 658 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
 659
 660 struct atom_mc_reg_entry {
 661         u32 mclk_max;
 662         u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
 663 };
 664
 665 struct atom_mc_register_address {
 666         u16 s1;
 667         u8 pre_reg_data;
 668 };
 669
 670 struct atom_mc_reg_table {
 671         u8 last;
 672         u8 num_entries;
 673         struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
 674         struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
 675 };
 676
 677 #define MAX_VOLTAGE_ENTRIES 32
 678
 679 struct atom_voltage_table_entry
 680 {
 681         u16 value;
 682         u32 smio_low;
 683 };
 684
 685 struct atom_voltage_table
 686 {
 687         u32 count;
 688         u32 mask_low;
 689         u32 phase_delay;
 690         struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
 691 };
 692
 693 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
 694 #define DRM_SCANOUTPOS_VALID        (1 << 0)
 695 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
 696 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
 697 #define USE_REAL_VBLANKSTART            (1 << 30)
 698 #define GET_DISTANCE_TO_VBLANKSTART     (1 << 31)
 699
 700 extern void
 701 radeon_add_atom_connector(struct drm_device *dev,
 702                           uint32_t connector_id,
 703                           uint32_t supported_device,
 704                           int connector_type,
 705                           struct radeon_i2c_bus_rec *i2c_bus,
 706                           uint32_t igp_lane_info,
 707                           uint16_t connector_object_id,
 708                           struct radeon_hpd *hpd,
 709                           struct radeon_router *router);
 710 extern void
 711 radeon_add_legacy_connector(struct drm_device *dev,
 712                             uint32_t connector_id,
 713                             uint32_t supported_device,
 714                             int connector_type,
 715                             struct radeon_i2c_bus_rec *i2c_bus,
 716                             uint16_t connector_object_id,
 717                             struct radeon_hpd *hpd);
 718 extern uint32_t
 719 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
 720                         uint8_t dac);
 721 extern void radeon_link_encoder_connector(struct drm_device *dev);
 722
 723 extern enum radeon_tv_std
 724 radeon_combios_get_tv_info(struct radeon_device *rdev);
 725 extern enum radeon_tv_std
 726 radeon_atombios_get_tv_info(struct radeon_device *rdev);
 727 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
 728                                                  u16 *vddc, u16 *vddci, u16 *mvdd);
 729
 730 extern void
 731 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
 732                                       struct drm_encoder *encoder,
 733                                       bool connected);
 734 extern void
 735 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
 736                                        struct drm_encoder *encoder,
 737                                        bool connected);
 738
 739 extern struct drm_connector *
 740 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
 741 extern struct drm_connector *
 742 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
 743 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
 744                                     u32 pixel_clock);
 745
 746 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
 747 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
 748 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
 749 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
 750
 751 extern struct edid *radeon_connector_edid(struct drm_connector *connector);
 752
 753 extern void radeon_connector_hotplug(struct drm_connector *connector);
 754 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 755                                        struct drm_display_mode *mode);
 756 extern void radeon_dp_set_link_config(struct drm_connector *connector,
 757                                       const struct drm_display_mode *mode);
 758 extern void radeon_dp_link_train(struct drm_encoder *encoder,
 759                                  struct drm_connector *connector);
 760 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
 761 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
 762 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
 763 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 764                                     struct drm_connector *connector);
 765 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 766                                          u8 power_state);
 767 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
 768 extern ssize_t
 769 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
 770
 771 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
 772 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
 773 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
 774 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
 775 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
 776                                            int action, uint8_t lane_num,
 777                                            uint8_t lane_set);
 778 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
 779                                             int action, uint8_t lane_num,
 780                                             uint8_t lane_set, int fe);
 781 extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder,
 782                                                  int fe);
 783 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
 784 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
 785 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
 786
 787 extern void radeon_i2c_init(struct radeon_device *rdev);
 788 extern void radeon_i2c_fini(struct radeon_device *rdev);
 789 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
 790 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
 791 extern void radeon_i2c_add(struct radeon_device *rdev,
 792                            struct radeon_i2c_bus_rec *rec,
 793                            const char *name);
 794 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
 795                                                  struct radeon_i2c_bus_rec *i2c_bus);
 796 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
 797                                                  struct radeon_i2c_bus_rec *rec,
 798                                                  const char *name);
 799 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
 800 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
 801                                 u8 slave_addr,
 802                                 u8 addr,
 803                                 u8 *val);
 804 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
 805                                 u8 slave_addr,
 806                                 u8 addr,
 807                                 u8 val);
 808 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
 809 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
 810 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
 811
 812 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
 813                                              struct radeon_atom_ss *ss,
 814                                              int id);
 815 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
 816                                              struct radeon_atom_ss *ss,
 817                                              int id, u32 clock);
 818 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
 819                                                           u8 id);
 820
 821 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
 822                                       uint64_t freq,
 823                                       uint32_t *dot_clock_p,
 824                                       uint32_t *fb_div_p,
 825                                       uint32_t *frac_fb_div_p,
 826                                       uint32_t *ref_div_p,
 827                                       uint32_t *post_div_p);
 828
 829 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
 830                                      u32 freq,
 831                                      u32 *dot_clock_p,
 832                                      u32 *fb_div_p,
 833                                      u32 *frac_fb_div_p,
 834                                      u32 *ref_div_p,
 835                                      u32 *post_div_p);
 836
 837 extern void radeon_setup_encoder_clones(struct drm_device *dev);
 838
 839 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
 840 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
 841 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
 842 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
 843 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
 844 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
 845 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
 846 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
 847 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
 848 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
 849 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
 850
 851 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
 852 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 853                                    struct drm_framebuffer *old_fb);
 854 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
 855                                          struct drm_framebuffer *fb,
 856                                          int x, int y,
 857                                          enum mode_set_atomic state);
 858 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
 859                                    struct drm_display_mode *mode,
 860                                    struct drm_display_mode *adjusted_mode,
 861                                    int x, int y,
 862                                    struct drm_framebuffer *old_fb);
 863 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
 864
 865 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 866                                  struct drm_framebuffer *old_fb);
 867 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 868                                        struct drm_framebuffer *fb,
 869                                        int x, int y,
 870                                        enum mode_set_atomic state);
 871 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 872                                    struct drm_framebuffer *fb,
 873                                    int x, int y, int atomic);
 874 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
 875                                    struct drm_file *file_priv,
 876                                    uint32_t handle,
 877                                    uint32_t width,
 878                                    uint32_t height,
 879                                    int32_t hot_x,
 880                                    int32_t hot_y);
 881 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
 882                                    int x, int y);
 883 extern void radeon_cursor_reset(struct drm_crtc *crtc);
 884
 885 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 886                                       unsigned int flags, int *vpos, int *hpos,
 887                                       ktime_t *stime, ktime_t *etime,
 888                                       const struct drm_display_mode *mode);
 889
 890 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
 891 extern struct edid *
 892 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
 893 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
 894 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
 895 extern struct radeon_encoder_atom_dig *
 896 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
 897 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 898                                           struct radeon_encoder_int_tmds *tmds);
 899 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
 900                                                      struct radeon_encoder_int_tmds *tmds);
 901 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
 902                                                    struct radeon_encoder_int_tmds *tmds);
 903 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
 904                                                          struct radeon_encoder_ext_tmds *tmds);
 905 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
 906                                                        struct radeon_encoder_ext_tmds *tmds);
 907 extern struct radeon_encoder_primary_dac *
 908 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
 909 extern struct radeon_encoder_tv_dac *
 910 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
 911 extern struct radeon_encoder_lvds *
 912 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
 913 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
 914 extern struct radeon_encoder_tv_dac *
 915 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
 916 extern struct radeon_encoder_primary_dac *
 917 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
 918 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
 919 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
 920 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
 921 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
 922 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
 923 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
 924 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
 925 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
 926 extern void
 927 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 928 extern void
 929 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 930 extern void
 931 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 932 extern void
 933 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 934 int radeon_framebuffer_init(struct drm_device *dev,
 935                              struct radeon_framebuffer *rfb,
 936                              const struct drm_mode_fb_cmd2 *mode_cmd,
 937                              struct drm_gem_object *obj);
 938
 939 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 940 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
 941 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
 942 void radeon_atombios_init_crtc(struct drm_device *dev,
 943                                struct radeon_crtc *radeon_crtc);
 944 void radeon_legacy_init_crtc(struct drm_device *dev,
 945                              struct radeon_crtc *radeon_crtc);
 946
 947 void radeon_get_clock_info(struct drm_device *dev);
 948
 949 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
 950 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
 951
 952 void radeon_enc_destroy(struct drm_encoder *encoder);
 953 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
 954 void radeon_combios_asic_init(struct drm_device *dev);
 955 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 956                                         const struct drm_display_mode *mode,
 957                                         struct drm_display_mode *adjusted_mode);
 958 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 959                              struct drm_display_mode *adjusted_mode);
 960 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
 961
 962 /* legacy tv */
 963 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
 964                                       uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
 965                                       uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
 966 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
 967                                   uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
 968                                   uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
 969 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
 970                                   uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
 971                                   uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
 972 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
 973                                struct drm_display_mode *mode,
 974                                struct drm_display_mode *adjusted_mode);
 975
 976 /* fmt blocks */
 977 void avivo_program_fmt(struct drm_encoder *encoder);
 978 void dce3_program_fmt(struct drm_encoder *encoder);
 979 void dce4_program_fmt(struct drm_encoder *encoder);
 980 void dce8_program_fmt(struct drm_encoder *encoder);
 981
 982 /* fbdev layer */
 983 int radeon_fbdev_init(struct radeon_device *rdev);
 984 void radeon_fbdev_fini(struct radeon_device *rdev);
 985 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
 986 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
 987
 988 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
 989
 990 void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector);
 991 void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector);
 992
 993 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
 994
 995 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
 996
 997 /* mst */
 998 int radeon_dp_mst_init(struct radeon_connector *radeon_connector);
 999 int radeon_dp_mst_probe(struct radeon_connector *radeon_connector);
1000 int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector);
1001 int radeon_mst_debugfs_init(struct radeon_device *rdev);
1002 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode);
1003
1004 void radeon_setup_mst_connector(struct drm_device *dev);
1005
1006 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
1007 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
1008 #endif