2 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
3 * (http://www.opencores.org/projects.cgi/web/i2c/overview).
5 * Peter Korsgaard <jacmet@sunsite.dk>
7 * Support for the GRLIB port of the controller by
8 * Andreas Larsson <andreas@gaisler.com>
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/errno.h>
20 #include <linux/platform_device.h>
21 #include <linux/i2c.h>
22 #include <linux/interrupt.h>
23 #include <linux/wait.h>
24 #include <linux/i2c-ocores.h>
25 #include <linux/slab.h>
27 #include <linux/log2.h>
33 wait_queue_head_t wait
;
34 struct i2c_adapter adap
;
38 int state
; /* see STATE_ */
42 void (*setreg
)(struct ocores_i2c
*i2c
, int reg
, u8 value
);
43 u8 (*getreg
)(struct ocores_i2c
*i2c
, int reg
);
47 #define OCI2C_PRELOW 0
48 #define OCI2C_PREHIGH 1
49 #define OCI2C_CONTROL 2
51 #define OCI2C_CMD 4 /* write only */
52 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
54 #define OCI2C_CTRL_IEN 0x40
55 #define OCI2C_CTRL_EN 0x80
57 #define OCI2C_CMD_START 0x91
58 #define OCI2C_CMD_STOP 0x41
59 #define OCI2C_CMD_READ 0x21
60 #define OCI2C_CMD_WRITE 0x11
61 #define OCI2C_CMD_READ_ACK 0x21
62 #define OCI2C_CMD_READ_NACK 0x29
63 #define OCI2C_CMD_IACK 0x01
65 #define OCI2C_STAT_IF 0x01
66 #define OCI2C_STAT_TIP 0x02
67 #define OCI2C_STAT_ARBLOST 0x20
68 #define OCI2C_STAT_BUSY 0x40
69 #define OCI2C_STAT_NACK 0x80
80 static void oc_setreg_8(struct ocores_i2c
*i2c
, int reg
, u8 value
)
82 iowrite8(value
, i2c
->base
+ (reg
<< i2c
->reg_shift
));
85 static void oc_setreg_16(struct ocores_i2c
*i2c
, int reg
, u8 value
)
87 iowrite16(value
, i2c
->base
+ (reg
<< i2c
->reg_shift
));
90 static void oc_setreg_32(struct ocores_i2c
*i2c
, int reg
, u8 value
)
92 iowrite32(value
, i2c
->base
+ (reg
<< i2c
->reg_shift
));
95 static void oc_setreg_16be(struct ocores_i2c
*i2c
, int reg
, u8 value
)
97 iowrite16be(value
, i2c
->base
+ (reg
<< i2c
->reg_shift
));
100 static void oc_setreg_32be(struct ocores_i2c
*i2c
, int reg
, u8 value
)
102 iowrite32be(value
, i2c
->base
+ (reg
<< i2c
->reg_shift
));
105 static inline u8
oc_getreg_8(struct ocores_i2c
*i2c
, int reg
)
107 return ioread8(i2c
->base
+ (reg
<< i2c
->reg_shift
));
110 static inline u8
oc_getreg_16(struct ocores_i2c
*i2c
, int reg
)
112 return ioread16(i2c
->base
+ (reg
<< i2c
->reg_shift
));
115 static inline u8
oc_getreg_32(struct ocores_i2c
*i2c
, int reg
)
117 return ioread32(i2c
->base
+ (reg
<< i2c
->reg_shift
));
120 static inline u8
oc_getreg_16be(struct ocores_i2c
*i2c
, int reg
)
122 return ioread16be(i2c
->base
+ (reg
<< i2c
->reg_shift
));
125 static inline u8
oc_getreg_32be(struct ocores_i2c
*i2c
, int reg
)
127 return ioread32be(i2c
->base
+ (reg
<< i2c
->reg_shift
));
130 static inline void oc_setreg(struct ocores_i2c
*i2c
, int reg
, u8 value
)
132 i2c
->setreg(i2c
, reg
, value
);
135 static inline u8
oc_getreg(struct ocores_i2c
*i2c
, int reg
)
137 return i2c
->getreg(i2c
, reg
);
140 static void ocores_process(struct ocores_i2c
*i2c
)
142 struct i2c_msg
*msg
= i2c
->msg
;
143 u8 stat
= oc_getreg(i2c
, OCI2C_STATUS
);
145 if ((i2c
->state
== STATE_DONE
) || (i2c
->state
== STATE_ERROR
)) {
146 /* stop has been sent */
147 oc_setreg(i2c
, OCI2C_CMD
, OCI2C_CMD_IACK
);
153 if (stat
& OCI2C_STAT_ARBLOST
) {
154 i2c
->state
= STATE_ERROR
;
155 oc_setreg(i2c
, OCI2C_CMD
, OCI2C_CMD_STOP
);
159 if ((i2c
->state
== STATE_START
) || (i2c
->state
== STATE_WRITE
)) {
161 (msg
->flags
& I2C_M_RD
) ? STATE_READ
: STATE_WRITE
;
163 if (stat
& OCI2C_STAT_NACK
) {
164 i2c
->state
= STATE_ERROR
;
165 oc_setreg(i2c
, OCI2C_CMD
, OCI2C_CMD_STOP
);
169 msg
->buf
[i2c
->pos
++] = oc_getreg(i2c
, OCI2C_DATA
);
172 if (i2c
->pos
== msg
->len
) {
178 if (i2c
->nmsgs
) { /* end? */
180 if (!(msg
->flags
& I2C_M_NOSTART
)) {
181 u8 addr
= i2c_8bit_addr_from_msg(msg
);
183 i2c
->state
= STATE_START
;
185 oc_setreg(i2c
, OCI2C_DATA
, addr
);
186 oc_setreg(i2c
, OCI2C_CMD
, OCI2C_CMD_START
);
189 i2c
->state
= (msg
->flags
& I2C_M_RD
)
190 ? STATE_READ
: STATE_WRITE
;
192 i2c
->state
= STATE_DONE
;
193 oc_setreg(i2c
, OCI2C_CMD
, OCI2C_CMD_STOP
);
198 if (i2c
->state
== STATE_READ
) {
199 oc_setreg(i2c
, OCI2C_CMD
, i2c
->pos
== (msg
->len
-1) ?
200 OCI2C_CMD_READ_NACK
: OCI2C_CMD_READ_ACK
);
202 oc_setreg(i2c
, OCI2C_DATA
, msg
->buf
[i2c
->pos
++]);
203 oc_setreg(i2c
, OCI2C_CMD
, OCI2C_CMD_WRITE
);
207 static irqreturn_t
ocores_isr(int irq
, void *dev_id
)
209 struct ocores_i2c
*i2c
= dev_id
;
216 static int ocores_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
218 struct ocores_i2c
*i2c
= i2c_get_adapdata(adap
);
223 i2c
->state
= STATE_START
;
225 oc_setreg(i2c
, OCI2C_DATA
,
226 (i2c
->msg
->addr
<< 1) |
227 ((i2c
->msg
->flags
& I2C_M_RD
) ? 1:0));
229 oc_setreg(i2c
, OCI2C_CMD
, OCI2C_CMD_START
);
231 if (wait_event_timeout(i2c
->wait
, (i2c
->state
== STATE_ERROR
) ||
232 (i2c
->state
== STATE_DONE
), HZ
))
233 return (i2c
->state
== STATE_DONE
) ? num
: -EIO
;
238 static int ocores_init(struct device
*dev
, struct ocores_i2c
*i2c
)
242 u8 ctrl
= oc_getreg(i2c
, OCI2C_CONTROL
);
244 /* make sure the device is disabled */
245 oc_setreg(i2c
, OCI2C_CONTROL
, ctrl
& ~(OCI2C_CTRL_EN
|OCI2C_CTRL_IEN
));
247 prescale
= (i2c
->ip_clock_khz
/ (5 * i2c
->bus_clock_khz
)) - 1;
248 prescale
= clamp(prescale
, 0, 0xffff);
250 diff
= i2c
->ip_clock_khz
/ (5 * (prescale
+ 1)) - i2c
->bus_clock_khz
;
251 if (abs(diff
) > i2c
->bus_clock_khz
/ 10) {
253 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
254 i2c
->ip_clock_khz
, i2c
->bus_clock_khz
);
258 oc_setreg(i2c
, OCI2C_PRELOW
, prescale
& 0xff);
259 oc_setreg(i2c
, OCI2C_PREHIGH
, prescale
>> 8);
261 /* Init the device */
262 oc_setreg(i2c
, OCI2C_CMD
, OCI2C_CMD_IACK
);
263 oc_setreg(i2c
, OCI2C_CONTROL
, ctrl
| OCI2C_CTRL_IEN
| OCI2C_CTRL_EN
);
269 static u32
ocores_func(struct i2c_adapter
*adap
)
271 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
274 static const struct i2c_algorithm ocores_algorithm
= {
275 .master_xfer
= ocores_xfer
,
276 .functionality
= ocores_func
,
279 static const struct i2c_adapter ocores_adapter
= {
280 .owner
= THIS_MODULE
,
281 .name
= "i2c-ocores",
282 .class = I2C_CLASS_DEPRECATED
,
283 .algo
= &ocores_algorithm
,
286 static const struct of_device_id ocores_i2c_match
[] = {
288 .compatible
= "opencores,i2c-ocores",
289 .data
= (void *)TYPE_OCORES
,
292 .compatible
= "aeroflexgaisler,i2cmst",
293 .data
= (void *)TYPE_GRLIB
,
297 MODULE_DEVICE_TABLE(of
, ocores_i2c_match
);
300 /* Read and write functions for the GRLIB port of the controller. Registers are
301 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
302 * register. The subsequent registers has their offset decreased accordingly. */
303 static u8
oc_getreg_grlib(struct ocores_i2c
*i2c
, int reg
)
307 if (reg
!= OCI2C_PRELOW
)
309 rd
= ioread32be(i2c
->base
+ (rreg
<< i2c
->reg_shift
));
310 if (reg
== OCI2C_PREHIGH
)
311 return (u8
)(rd
>> 8);
316 static void oc_setreg_grlib(struct ocores_i2c
*i2c
, int reg
, u8 value
)
320 if (reg
!= OCI2C_PRELOW
)
322 if (reg
== OCI2C_PRELOW
|| reg
== OCI2C_PREHIGH
) {
323 curr
= ioread32be(i2c
->base
+ (rreg
<< i2c
->reg_shift
));
324 if (reg
== OCI2C_PRELOW
)
325 wr
= (curr
& 0xff00) | value
;
327 wr
= (((u32
)value
) << 8) | (curr
& 0xff);
331 iowrite32be(wr
, i2c
->base
+ (rreg
<< i2c
->reg_shift
));
334 static int ocores_i2c_of_probe(struct platform_device
*pdev
,
335 struct ocores_i2c
*i2c
)
337 struct device_node
*np
= pdev
->dev
.of_node
;
338 const struct of_device_id
*match
;
341 bool clock_frequency_present
;
343 if (of_property_read_u32(np
, "reg-shift", &i2c
->reg_shift
)) {
344 /* no 'reg-shift', check for deprecated 'regstep' */
345 if (!of_property_read_u32(np
, "regstep", &val
)) {
346 if (!is_power_of_2(val
)) {
347 dev_err(&pdev
->dev
, "invalid regstep %d\n",
351 i2c
->reg_shift
= ilog2(val
);
353 "regstep property deprecated, use reg-shift\n");
357 clock_frequency_present
= !of_property_read_u32(np
, "clock-frequency",
359 i2c
->bus_clock_khz
= 100;
361 i2c
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
363 if (!IS_ERR(i2c
->clk
)) {
364 int ret
= clk_prepare_enable(i2c
->clk
);
368 "clk_prepare_enable failed: %d\n", ret
);
371 i2c
->ip_clock_khz
= clk_get_rate(i2c
->clk
) / 1000;
372 if (clock_frequency_present
)
373 i2c
->bus_clock_khz
= clock_frequency
/ 1000;
376 if (i2c
->ip_clock_khz
== 0) {
377 if (of_property_read_u32(np
, "opencores,ip-clock-frequency",
379 if (!clock_frequency_present
) {
381 "Missing required parameter 'opencores,ip-clock-frequency'\n");
382 clk_disable_unprepare(i2c
->clk
);
385 i2c
->ip_clock_khz
= clock_frequency
/ 1000;
387 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
389 i2c
->ip_clock_khz
= val
/ 1000;
390 if (clock_frequency_present
)
391 i2c
->bus_clock_khz
= clock_frequency
/ 1000;
395 of_property_read_u32(pdev
->dev
.of_node
, "reg-io-width",
398 match
= of_match_node(ocores_i2c_match
, pdev
->dev
.of_node
);
399 if (match
&& (long)match
->data
== TYPE_GRLIB
) {
400 dev_dbg(&pdev
->dev
, "GRLIB variant of i2c-ocores\n");
401 i2c
->setreg
= oc_setreg_grlib
;
402 i2c
->getreg
= oc_getreg_grlib
;
408 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV
411 static int ocores_i2c_probe(struct platform_device
*pdev
)
413 struct ocores_i2c
*i2c
;
414 struct ocores_i2c_platform_data
*pdata
;
415 struct resource
*res
;
420 irq
= platform_get_irq(pdev
, 0);
424 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(*i2c
), GFP_KERNEL
);
428 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
429 i2c
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
430 if (IS_ERR(i2c
->base
))
431 return PTR_ERR(i2c
->base
);
433 pdata
= dev_get_platdata(&pdev
->dev
);
435 i2c
->reg_shift
= pdata
->reg_shift
;
436 i2c
->reg_io_width
= pdata
->reg_io_width
;
437 i2c
->ip_clock_khz
= pdata
->clock_khz
;
438 i2c
->bus_clock_khz
= 100;
440 ret
= ocores_i2c_of_probe(pdev
, i2c
);
445 if (i2c
->reg_io_width
== 0)
446 i2c
->reg_io_width
= 1; /* Set to default value */
448 if (!i2c
->setreg
|| !i2c
->getreg
) {
449 bool be
= pdata
? pdata
->big_endian
:
450 of_device_is_big_endian(pdev
->dev
.of_node
);
452 switch (i2c
->reg_io_width
) {
454 i2c
->setreg
= oc_setreg_8
;
455 i2c
->getreg
= oc_getreg_8
;
459 i2c
->setreg
= be
? oc_setreg_16be
: oc_setreg_16
;
460 i2c
->getreg
= be
? oc_getreg_16be
: oc_getreg_16
;
464 i2c
->setreg
= be
? oc_setreg_32be
: oc_setreg_32
;
465 i2c
->getreg
= be
? oc_getreg_32be
: oc_getreg_32
;
469 dev_err(&pdev
->dev
, "Unsupported I/O width (%d)\n",
476 ret
= ocores_init(&pdev
->dev
, i2c
);
480 init_waitqueue_head(&i2c
->wait
);
481 ret
= devm_request_irq(&pdev
->dev
, irq
, ocores_isr
, 0,
484 dev_err(&pdev
->dev
, "Cannot claim IRQ\n");
488 /* hook up driver to tree */
489 platform_set_drvdata(pdev
, i2c
);
490 i2c
->adap
= ocores_adapter
;
491 i2c_set_adapdata(&i2c
->adap
, i2c
);
492 i2c
->adap
.dev
.parent
= &pdev
->dev
;
493 i2c
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
495 /* add i2c adapter to i2c tree */
496 ret
= i2c_add_adapter(&i2c
->adap
);
500 /* add in known devices to the bus */
502 for (i
= 0; i
< pdata
->num_devices
; i
++)
503 i2c_new_device(&i2c
->adap
, pdata
->devices
+ i
);
509 clk_disable_unprepare(i2c
->clk
);
513 static int ocores_i2c_remove(struct platform_device
*pdev
)
515 struct ocores_i2c
*i2c
= platform_get_drvdata(pdev
);
517 /* disable i2c logic */
518 oc_setreg(i2c
, OCI2C_CONTROL
, oc_getreg(i2c
, OCI2C_CONTROL
)
519 & ~(OCI2C_CTRL_EN
|OCI2C_CTRL_IEN
));
521 /* remove adapter & data */
522 i2c_del_adapter(&i2c
->adap
);
524 if (!IS_ERR(i2c
->clk
))
525 clk_disable_unprepare(i2c
->clk
);
530 #ifdef CONFIG_PM_SLEEP
531 static int ocores_i2c_suspend(struct device
*dev
)
533 struct ocores_i2c
*i2c
= dev_get_drvdata(dev
);
534 u8 ctrl
= oc_getreg(i2c
, OCI2C_CONTROL
);
536 /* make sure the device is disabled */
537 oc_setreg(i2c
, OCI2C_CONTROL
, ctrl
& ~(OCI2C_CTRL_EN
|OCI2C_CTRL_IEN
));
539 if (!IS_ERR(i2c
->clk
))
540 clk_disable_unprepare(i2c
->clk
);
544 static int ocores_i2c_resume(struct device
*dev
)
546 struct ocores_i2c
*i2c
= dev_get_drvdata(dev
);
548 if (!IS_ERR(i2c
->clk
)) {
550 int ret
= clk_prepare_enable(i2c
->clk
);
554 "clk_prepare_enable failed: %d\n", ret
);
557 rate
= clk_get_rate(i2c
->clk
) / 1000;
559 i2c
->ip_clock_khz
= rate
;
561 return ocores_init(dev
, i2c
);
564 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm
, ocores_i2c_suspend
, ocores_i2c_resume
);
565 #define OCORES_I2C_PM (&ocores_i2c_pm)
567 #define OCORES_I2C_PM NULL
570 static struct platform_driver ocores_i2c_driver
= {
571 .probe
= ocores_i2c_probe
,
572 .remove
= ocores_i2c_remove
,
574 .name
= "ocores-i2c",
575 .of_match_table
= ocores_i2c_match
,
580 module_platform_driver(ocores_i2c_driver
);
582 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
583 MODULE_DESCRIPTION("OpenCores I2C bus driver");
584 MODULE_LICENSE("GPL");
585 MODULE_ALIAS("platform:ocores-i2c");