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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / infiniband / hw / cxgb4 / iw_cxgb4.h
blobcc929002c05eb3ee244f95b1a33329fa72ab139a
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31 #ifndef __IW_CXGB4_H__
32 #define __IW_CXGB4_H__
33
34 #include <linux/mutex.h>
35 #include <linux/list.h>
36 #include <linux/spinlock.h>
37 #include <linux/idr.h>
38 #include <linux/completion.h>
39 #include <linux/netdevice.h>
40 #include <linux/sched/mm.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/inet.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
47 #include <linux/io.h>
48 #include <linux/workqueue.h>
49
50 #include <asm/byteorder.h>
51
52 #include <net/net_namespace.h>
53
54 #include <rdma/ib_verbs.h>
55 #include <rdma/iw_cm.h>
56 #include <rdma/rdma_netlink.h>
57 #include <rdma/iw_portmap.h>
58
59 #include "cxgb4.h"
60 #include "cxgb4_uld.h"
61 #include "l2t.h"
62 #include <rdma/cxgb4-abi.h>
63
64 #define DRV_NAME "iw_cxgb4"
65 #define MOD DRV_NAME ":"
66
67 #ifdef pr_fmt
68 #undef pr_fmt
69 #endif
70
71 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
72
73 #include "t4.h"
74
75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
77
78 static inline void *cplhdr(struct sk_buff *skb)
79 {
80 return skb->data;
81 }
82
83 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
84 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
85
86 struct c4iw_id_table {
87 u32 flags;
88 u32 start; /* logical minimal id */
89 u32 last; /* hint for find */
90 u32 max;
91 spinlock_t lock;
92 unsigned long *table;
93 };
94
95 struct c4iw_resource {
96 struct c4iw_id_table tpt_table;
97 struct c4iw_id_table qid_table;
98 struct c4iw_id_table pdid_table;
99 };
100
101 struct c4iw_qid_list {
102 struct list_head entry;
103 u32 qid;
104 };
105
106 struct c4iw_dev_ucontext {
107 struct list_head qpids;
108 struct list_head cqids;
109 struct mutex lock;
110 struct kref kref;
111 };
112
113 enum c4iw_rdev_flags {
114 T4_FATAL_ERROR = (1<<0),
115 T4_STATUS_PAGE_DISABLED = (1<<1),
116 };
117
118 struct c4iw_stat {
119 u64 total;
120 u64 cur;
121 u64 max;
122 u64 fail;
123 };
124
125 struct c4iw_stats {
126 struct mutex lock;
127 struct c4iw_stat qid;
128 struct c4iw_stat pd;
129 struct c4iw_stat stag;
130 struct c4iw_stat pbl;
131 struct c4iw_stat rqt;
132 struct c4iw_stat ocqp;
133 u64 db_full;
134 u64 db_empty;
135 u64 db_drop;
136 u64 db_state_transitions;
137 u64 db_fc_interruptions;
138 u64 tcam_full;
139 u64 act_ofld_conn_fails;
140 u64 pas_ofld_conn_fails;
141 u64 neg_adv;
142 };
143
144 struct c4iw_hw_queue {
145 int t4_eq_status_entries;
146 int t4_max_eq_size;
147 int t4_max_iq_size;
148 int t4_max_rq_size;
149 int t4_max_sq_size;
150 int t4_max_qp_depth;
151 int t4_max_cq_depth;
152 int t4_stat_len;
153 };
154
155 struct wr_log_entry {
156 ktime_t post_host_time;
157 ktime_t poll_host_time;
158 u64 post_sge_ts;
159 u64 cqe_sge_ts;
160 u64 poll_sge_ts;
161 u16 qid;
162 u16 wr_id;
163 u8 opcode;
164 u8 valid;
165 };
166
167 struct c4iw_rdev {
168 struct c4iw_resource resource;
169 u32 qpmask;
170 u32 cqmask;
171 struct c4iw_dev_ucontext uctx;
172 struct gen_pool *pbl_pool;
173 struct gen_pool *rqt_pool;
174 struct gen_pool *ocqp_pool;
175 u32 flags;
176 struct cxgb4_lld_info lldi;
177 unsigned long bar2_pa;
178 void __iomem *bar2_kva;
179 unsigned long oc_mw_pa;
180 void __iomem *oc_mw_kva;
181 struct c4iw_stats stats;
182 struct c4iw_hw_queue hw_queue;
183 struct t4_dev_status_page *status_page;
184 atomic_t wr_log_idx;
185 struct wr_log_entry *wr_log;
186 int wr_log_size;
187 struct workqueue_struct *free_workq;
188 };
189
190 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
191 {
192 return rdev->flags & T4_FATAL_ERROR;
193 }
194
195 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
196 {
197 return (int)(rdev->lldi.vr->stag.size >> 5);
198 }
199
200 #define C4IW_WR_TO (60*HZ)
201
202 struct c4iw_wr_wait {
203 struct completion completion;
204 int ret;
205 struct kref kref;
206 };
207
208 void _c4iw_free_wr_wait(struct kref *kref);
209
210 static inline void c4iw_put_wr_wait(struct c4iw_wr_wait *wr_waitp)
211 {
212 pr_debug("wr_wait %p ref before put %u\n", wr_waitp,
213 kref_read(&wr_waitp->kref));
214 WARN_ON(kref_read(&wr_waitp->kref) == 0);
215 kref_put(&wr_waitp->kref, _c4iw_free_wr_wait);
216 }
217
218 static inline void c4iw_get_wr_wait(struct c4iw_wr_wait *wr_waitp)
219 {
220 pr_debug("wr_wait %p ref before get %u\n", wr_waitp,
221 kref_read(&wr_waitp->kref));
222 WARN_ON(kref_read(&wr_waitp->kref) == 0);
223 kref_get(&wr_waitp->kref);
224 }
225
226 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
227 {
228 wr_waitp->ret = 0;
229 init_completion(&wr_waitp->completion);
230 }
231
232 static inline void _c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret,
233 bool deref)
234 {
235 wr_waitp->ret = ret;
236 complete(&wr_waitp->completion);
237 if (deref)
238 c4iw_put_wr_wait(wr_waitp);
239 }
240
241 static inline void c4iw_wake_up_noref(struct c4iw_wr_wait *wr_waitp, int ret)
242 {
243 _c4iw_wake_up(wr_waitp, ret, false);
244 }
245
246 static inline void c4iw_wake_up_deref(struct c4iw_wr_wait *wr_waitp, int ret)
247 {
248 _c4iw_wake_up(wr_waitp, ret, true);
249 }
250
251 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
252 struct c4iw_wr_wait *wr_waitp,
253 u32 hwtid, u32 qpid,
254 const char *func)
255 {
256 int ret;
257
258 if (c4iw_fatal_error(rdev)) {
259 wr_waitp->ret = -EIO;
260 goto out;
261 }
262
263 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
264 if (!ret) {
265 pr_err("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
266 func, pci_name(rdev->lldi.pdev), hwtid, qpid);
267 rdev->flags |= T4_FATAL_ERROR;
268 wr_waitp->ret = -EIO;
269 goto out;
270 }
271 if (wr_waitp->ret)
272 pr_debug("%s: FW reply %d tid %u qpid %u\n",
273 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
274 out:
275 return wr_waitp->ret;
276 }
277
278 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
279
280 static inline int c4iw_ref_send_wait(struct c4iw_rdev *rdev,
281 struct sk_buff *skb,
282 struct c4iw_wr_wait *wr_waitp,
283 u32 hwtid, u32 qpid,
284 const char *func)
285 {
286 int ret;
287
288 pr_debug("%s wr_wait %p hwtid %u qpid %u\n", func, wr_waitp, hwtid,
289 qpid);
290 c4iw_get_wr_wait(wr_waitp);
291 ret = c4iw_ofld_send(rdev, skb);
292 if (ret) {
293 c4iw_put_wr_wait(wr_waitp);
294 return ret;
295 }
296 return c4iw_wait_for_reply(rdev, wr_waitp, hwtid, qpid, func);
297 }
298
299 enum db_state {
300 NORMAL = 0,
301 FLOW_CONTROL = 1,
302 RECOVERY = 2,
303 STOPPED = 3
304 };
305
306 struct c4iw_dev {
307 struct ib_device ibdev;
308 struct c4iw_rdev rdev;
309 u32 device_cap_flags;
310 struct idr cqidr;
311 struct idr qpidr;
312 struct idr mmidr;
313 spinlock_t lock;
314 struct mutex db_mutex;
315 struct dentry *debugfs_root;
316 enum db_state db_state;
317 struct idr hwtid_idr;
318 struct idr atid_idr;
319 struct idr stid_idr;
320 struct list_head db_fc_list;
321 u32 avail_ird;
322 wait_queue_head_t wait;
323 };
324
325 struct uld_ctx {
326 struct list_head entry;
327 struct cxgb4_lld_info lldi;
328 struct c4iw_dev *dev;
329 struct work_struct reg_work;
330 };
331
332 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
333 {
334 return container_of(ibdev, struct c4iw_dev, ibdev);
335 }
336
337 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
338 {
339 return container_of(rdev, struct c4iw_dev, rdev);
340 }
341
342 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
343 {
344 return idr_find(&rhp->cqidr, cqid);
345 }
346
347 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
348 {
349 return idr_find(&rhp->qpidr, qpid);
350 }
351
352 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
353 {
354 return idr_find(&rhp->mmidr, mmid);
355 }
356
357 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
358 void *handle, u32 id, int lock)
359 {
360 int ret;
361
362 if (lock) {
363 idr_preload(GFP_KERNEL);
364 spin_lock_irq(&rhp->lock);
365 }
366
367 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
368
369 if (lock) {
370 spin_unlock_irq(&rhp->lock);
371 idr_preload_end();
372 }
373
374 return ret < 0 ? ret : 0;
375 }
376
377 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
378 void *handle, u32 id)
379 {
380 return _insert_handle(rhp, idr, handle, id, 1);
381 }
382
383 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
384 void *handle, u32 id)
385 {
386 return _insert_handle(rhp, idr, handle, id, 0);
387 }
388
389 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
390 u32 id, int lock)
391 {
392 if (lock)
393 spin_lock_irq(&rhp->lock);
394 idr_remove(idr, id);
395 if (lock)
396 spin_unlock_irq(&rhp->lock);
397 }
398
399 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
400 {
401 _remove_handle(rhp, idr, id, 1);
402 }
403
404 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
405 struct idr *idr, u32 id)
406 {
407 _remove_handle(rhp, idr, id, 0);
408 }
409
410 extern uint c4iw_max_read_depth;
411
412 static inline int cur_max_read_depth(struct c4iw_dev *dev)
413 {
414 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
415 }
416
417 struct c4iw_pd {
418 struct ib_pd ibpd;
419 u32 pdid;
420 struct c4iw_dev *rhp;
421 };
422
423 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
424 {
425 return container_of(ibpd, struct c4iw_pd, ibpd);
426 }
427
428 struct tpt_attributes {
429 u64 len;
430 u64 va_fbo;
431 enum fw_ri_mem_perms perms;
432 u32 stag;
433 u32 pdid;
434 u32 qpid;
435 u32 pbl_addr;
436 u32 pbl_size;
437 u32 state:1;
438 u32 type:2;
439 u32 rsvd:1;
440 u32 remote_invaliate_disable:1;
441 u32 zbva:1;
442 u32 mw_bind_enable:1;
443 u32 page_size:5;
444 };
445
446 struct c4iw_mr {
447 struct ib_mr ibmr;
448 struct ib_umem *umem;
449 struct c4iw_dev *rhp;
450 struct sk_buff *dereg_skb;
451 u64 kva;
452 struct tpt_attributes attr;
453 u64 *mpl;
454 dma_addr_t mpl_addr;
455 u32 max_mpl_len;
456 u32 mpl_len;
457 struct c4iw_wr_wait *wr_waitp;
458 };
459
460 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
461 {
462 return container_of(ibmr, struct c4iw_mr, ibmr);
463 }
464
465 struct c4iw_mw {
466 struct ib_mw ibmw;
467 struct c4iw_dev *rhp;
468 struct sk_buff *dereg_skb;
469 u64 kva;
470 struct tpt_attributes attr;
471 struct c4iw_wr_wait *wr_waitp;
472 };
473
474 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
475 {
476 return container_of(ibmw, struct c4iw_mw, ibmw);
477 }
478
479 struct c4iw_cq {
480 struct ib_cq ibcq;
481 struct c4iw_dev *rhp;
482 struct sk_buff *destroy_skb;
483 struct t4_cq cq;
484 spinlock_t lock;
485 spinlock_t comp_handler_lock;
486 atomic_t refcnt;
487 wait_queue_head_t wait;
488 struct c4iw_wr_wait *wr_waitp;
489 };
490
491 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
492 {
493 return container_of(ibcq, struct c4iw_cq, ibcq);
494 }
495
496 struct c4iw_mpa_attributes {
497 u8 initiator;
498 u8 recv_marker_enabled;
499 u8 xmit_marker_enabled;
500 u8 crc_enabled;
501 u8 enhanced_rdma_conn;
502 u8 version;
503 u8 p2p_type;
504 };
505
506 struct c4iw_qp_attributes {
507 u32 scq;
508 u32 rcq;
509 u32 sq_num_entries;
510 u32 rq_num_entries;
511 u32 sq_max_sges;
512 u32 sq_max_sges_rdma_write;
513 u32 rq_max_sges;
514 u32 state;
515 u8 enable_rdma_read;
516 u8 enable_rdma_write;
517 u8 enable_bind;
518 u8 enable_mmid0_fastreg;
519 u32 max_ord;
520 u32 max_ird;
521 u32 pd;
522 u32 next_state;
523 char terminate_buffer[52];
524 u32 terminate_msg_len;
525 u8 is_terminate_local;
526 struct c4iw_mpa_attributes mpa_attr;
527 struct c4iw_ep *llp_stream_handle;
528 u8 layer_etype;
529 u8 ecode;
530 u16 sq_db_inc;
531 u16 rq_db_inc;
532 u8 send_term;
533 };
534
535 struct c4iw_qp {
536 struct ib_qp ibqp;
537 struct list_head db_fc_entry;
538 struct c4iw_dev *rhp;
539 struct c4iw_ep *ep;
540 struct c4iw_qp_attributes attr;
541 struct t4_wq wq;
542 spinlock_t lock;
543 struct mutex mutex;
544 struct kref kref;
545 wait_queue_head_t wait;
546 int sq_sig_all;
547 struct work_struct free_work;
548 struct c4iw_ucontext *ucontext;
549 struct c4iw_wr_wait *wr_waitp;
550 };
551
552 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
553 {
554 return container_of(ibqp, struct c4iw_qp, ibqp);
555 }
556
557 struct c4iw_ucontext {
558 struct ib_ucontext ibucontext;
559 struct c4iw_dev_ucontext uctx;
560 u32 key;
561 spinlock_t mmap_lock;
562 struct list_head mmaps;
563 struct kref kref;
564 };
565
566 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
567 {
568 return container_of(c, struct c4iw_ucontext, ibucontext);
569 }
570
571 void _c4iw_free_ucontext(struct kref *kref);
572
573 static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext)
574 {
575 kref_put(&ucontext->kref, _c4iw_free_ucontext);
576 }
577
578 static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext)
579 {
580 kref_get(&ucontext->kref);
581 }
582
583 struct c4iw_mm_entry {
584 struct list_head entry;
585 u64 addr;
586 u32 key;
587 unsigned len;
588 };
589
590 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
591 u32 key, unsigned len)
592 {
593 struct list_head *pos, *nxt;
594 struct c4iw_mm_entry *mm;
595
596 spin_lock(&ucontext->mmap_lock);
597 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
598
599 mm = list_entry(pos, struct c4iw_mm_entry, entry);
600 if (mm->key == key && mm->len == len) {
601 list_del_init(&mm->entry);
602 spin_unlock(&ucontext->mmap_lock);
603 pr_debug("key 0x%x addr 0x%llx len %d\n", key,
604 (unsigned long long)mm->addr, mm->len);
605 return mm;
606 }
607 }
608 spin_unlock(&ucontext->mmap_lock);
609 return NULL;
610 }
611
612 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
613 struct c4iw_mm_entry *mm)
614 {
615 spin_lock(&ucontext->mmap_lock);
616 pr_debug("key 0x%x addr 0x%llx len %d\n",
617 mm->key, (unsigned long long)mm->addr, mm->len);
618 list_add_tail(&mm->entry, &ucontext->mmaps);
619 spin_unlock(&ucontext->mmap_lock);
620 }
621
622 enum c4iw_qp_attr_mask {
623 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
624 C4IW_QP_ATTR_SQ_DB = 1<<1,
625 C4IW_QP_ATTR_RQ_DB = 1<<2,
626 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
627 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
628 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
629 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
630 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
631 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
632 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
633 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
634 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
635 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
636 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
637 C4IW_QP_ATTR_MAX_ORD |
638 C4IW_QP_ATTR_MAX_IRD |
639 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
640 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
641 C4IW_QP_ATTR_MPA_ATTR |
642 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
643 };
644
645 int c4iw_modify_qp(struct c4iw_dev *rhp,
646 struct c4iw_qp *qhp,
647 enum c4iw_qp_attr_mask mask,
648 struct c4iw_qp_attributes *attrs,
649 int internal);
650
651 enum c4iw_qp_state {
652 C4IW_QP_STATE_IDLE,
653 C4IW_QP_STATE_RTS,
654 C4IW_QP_STATE_ERROR,
655 C4IW_QP_STATE_TERMINATE,
656 C4IW_QP_STATE_CLOSING,
657 C4IW_QP_STATE_TOT
658 };
659
660 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
661 {
662 switch (ib_state) {
663 case IB_QPS_RESET:
664 case IB_QPS_INIT:
665 return C4IW_QP_STATE_IDLE;
666 case IB_QPS_RTS:
667 return C4IW_QP_STATE_RTS;
668 case IB_QPS_SQD:
669 return C4IW_QP_STATE_CLOSING;
670 case IB_QPS_SQE:
671 return C4IW_QP_STATE_TERMINATE;
672 case IB_QPS_ERR:
673 return C4IW_QP_STATE_ERROR;
674 default:
675 return -1;
676 }
677 }
678
679 static inline int to_ib_qp_state(int c4iw_qp_state)
680 {
681 switch (c4iw_qp_state) {
682 case C4IW_QP_STATE_IDLE:
683 return IB_QPS_INIT;
684 case C4IW_QP_STATE_RTS:
685 return IB_QPS_RTS;
686 case C4IW_QP_STATE_CLOSING:
687 return IB_QPS_SQD;
688 case C4IW_QP_STATE_TERMINATE:
689 return IB_QPS_SQE;
690 case C4IW_QP_STATE_ERROR:
691 return IB_QPS_ERR;
692 }
693 return IB_QPS_ERR;
694 }
695
696 static inline u32 c4iw_ib_to_tpt_access(int a)
697 {
698 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
699 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
700 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
701 FW_RI_MEM_ACCESS_LOCAL_READ;
702 }
703
704 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
705 {
706 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
707 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
708 }
709
710 enum c4iw_mmid_state {
711 C4IW_STAG_STATE_VALID,
712 C4IW_STAG_STATE_INVALID
713 };
714
715 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
716
717 #define MPA_KEY_REQ "MPA ID Req Frame"
718 #define MPA_KEY_REP "MPA ID Rep Frame"
719
720 #define MPA_MAX_PRIVATE_DATA 256
721 #define MPA_ENHANCED_RDMA_CONN 0x10
722 #define MPA_REJECT 0x20
723 #define MPA_CRC 0x40
724 #define MPA_MARKERS 0x80
725 #define MPA_FLAGS_MASK 0xE0
726
727 #define MPA_V2_PEER2PEER_MODEL 0x8000
728 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
729 #define MPA_V2_RDMA_WRITE_RTR 0x8000
730 #define MPA_V2_RDMA_READ_RTR 0x4000
731 #define MPA_V2_IRD_ORD_MASK 0x3FFF
732
733 #define c4iw_put_ep(ep) { \
734 pr_debug("put_ep ep %p refcnt %d\n", \
735 ep, kref_read(&((ep)->kref))); \
736 WARN_ON(kref_read(&((ep)->kref)) < 1); \
737 kref_put(&((ep)->kref), _c4iw_free_ep); \
738 }
739
740 #define c4iw_get_ep(ep) { \
741 pr_debug("get_ep ep %p, refcnt %d\n", \
742 ep, kref_read(&((ep)->kref))); \
743 kref_get(&((ep)->kref)); \
744 }
745 void _c4iw_free_ep(struct kref *kref);
746
747 struct mpa_message {
748 u8 key[16];
749 u8 flags;
750 u8 revision;
751 __be16 private_data_size;
752 u8 private_data[0];
753 };
754
755 struct mpa_v2_conn_params {
756 __be16 ird;
757 __be16 ord;
758 };
759
760 struct terminate_message {
761 u8 layer_etype;
762 u8 ecode;
763 __be16 hdrct_rsvd;
764 u8 len_hdrs[0];
765 };
766
767 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
768
769 enum c4iw_layers_types {
770 LAYER_RDMAP = 0x00,
771 LAYER_DDP = 0x10,
772 LAYER_MPA = 0x20,
773 RDMAP_LOCAL_CATA = 0x00,
774 RDMAP_REMOTE_PROT = 0x01,
775 RDMAP_REMOTE_OP = 0x02,
776 DDP_LOCAL_CATA = 0x00,
777 DDP_TAGGED_ERR = 0x01,
778 DDP_UNTAGGED_ERR = 0x02,
779 DDP_LLP = 0x03
780 };
781
782 enum c4iw_rdma_ecodes {
783 RDMAP_INV_STAG = 0x00,
784 RDMAP_BASE_BOUNDS = 0x01,
785 RDMAP_ACC_VIOL = 0x02,
786 RDMAP_STAG_NOT_ASSOC = 0x03,
787 RDMAP_TO_WRAP = 0x04,
788 RDMAP_INV_VERS = 0x05,
789 RDMAP_INV_OPCODE = 0x06,
790 RDMAP_STREAM_CATA = 0x07,
791 RDMAP_GLOBAL_CATA = 0x08,
792 RDMAP_CANT_INV_STAG = 0x09,
793 RDMAP_UNSPECIFIED = 0xff
794 };
795
796 enum c4iw_ddp_ecodes {
797 DDPT_INV_STAG = 0x00,
798 DDPT_BASE_BOUNDS = 0x01,
799 DDPT_STAG_NOT_ASSOC = 0x02,
800 DDPT_TO_WRAP = 0x03,
801 DDPT_INV_VERS = 0x04,
802 DDPU_INV_QN = 0x01,
803 DDPU_INV_MSN_NOBUF = 0x02,
804 DDPU_INV_MSN_RANGE = 0x03,
805 DDPU_INV_MO = 0x04,
806 DDPU_MSG_TOOBIG = 0x05,
807 DDPU_INV_VERS = 0x06
808 };
809
810 enum c4iw_mpa_ecodes {
811 MPA_CRC_ERR = 0x02,
812 MPA_MARKER_ERR = 0x03,
813 MPA_LOCAL_CATA = 0x05,
814 MPA_INSUFF_IRD = 0x06,
815 MPA_NOMATCH_RTR = 0x07,
816 };
817
818 enum c4iw_ep_state {
819 IDLE = 0,
820 LISTEN,
821 CONNECTING,
822 MPA_REQ_WAIT,
823 MPA_REQ_SENT,
824 MPA_REQ_RCVD,
825 MPA_REP_SENT,
826 FPDU_MODE,
827 ABORTING,
828 CLOSING,
829 MORIBUND,
830 DEAD,
831 };
832
833 enum c4iw_ep_flags {
834 PEER_ABORT_IN_PROGRESS = 0,
835 ABORT_REQ_IN_PROGRESS = 1,
836 RELEASE_RESOURCES = 2,
837 CLOSE_SENT = 3,
838 TIMEOUT = 4,
839 QP_REFERENCED = 5,
840 STOP_MPA_TIMER = 7,
841 };
842
843 enum c4iw_ep_history {
844 ACT_OPEN_REQ = 0,
845 ACT_OFLD_CONN = 1,
846 ACT_OPEN_RPL = 2,
847 ACT_ESTAB = 3,
848 PASS_ACCEPT_REQ = 4,
849 PASS_ESTAB = 5,
850 ABORT_UPCALL = 6,
851 ESTAB_UPCALL = 7,
852 CLOSE_UPCALL = 8,
853 ULP_ACCEPT = 9,
854 ULP_REJECT = 10,
855 TIMEDOUT = 11,
856 PEER_ABORT = 12,
857 PEER_CLOSE = 13,
858 CONNREQ_UPCALL = 14,
859 ABORT_CONN = 15,
860 DISCONN_UPCALL = 16,
861 EP_DISC_CLOSE = 17,
862 EP_DISC_ABORT = 18,
863 CONN_RPL_UPCALL = 19,
864 ACT_RETRY_NOMEM = 20,
865 ACT_RETRY_INUSE = 21,
866 CLOSE_CON_RPL = 22,
867 EP_DISC_FAIL = 24,
868 QP_REFED = 25,
869 QP_DEREFED = 26,
870 CM_ID_REFED = 27,
871 CM_ID_DEREFED = 28,
872 };
873
874 enum conn_pre_alloc_buffers {
875 CN_ABORT_REQ_BUF,
876 CN_ABORT_RPL_BUF,
877 CN_CLOSE_CON_REQ_BUF,
878 CN_DESTROY_BUF,
879 CN_FLOWC_BUF,
880 CN_MAX_CON_BUF
881 };
882
883 #define FLOWC_LEN 80
884 union cpl_wr_size {
885 struct cpl_abort_req abrt_req;
886 struct cpl_abort_rpl abrt_rpl;
887 struct fw_ri_wr ri_req;
888 struct cpl_close_con_req close_req;
889 char flowc_buf[FLOWC_LEN];
890 };
891
892 struct c4iw_ep_common {
893 struct iw_cm_id *cm_id;
894 struct c4iw_qp *qp;
895 struct c4iw_dev *dev;
896 struct sk_buff_head ep_skb_list;
897 enum c4iw_ep_state state;
898 struct kref kref;
899 struct mutex mutex;
900 struct sockaddr_storage local_addr;
901 struct sockaddr_storage remote_addr;
902 struct c4iw_wr_wait *wr_waitp;
903 unsigned long flags;
904 unsigned long history;
905 };
906
907 struct c4iw_listen_ep {
908 struct c4iw_ep_common com;
909 unsigned int stid;
910 int backlog;
911 };
912
913 struct c4iw_ep_stats {
914 unsigned connect_neg_adv;
915 unsigned abort_neg_adv;
916 };
917
918 struct c4iw_ep {
919 struct c4iw_ep_common com;
920 struct c4iw_ep *parent_ep;
921 struct timer_list timer;
922 struct list_head entry;
923 unsigned int atid;
924 u32 hwtid;
925 u32 snd_seq;
926 u32 rcv_seq;
927 struct l2t_entry *l2t;
928 struct dst_entry *dst;
929 struct sk_buff *mpa_skb;
930 struct c4iw_mpa_attributes mpa_attr;
931 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
932 unsigned int mpa_pkt_len;
933 u32 ird;
934 u32 ord;
935 u32 smac_idx;
936 u32 tx_chan;
937 u32 mtu;
938 u16 mss;
939 u16 emss;
940 u16 plen;
941 u16 rss_qid;
942 u16 txq_idx;
943 u16 ctrlq_idx;
944 u8 tos;
945 u8 retry_with_mpa_v1;
946 u8 tried_with_mpa_v1;
947 unsigned int retry_count;
948 int snd_win;
949 int rcv_win;
950 struct c4iw_ep_stats stats;
951 };
952
953 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
954 {
955 return cm_id->provider_data;
956 }
957
958 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
959 {
960 return cm_id->provider_data;
961 }
962
963 static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
964 {
965 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
966 return infop->vr->ocq.size > 0;
967 #else
968 return 0;
969 #endif
970 }
971
972 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
973 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
974 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
975 u32 reserved, u32 flags);
976 void c4iw_id_table_free(struct c4iw_id_table *alloc);
977
978 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
979
980 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
981 struct l2t_entry *l2t);
982 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
983 struct c4iw_dev_ucontext *uctx);
984 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
985 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
986 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
987 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
988 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
989 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
990 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
991 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
992 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
993 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
994 void c4iw_destroy_resource(struct c4iw_resource *rscp);
995 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
996 void c4iw_register_device(struct work_struct *work);
997 void c4iw_unregister_device(struct c4iw_dev *dev);
998 int __init c4iw_cm_init(void);
999 void c4iw_cm_term(void);
1000 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
1001 struct c4iw_dev_ucontext *uctx);
1002 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
1003 struct c4iw_dev_ucontext *uctx);
1004 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1005 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1006 struct ib_send_wr **bad_wr);
1007 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1008 struct ib_recv_wr **bad_wr);
1009 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
1010 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
1011 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
1012 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
1013 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
1014 void c4iw_qp_add_ref(struct ib_qp *qp);
1015 void c4iw_qp_rem_ref(struct ib_qp *qp);
1016 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
1017 enum ib_mr_type mr_type,
1018 u32 max_num_sg);
1019 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1020 unsigned int *sg_offset);
1021 int c4iw_dealloc_mw(struct ib_mw *mw);
1022 void c4iw_dealloc(struct uld_ctx *ctx);
1023 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1024 struct ib_udata *udata);
1025 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
1026 u64 length, u64 virt, int acc,
1027 struct ib_udata *udata);
1028 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
1029 int c4iw_dereg_mr(struct ib_mr *ib_mr);
1030 int c4iw_destroy_cq(struct ib_cq *ib_cq);
1031 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
1032 const struct ib_cq_init_attr *attr,
1033 struct ib_ucontext *ib_context,
1034 struct ib_udata *udata);
1035 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
1036 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1037 int c4iw_destroy_qp(struct ib_qp *ib_qp);
1038 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
1039 struct ib_qp_init_attr *attrs,
1040 struct ib_udata *udata);
1041 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1042 int attr_mask, struct ib_udata *udata);
1043 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1044 int attr_mask, struct ib_qp_init_attr *init_attr);
1045 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
1046 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
1047 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1048 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
1049 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1050 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
1051 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1052 void c4iw_flush_hw_cq(struct c4iw_cq *chp);
1053 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
1054 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
1055 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1056 int c4iw_flush_sq(struct c4iw_qp *qhp);
1057 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
1058 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
1059 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
1060 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1061 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
1062 struct c4iw_dev_ucontext *uctx);
1063 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1064 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
1065 struct c4iw_dev_ucontext *uctx);
1066 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
1067
1068 extern struct cxgb4_client t4c_client;
1069 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
1070 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
1071 enum cxgb4_bar2_qtype qtype,
1072 unsigned int *pbar2_qid, u64 *pbar2_pa);
1073 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
1074 extern int c4iw_wr_log;
1075 extern int db_fc_threshold;
1076 extern int db_coalescing_threshold;
1077 extern int use_dsgl;
1078 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
1079 struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp);
1080
1081 #endif
CRIS linux kernel tree