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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / infiniband / hw / cxgb4 / mem.c
blob7e0eb201cc26d22c12d8d847c47231e87f86c98e
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <rdma/ib_umem.h>
36 #include <linux/atomic.h>
37 #include <rdma/ib_user_verbs.h>
38
39 #include "iw_cxgb4.h"
40
41 int use_dsgl = 1;
42 module_param(use_dsgl, int, 0644);
43 MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=1) (DEPRECATED)");
44
45 #define T4_ULPTX_MIN_IO 32
46 #define C4IW_MAX_INLINE_SIZE 96
47 #define T4_ULPTX_MAX_DMA 1024
48 #define C4IW_INLINE_THRESHOLD 128
49
50 static int inline_threshold = C4IW_INLINE_THRESHOLD;
51 module_param(inline_threshold, int, 0644);
52 MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)");
53
54 static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
55 {
56 return (is_t4(dev->rdev.lldi.adapter_type) ||
57 is_t5(dev->rdev.lldi.adapter_type)) &&
58 length >= 8*1024*1024*1024ULL;
59 }
60
61 static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
62 u32 len, dma_addr_t data,
63 struct sk_buff *skb,
64 struct c4iw_wr_wait *wr_waitp)
65 {
66 struct ulp_mem_io *req;
67 struct ulptx_sgl *sgl;
68 u8 wr_len;
69 int ret = 0;
70
71 addr &= 0x7FFFFFF;
72
73 if (wr_waitp)
74 c4iw_init_wr_wait(wr_waitp);
75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16);
76
77 if (!skb) {
78 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
79 if (!skb)
80 return -ENOMEM;
81 }
82 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
83
84 req = __skb_put_zero(skb, wr_len);
85 INIT_ULPTX_WR(req, wr_len, 0, 0);
86 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
87 (wr_waitp ? FW_WR_COMPL_F : 0));
88 req->wr.wr_lo = wr_waitp ? (__force __be64)(unsigned long)wr_waitp : 0L;
89 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
90 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
91 T5_ULP_MEMIO_ORDER_V(1) |
92 T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0]));
93 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5));
94 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16));
95 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr));
96
97 sgl = (struct ulptx_sgl *)(req + 1);
98 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
99 ULPTX_NSGE_V(1));
100 sgl->len0 = cpu_to_be32(len);
101 sgl->addr0 = cpu_to_be64(data);
102
103 if (wr_waitp)
104 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
105 else
106 ret = c4iw_ofld_send(rdev, skb);
107 return ret;
108 }
109
110 static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
111 void *data, struct sk_buff *skb,
112 struct c4iw_wr_wait *wr_waitp)
113 {
114 struct ulp_mem_io *req;
115 struct ulptx_idata *sc;
116 u8 wr_len, *to_dp, *from_dp;
117 int copy_len, num_wqe, i, ret = 0;
118 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
119
120 if (is_t4(rdev->lldi.adapter_type))
121 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F);
122 else
123 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F);
124
125 addr &= 0x7FFFFFF;
126 pr_debug("addr 0x%x len %u\n", addr, len);
127 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
128 c4iw_init_wr_wait(wr_waitp);
129 for (i = 0; i < num_wqe; i++) {
130
131 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
132 len;
133 wr_len = roundup(sizeof *req + sizeof *sc +
134 roundup(copy_len, T4_ULPTX_MIN_IO), 16);
135
136 if (!skb) {
137 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
138 if (!skb)
139 return -ENOMEM;
140 }
141 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
142
143 req = __skb_put_zero(skb, wr_len);
144 INIT_ULPTX_WR(req, wr_len, 0, 0);
145
146 if (i == (num_wqe-1)) {
147 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
148 FW_WR_COMPL_F);
149 req->wr.wr_lo = (__force __be64)(unsigned long)wr_waitp;
150 } else
151 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
152 req->wr.wr_mid = cpu_to_be32(
153 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
154
155 req->cmd = cmd;
156 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(
157 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
158 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr),
159 16));
160 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3));
161
162 sc = (struct ulptx_idata *)(req + 1);
163 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM));
164 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
165
166 to_dp = (u8 *)(sc + 1);
167 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
168 if (data)
169 memcpy(to_dp, from_dp, copy_len);
170 else
171 memset(to_dp, 0, copy_len);
172 if (copy_len % T4_ULPTX_MIN_IO)
173 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
174 (copy_len % T4_ULPTX_MIN_IO));
175 if (i == (num_wqe-1))
176 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0,
177 __func__);
178 else
179 ret = c4iw_ofld_send(rdev, skb);
180 if (ret)
181 break;
182 skb = NULL;
183 len -= C4IW_MAX_INLINE_SIZE;
184 }
185
186 return ret;
187 }
188
189 static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len,
190 void *data, struct sk_buff *skb,
191 struct c4iw_wr_wait *wr_waitp)
192 {
193 u32 remain = len;
194 u32 dmalen;
195 int ret = 0;
196 dma_addr_t daddr;
197 dma_addr_t save;
198
199 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE);
200 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr))
201 return -1;
202 save = daddr;
203
204 while (remain > inline_threshold) {
205 if (remain < T4_ULPTX_MAX_DMA) {
206 if (remain & ~T4_ULPTX_MIN_IO)
207 dmalen = remain & ~(T4_ULPTX_MIN_IO-1);
208 else
209 dmalen = remain;
210 } else
211 dmalen = T4_ULPTX_MAX_DMA;
212 remain -= dmalen;
213 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
214 skb, remain ? NULL : wr_waitp);
215 if (ret)
216 goto out;
217 addr += dmalen >> 5;
218 data += dmalen;
219 daddr += dmalen;
220 }
221 if (remain)
222 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb,
223 wr_waitp);
224 out:
225 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
226 return ret;
227 }
228
229 /*
230 * write len bytes of data into addr (32B aligned address)
231 * If data is NULL, clear len byte of memory to zero.
232 */
233 static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
234 void *data, struct sk_buff *skb,
235 struct c4iw_wr_wait *wr_waitp)
236 {
237 int ret;
238
239 if (!rdev->lldi.ulptx_memwrite_dsgl || !use_dsgl) {
240 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
241 wr_waitp);
242 goto out;
243 }
244
245 if (len <= inline_threshold) {
246 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
247 wr_waitp);
248 goto out;
249 }
250
251 ret = _c4iw_write_mem_dma(rdev, addr, len, data, skb, wr_waitp);
252 if (ret) {
253 pr_warn_ratelimited("%s: dma map failure (non fatal)\n",
254 pci_name(rdev->lldi.pdev));
255 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
256 wr_waitp);
257 }
258 out:
259 return ret;
260
261 }
262
263 /*
264 * Build and write a TPT entry.
265 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size,
266 * pbl_size and pbl_addr
267 * OUT: stag index
268 */
269 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
270 u32 *stag, u8 stag_state, u32 pdid,
271 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
272 int bind_enabled, u32 zbva, u64 to,
273 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr,
274 struct sk_buff *skb, struct c4iw_wr_wait *wr_waitp)
275 {
276 int err;
277 struct fw_ri_tpte tpt;
278 u32 stag_idx;
279 static atomic_t key;
280
281 if (c4iw_fatal_error(rdev))
282 return -EIO;
283
284 stag_state = stag_state > 0;
285 stag_idx = (*stag) >> 8;
286
287 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
288 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
289 if (!stag_idx) {
290 mutex_lock(&rdev->stats.lock);
291 rdev->stats.stag.fail++;
292 mutex_unlock(&rdev->stats.lock);
293 return -ENOMEM;
294 }
295 mutex_lock(&rdev->stats.lock);
296 rdev->stats.stag.cur += 32;
297 if (rdev->stats.stag.cur > rdev->stats.stag.max)
298 rdev->stats.stag.max = rdev->stats.stag.cur;
299 mutex_unlock(&rdev->stats.lock);
300 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
301 }
302 pr_debug("stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
303 stag_state, type, pdid, stag_idx);
304
305 /* write TPT entry */
306 if (reset_tpt_entry)
307 memset(&tpt, 0, sizeof(tpt));
308 else {
309 tpt.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
310 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) |
311 FW_RI_TPTE_STAGSTATE_V(stag_state) |
312 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid));
313 tpt.locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) |
314 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) |
315 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO :
316 FW_RI_VA_BASED_TO))|
317 FW_RI_TPTE_PS_V(page_size));
318 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
319 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3));
320 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
321 tpt.va_hi = cpu_to_be32((u32)(to >> 32));
322 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
323 tpt.dca_mwbcnt_pstag = cpu_to_be32(0);
324 tpt.len_hi = cpu_to_be32((u32)(len >> 32));
325 }
326 err = write_adapter_mem(rdev, stag_idx +
327 (rdev->lldi.vr->stag.start >> 5),
328 sizeof(tpt), &tpt, skb, wr_waitp);
329
330 if (reset_tpt_entry) {
331 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
332 mutex_lock(&rdev->stats.lock);
333 rdev->stats.stag.cur -= 32;
334 mutex_unlock(&rdev->stats.lock);
335 }
336 return err;
337 }
338
339 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
340 u32 pbl_addr, u32 pbl_size, struct c4iw_wr_wait *wr_waitp)
341 {
342 int err;
343
344 pr_debug("*pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
345 pbl_addr, rdev->lldi.vr->pbl.start,
346 pbl_size);
347
348 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL,
349 wr_waitp);
350 return err;
351 }
352
353 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
354 u32 pbl_addr, struct sk_buff *skb,
355 struct c4iw_wr_wait *wr_waitp)
356 {
357 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
358 pbl_size, pbl_addr, skb, wr_waitp);
359 }
360
361 static int allocate_window(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
362 struct c4iw_wr_wait *wr_waitp)
363 {
364 *stag = T4_STAG_UNSET;
365 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
366 0UL, 0, 0, 0, 0, NULL, wr_waitp);
367 }
368
369 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag,
370 struct sk_buff *skb,
371 struct c4iw_wr_wait *wr_waitp)
372 {
373 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
374 0, skb, wr_waitp);
375 }
376
377 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
378 u32 pbl_size, u32 pbl_addr,
379 struct c4iw_wr_wait *wr_waitp)
380 {
381 *stag = T4_STAG_UNSET;
382 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
383 0UL, 0, 0, pbl_size, pbl_addr, NULL, wr_waitp);
384 }
385
386 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
387 {
388 u32 mmid;
389
390 mhp->attr.state = 1;
391 mhp->attr.stag = stag;
392 mmid = stag >> 8;
393 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
394 pr_debug("mmid 0x%x mhp %p\n", mmid, mhp);
395 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
396 }
397
398 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
399 struct c4iw_mr *mhp, int shift)
400 {
401 u32 stag = T4_STAG_UNSET;
402 int ret;
403
404 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
405 FW_RI_STAG_NSMR, mhp->attr.len ?
406 mhp->attr.perms : 0,
407 mhp->attr.mw_bind_enable, mhp->attr.zbva,
408 mhp->attr.va_fbo, mhp->attr.len ?
409 mhp->attr.len : -1, shift - 12,
410 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL,
411 mhp->wr_waitp);
412 if (ret)
413 return ret;
414
415 ret = finish_mem_reg(mhp, stag);
416 if (ret) {
417 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
418 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
419 mhp->dereg_skb = NULL;
420 }
421 return ret;
422 }
423
424 static int alloc_pbl(struct c4iw_mr *mhp, int npages)
425 {
426 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
427 npages << 3);
428
429 if (!mhp->attr.pbl_addr)
430 return -ENOMEM;
431
432 mhp->attr.pbl_size = npages;
433
434 return 0;
435 }
436
437 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
438 {
439 struct c4iw_dev *rhp;
440 struct c4iw_pd *php;
441 struct c4iw_mr *mhp;
442 int ret;
443 u32 stag = T4_STAG_UNSET;
444
445 pr_debug("ib_pd %p\n", pd);
446 php = to_c4iw_pd(pd);
447 rhp = php->rhp;
448
449 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
450 if (!mhp)
451 return ERR_PTR(-ENOMEM);
452 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
453 if (!mhp->wr_waitp) {
454 ret = -ENOMEM;
455 goto err_free_mhp;
456 }
457 c4iw_init_wr_wait(mhp->wr_waitp);
458
459 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
460 if (!mhp->dereg_skb) {
461 ret = -ENOMEM;
462 goto err_free_wr_wait;
463 }
464
465 mhp->rhp = rhp;
466 mhp->attr.pdid = php->pdid;
467 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
468 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
469 mhp->attr.zbva = 0;
470 mhp->attr.va_fbo = 0;
471 mhp->attr.page_size = 0;
472 mhp->attr.len = ~0ULL;
473 mhp->attr.pbl_size = 0;
474
475 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
476 FW_RI_STAG_NSMR, mhp->attr.perms,
477 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0,
478 NULL, mhp->wr_waitp);
479 if (ret)
480 goto err_free_skb;
481
482 ret = finish_mem_reg(mhp, stag);
483 if (ret)
484 goto err_dereg_mem;
485 return &mhp->ibmr;
486 err_dereg_mem:
487 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
488 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
489 err_free_wr_wait:
490 c4iw_put_wr_wait(mhp->wr_waitp);
491 err_free_skb:
492 kfree_skb(mhp->dereg_skb);
493 err_free_mhp:
494 kfree(mhp);
495 return ERR_PTR(ret);
496 }
497
498 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
499 u64 virt, int acc, struct ib_udata *udata)
500 {
501 __be64 *pages;
502 int shift, n, len;
503 int i, k, entry;
504 int err = -ENOMEM;
505 struct scatterlist *sg;
506 struct c4iw_dev *rhp;
507 struct c4iw_pd *php;
508 struct c4iw_mr *mhp;
509
510 pr_debug("ib_pd %p\n", pd);
511
512 if (length == ~0ULL)
513 return ERR_PTR(-EINVAL);
514
515 if ((length + start) < start)
516 return ERR_PTR(-EINVAL);
517
518 php = to_c4iw_pd(pd);
519 rhp = php->rhp;
520
521 if (mr_exceeds_hw_limits(rhp, length))
522 return ERR_PTR(-EINVAL);
523
524 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
525 if (!mhp)
526 return ERR_PTR(-ENOMEM);
527 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
528 if (!mhp->wr_waitp)
529 goto err_free_mhp;
530
531 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
532 if (!mhp->dereg_skb)
533 goto err_free_wr_wait;
534
535 mhp->rhp = rhp;
536
537 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0);
538 if (IS_ERR(mhp->umem))
539 goto err_free_skb;
540
541 shift = mhp->umem->page_shift;
542
543 n = mhp->umem->nmap;
544 err = alloc_pbl(mhp, n);
545 if (err)
546 goto err_umem_release;
547
548 pages = (__be64 *) __get_free_page(GFP_KERNEL);
549 if (!pages) {
550 err = -ENOMEM;
551 goto err_pbl_free;
552 }
553
554 i = n = 0;
555
556 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) {
557 len = sg_dma_len(sg) >> shift;
558 for (k = 0; k < len; ++k) {
559 pages[i++] = cpu_to_be64(sg_dma_address(sg) +
560 (k << shift));
561 if (i == PAGE_SIZE / sizeof *pages) {
562 err = write_pbl(&mhp->rhp->rdev,
563 pages,
564 mhp->attr.pbl_addr + (n << 3), i,
565 mhp->wr_waitp);
566 if (err)
567 goto pbl_done;
568 n += i;
569 i = 0;
570 }
571 }
572 }
573
574 if (i)
575 err = write_pbl(&mhp->rhp->rdev, pages,
576 mhp->attr.pbl_addr + (n << 3), i,
577 mhp->wr_waitp);
578
579 pbl_done:
580 free_page((unsigned long) pages);
581 if (err)
582 goto err_pbl_free;
583
584 mhp->attr.pdid = php->pdid;
585 mhp->attr.zbva = 0;
586 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
587 mhp->attr.va_fbo = virt;
588 mhp->attr.page_size = shift - 12;
589 mhp->attr.len = length;
590
591 err = register_mem(rhp, php, mhp, shift);
592 if (err)
593 goto err_pbl_free;
594
595 return &mhp->ibmr;
596
597 err_pbl_free:
598 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
599 mhp->attr.pbl_size << 3);
600 err_umem_release:
601 ib_umem_release(mhp->umem);
602 err_free_skb:
603 kfree_skb(mhp->dereg_skb);
604 err_free_wr_wait:
605 c4iw_put_wr_wait(mhp->wr_waitp);
606 err_free_mhp:
607 kfree(mhp);
608 return ERR_PTR(err);
609 }
610
611 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
612 struct ib_udata *udata)
613 {
614 struct c4iw_dev *rhp;
615 struct c4iw_pd *php;
616 struct c4iw_mw *mhp;
617 u32 mmid;
618 u32 stag = 0;
619 int ret;
620
621 if (type != IB_MW_TYPE_1)
622 return ERR_PTR(-EINVAL);
623
624 php = to_c4iw_pd(pd);
625 rhp = php->rhp;
626 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
627 if (!mhp)
628 return ERR_PTR(-ENOMEM);
629
630 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
631 if (!mhp->wr_waitp) {
632 ret = -ENOMEM;
633 goto free_mhp;
634 }
635
636 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
637 if (!mhp->dereg_skb) {
638 ret = -ENOMEM;
639 goto free_wr_wait;
640 }
641
642 ret = allocate_window(&rhp->rdev, &stag, php->pdid, mhp->wr_waitp);
643 if (ret)
644 goto free_skb;
645 mhp->rhp = rhp;
646 mhp->attr.pdid = php->pdid;
647 mhp->attr.type = FW_RI_STAG_MW;
648 mhp->attr.stag = stag;
649 mmid = (stag) >> 8;
650 mhp->ibmw.rkey = stag;
651 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
652 ret = -ENOMEM;
653 goto dealloc_win;
654 }
655 pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag);
656 return &(mhp->ibmw);
657
658 dealloc_win:
659 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb,
660 mhp->wr_waitp);
661 free_skb:
662 kfree_skb(mhp->dereg_skb);
663 free_wr_wait:
664 c4iw_put_wr_wait(mhp->wr_waitp);
665 free_mhp:
666 kfree(mhp);
667 return ERR_PTR(ret);
668 }
669
670 int c4iw_dealloc_mw(struct ib_mw *mw)
671 {
672 struct c4iw_dev *rhp;
673 struct c4iw_mw *mhp;
674 u32 mmid;
675
676 mhp = to_c4iw_mw(mw);
677 rhp = mhp->rhp;
678 mmid = (mw->rkey) >> 8;
679 remove_handle(rhp, &rhp->mmidr, mmid);
680 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb,
681 mhp->wr_waitp);
682 kfree_skb(mhp->dereg_skb);
683 c4iw_put_wr_wait(mhp->wr_waitp);
684 kfree(mhp);
685 pr_debug("ib_mw %p mmid 0x%x ptr %p\n", mw, mmid, mhp);
686 return 0;
687 }
688
689 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
690 enum ib_mr_type mr_type,
691 u32 max_num_sg)
692 {
693 struct c4iw_dev *rhp;
694 struct c4iw_pd *php;
695 struct c4iw_mr *mhp;
696 u32 mmid;
697 u32 stag = 0;
698 int ret = 0;
699 int length = roundup(max_num_sg * sizeof(u64), 32);
700
701 php = to_c4iw_pd(pd);
702 rhp = php->rhp;
703
704 if (mr_type != IB_MR_TYPE_MEM_REG ||
705 max_num_sg > t4_max_fr_depth(rhp->rdev.lldi.ulptx_memwrite_dsgl &&
706 use_dsgl))
707 return ERR_PTR(-EINVAL);
708
709 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
710 if (!mhp) {
711 ret = -ENOMEM;
712 goto err;
713 }
714
715 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
716 if (!mhp->wr_waitp) {
717 ret = -ENOMEM;
718 goto err_free_mhp;
719 }
720 c4iw_init_wr_wait(mhp->wr_waitp);
721
722 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev,
723 length, &mhp->mpl_addr, GFP_KERNEL);
724 if (!mhp->mpl) {
725 ret = -ENOMEM;
726 goto err_free_wr_wait;
727 }
728 mhp->max_mpl_len = length;
729
730 mhp->rhp = rhp;
731 ret = alloc_pbl(mhp, max_num_sg);
732 if (ret)
733 goto err_free_dma;
734 mhp->attr.pbl_size = max_num_sg;
735 ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
736 mhp->attr.pbl_size, mhp->attr.pbl_addr,
737 mhp->wr_waitp);
738 if (ret)
739 goto err_free_pbl;
740 mhp->attr.pdid = php->pdid;
741 mhp->attr.type = FW_RI_STAG_NSMR;
742 mhp->attr.stag = stag;
743 mhp->attr.state = 0;
744 mmid = (stag) >> 8;
745 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
746 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
747 ret = -ENOMEM;
748 goto err_dereg;
749 }
750
751 pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag);
752 return &(mhp->ibmr);
753 err_dereg:
754 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
755 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
756 err_free_pbl:
757 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
758 mhp->attr.pbl_size << 3);
759 err_free_dma:
760 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
761 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
762 err_free_wr_wait:
763 c4iw_put_wr_wait(mhp->wr_waitp);
764 err_free_mhp:
765 kfree(mhp);
766 err:
767 return ERR_PTR(ret);
768 }
769
770 static int c4iw_set_page(struct ib_mr *ibmr, u64 addr)
771 {
772 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
773
774 if (unlikely(mhp->mpl_len == mhp->max_mpl_len))
775 return -ENOMEM;
776
777 mhp->mpl[mhp->mpl_len++] = addr;
778
779 return 0;
780 }
781
782 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
783 unsigned int *sg_offset)
784 {
785 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
786
787 mhp->mpl_len = 0;
788
789 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page);
790 }
791
792 int c4iw_dereg_mr(struct ib_mr *ib_mr)
793 {
794 struct c4iw_dev *rhp;
795 struct c4iw_mr *mhp;
796 u32 mmid;
797
798 pr_debug("ib_mr %p\n", ib_mr);
799
800 mhp = to_c4iw_mr(ib_mr);
801 rhp = mhp->rhp;
802 mmid = mhp->attr.stag >> 8;
803 remove_handle(rhp, &rhp->mmidr, mmid);
804 if (mhp->mpl)
805 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
806 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
807 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
808 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
809 if (mhp->attr.pbl_size)
810 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
811 mhp->attr.pbl_size << 3);
812 if (mhp->kva)
813 kfree((void *) (unsigned long) mhp->kva);
814 if (mhp->umem)
815 ib_umem_release(mhp->umem);
816 pr_debug("mmid 0x%x ptr %p\n", mmid, mhp);
817 c4iw_put_wr_wait(mhp->wr_waitp);
818 kfree(mhp);
819 return 0;
820 }
821
822 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey)
823 {
824 struct c4iw_mr *mhp;
825 unsigned long flags;
826
827 spin_lock_irqsave(&rhp->lock, flags);
828 mhp = get_mhp(rhp, rkey >> 8);
829 if (mhp)
830 mhp->attr.state = 0;
831 spin_unlock_irqrestore(&rhp->lock, flags);
832 }
CRIS linux kernel tree