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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / infiniband / hw / i40iw / i40iw_verbs.c
blob70024e8e26922dd6109c39538c0496ec71ffb254
1 /*******************************************************************************
2 *
3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenFabrics.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 *******************************************************************************/
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/random.h>
38 #include <linux/highmem.h>
39 #include <linux/time.h>
40 #include <linux/hugetlb.h>
41 #include <asm/byteorder.h>
42 #include <net/ip.h>
43 #include <rdma/ib_verbs.h>
44 #include <rdma/iw_cm.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_umem.h>
47 #include "i40iw.h"
48
49 /**
50 * i40iw_query_device - get device attributes
51 * @ibdev: device pointer from stack
52 * @props: returning device attributes
53 * @udata: user data
54 */
55 static int i40iw_query_device(struct ib_device *ibdev,
56 struct ib_device_attr *props,
57 struct ib_udata *udata)
58 {
59 struct i40iw_device *iwdev = to_iwdev(ibdev);
60
61 if (udata->inlen || udata->outlen)
62 return -EINVAL;
63 memset(props, 0, sizeof(*props));
64 ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
65 props->fw_ver = I40IW_FW_VERSION;
66 props->device_cap_flags = iwdev->device_cap_flags;
67 props->vendor_id = iwdev->ldev->pcidev->vendor;
68 props->vendor_part_id = iwdev->ldev->pcidev->device;
69 props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
70 props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
71 props->max_qp = iwdev->max_qp - iwdev->used_qps;
72 props->max_qp_wr = I40IW_MAX_QP_WRS;
73 props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
74 props->max_cq = iwdev->max_cq - iwdev->used_cqs;
75 props->max_cqe = iwdev->max_cqe;
76 props->max_mr = iwdev->max_mr - iwdev->used_mrs;
77 props->max_pd = iwdev->max_pd - iwdev->used_pds;
78 props->max_sge_rd = I40IW_MAX_SGE_RD;
79 props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
80 props->max_qp_init_rd_atom = props->max_qp_rd_atom;
81 props->atomic_cap = IB_ATOMIC_NONE;
82 props->max_map_per_fmr = 1;
83 props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR;
84 return 0;
85 }
86
87 /**
88 * i40iw_query_port - get port attrubutes
89 * @ibdev: device pointer from stack
90 * @port: port number for query
91 * @props: returning device attributes
92 */
93 static int i40iw_query_port(struct ib_device *ibdev,
94 u8 port,
95 struct ib_port_attr *props)
96 {
97 struct i40iw_device *iwdev = to_iwdev(ibdev);
98 struct net_device *netdev = iwdev->netdev;
99
100 /* props being zeroed by the caller, avoid zeroing it here */
101 props->max_mtu = IB_MTU_4096;
102 props->active_mtu = ib_mtu_int_to_enum(netdev->mtu);
103
104 props->lid = 1;
105 if (netif_carrier_ok(iwdev->netdev))
106 props->state = IB_PORT_ACTIVE;
107 else
108 props->state = IB_PORT_DOWN;
109 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
110 IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
111 props->gid_tbl_len = 1;
112 props->pkey_tbl_len = 1;
113 props->active_width = IB_WIDTH_4X;
114 props->active_speed = 1;
115 props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
116 return 0;
117 }
118
119 /**
120 * i40iw_alloc_ucontext - Allocate the user context data structure
121 * @ibdev: device pointer from stack
122 * @udata: user data
123 *
124 * This keeps track of all objects associated with a particular
125 * user-mode client.
126 */
127 static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev,
128 struct ib_udata *udata)
129 {
130 struct i40iw_device *iwdev = to_iwdev(ibdev);
131 struct i40iw_alloc_ucontext_req req;
132 struct i40iw_alloc_ucontext_resp uresp;
133 struct i40iw_ucontext *ucontext;
134
135 if (ib_copy_from_udata(&req, udata, sizeof(req)))
136 return ERR_PTR(-EINVAL);
137
138 if (req.userspace_ver < 4 || req.userspace_ver > I40IW_ABI_VER) {
139 i40iw_pr_err("Unsupported provider library version %u.\n", req.userspace_ver);
140 return ERR_PTR(-EINVAL);
141 }
142
143 memset(&uresp, 0, sizeof(uresp));
144 uresp.max_qps = iwdev->max_qp;
145 uresp.max_pds = iwdev->max_pd;
146 uresp.wq_size = iwdev->max_qp_wr * 2;
147 uresp.kernel_ver = req.userspace_ver;
148
149 ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL);
150 if (!ucontext)
151 return ERR_PTR(-ENOMEM);
152
153 ucontext->iwdev = iwdev;
154 ucontext->abi_ver = req.userspace_ver;
155
156 if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
157 kfree(ucontext);
158 return ERR_PTR(-EFAULT);
159 }
160
161 INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
162 spin_lock_init(&ucontext->cq_reg_mem_list_lock);
163 INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
164 spin_lock_init(&ucontext->qp_reg_mem_list_lock);
165
166 return &ucontext->ibucontext;
167 }
168
169 /**
170 * i40iw_dealloc_ucontext - deallocate the user context data structure
171 * @context: user context created during alloc
172 */
173 static int i40iw_dealloc_ucontext(struct ib_ucontext *context)
174 {
175 struct i40iw_ucontext *ucontext = to_ucontext(context);
176 unsigned long flags;
177
178 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
179 if (!list_empty(&ucontext->cq_reg_mem_list)) {
180 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
181 return -EBUSY;
182 }
183 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
184 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
185 if (!list_empty(&ucontext->qp_reg_mem_list)) {
186 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
187 return -EBUSY;
188 }
189 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
190
191 kfree(ucontext);
192 return 0;
193 }
194
195 /**
196 * i40iw_mmap - user memory map
197 * @context: context created during alloc
198 * @vma: kernel info for user memory map
199 */
200 static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
201 {
202 struct i40iw_ucontext *ucontext;
203 u64 db_addr_offset;
204 u64 push_offset;
205
206 ucontext = to_ucontext(context);
207 if (ucontext->iwdev->sc_dev.is_pf) {
208 db_addr_offset = I40IW_DB_ADDR_OFFSET;
209 push_offset = I40IW_PUSH_OFFSET;
210 if (vma->vm_pgoff)
211 vma->vm_pgoff += I40IW_PF_FIRST_PUSH_PAGE_INDEX - 1;
212 } else {
213 db_addr_offset = I40IW_VF_DB_ADDR_OFFSET;
214 push_offset = I40IW_VF_PUSH_OFFSET;
215 if (vma->vm_pgoff)
216 vma->vm_pgoff += I40IW_VF_FIRST_PUSH_PAGE_INDEX - 1;
217 }
218
219 vma->vm_pgoff += db_addr_offset >> PAGE_SHIFT;
220
221 if (vma->vm_pgoff == (db_addr_offset >> PAGE_SHIFT)) {
222 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
223 vma->vm_private_data = ucontext;
224 } else {
225 if ((vma->vm_pgoff - (push_offset >> PAGE_SHIFT)) % 2)
226 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
227 else
228 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
229 }
230
231 if (io_remap_pfn_range(vma, vma->vm_start,
232 vma->vm_pgoff + (pci_resource_start(ucontext->iwdev->ldev->pcidev, 0) >> PAGE_SHIFT),
233 PAGE_SIZE, vma->vm_page_prot))
234 return -EAGAIN;
235
236 return 0;
237 }
238
239 /**
240 * i40iw_alloc_push_page - allocate a push page for qp
241 * @iwdev: iwarp device
242 * @qp: hardware control qp
243 */
244 static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
245 {
246 struct i40iw_cqp_request *cqp_request;
247 struct cqp_commands_info *cqp_info;
248 enum i40iw_status_code status;
249
250 if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
251 return;
252
253 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
254 if (!cqp_request)
255 return;
256
257 atomic_inc(&cqp_request->refcount);
258
259 cqp_info = &cqp_request->info;
260 cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
261 cqp_info->post_sq = 1;
262
263 cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
264 cqp_info->in.u.manage_push_page.info.free_page = 0;
265 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
266 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
267
268 status = i40iw_handle_cqp_op(iwdev, cqp_request);
269 if (!status)
270 qp->push_idx = cqp_request->compl_info.op_ret_val;
271 else
272 i40iw_pr_err("CQP-OP Push page fail");
273 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
274 }
275
276 /**
277 * i40iw_dealloc_push_page - free a push page for qp
278 * @iwdev: iwarp device
279 * @qp: hardware control qp
280 */
281 static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
282 {
283 struct i40iw_cqp_request *cqp_request;
284 struct cqp_commands_info *cqp_info;
285 enum i40iw_status_code status;
286
287 if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
288 return;
289
290 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
291 if (!cqp_request)
292 return;
293
294 cqp_info = &cqp_request->info;
295 cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
296 cqp_info->post_sq = 1;
297
298 cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
299 cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
300 cqp_info->in.u.manage_push_page.info.free_page = 1;
301 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
302 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
303
304 status = i40iw_handle_cqp_op(iwdev, cqp_request);
305 if (!status)
306 qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
307 else
308 i40iw_pr_err("CQP-OP Push page fail");
309 }
310
311 /**
312 * i40iw_alloc_pd - allocate protection domain
313 * @ibdev: device pointer from stack
314 * @context: user context created during alloc
315 * @udata: user data
316 */
317 static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
318 struct ib_ucontext *context,
319 struct ib_udata *udata)
320 {
321 struct i40iw_pd *iwpd;
322 struct i40iw_device *iwdev = to_iwdev(ibdev);
323 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
324 struct i40iw_alloc_pd_resp uresp;
325 struct i40iw_sc_pd *sc_pd;
326 struct i40iw_ucontext *ucontext;
327 u32 pd_id = 0;
328 int err;
329
330 if (iwdev->closing)
331 return ERR_PTR(-ENODEV);
332
333 err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
334 iwdev->max_pd, &pd_id, &iwdev->next_pd);
335 if (err) {
336 i40iw_pr_err("alloc resource failed\n");
337 return ERR_PTR(err);
338 }
339
340 iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL);
341 if (!iwpd) {
342 err = -ENOMEM;
343 goto free_res;
344 }
345
346 sc_pd = &iwpd->sc_pd;
347
348 if (context) {
349 ucontext = to_ucontext(context);
350 dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
351 memset(&uresp, 0, sizeof(uresp));
352 uresp.pd_id = pd_id;
353 if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
354 err = -EFAULT;
355 goto error;
356 }
357 } else {
358 dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, -1);
359 }
360
361 i40iw_add_pdusecount(iwpd);
362 return &iwpd->ibpd;
363 error:
364 kfree(iwpd);
365 free_res:
366 i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
367 return ERR_PTR(err);
368 }
369
370 /**
371 * i40iw_dealloc_pd - deallocate pd
372 * @ibpd: ptr of pd to be deallocated
373 */
374 static int i40iw_dealloc_pd(struct ib_pd *ibpd)
375 {
376 struct i40iw_pd *iwpd = to_iwpd(ibpd);
377 struct i40iw_device *iwdev = to_iwdev(ibpd->device);
378
379 i40iw_rem_pdusecount(iwpd, iwdev);
380 return 0;
381 }
382
383 /**
384 * i40iw_get_pbl - Retrieve pbl from a list given a virtual
385 * address
386 * @va: user virtual address
387 * @pbl_list: pbl list to search in (QP's or CQ's)
388 */
389 static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
390 struct list_head *pbl_list)
391 {
392 struct i40iw_pbl *iwpbl;
393
394 list_for_each_entry(iwpbl, pbl_list, list) {
395 if (iwpbl->user_base == va) {
396 list_del(&iwpbl->list);
397 return iwpbl;
398 }
399 }
400 return NULL;
401 }
402
403 /**
404 * i40iw_free_qp_resources - free up memory resources for qp
405 * @iwdev: iwarp device
406 * @iwqp: qp ptr (user or kernel)
407 * @qp_num: qp number assigned
408 */
409 void i40iw_free_qp_resources(struct i40iw_device *iwdev,
410 struct i40iw_qp *iwqp,
411 u32 qp_num)
412 {
413 struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
414
415 i40iw_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp);
416 i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp);
417 if (qp_num)
418 i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
419 if (iwpbl->pbl_allocated)
420 i40iw_free_pble(iwdev->pble_rsrc, &iwpbl->pble_alloc);
421 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
422 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
423 kfree(iwqp->kqp.wrid_mem);
424 iwqp->kqp.wrid_mem = NULL;
425 kfree(iwqp->allocated_buffer);
426 }
427
428 /**
429 * i40iw_clean_cqes - clean cq entries for qp
430 * @iwqp: qp ptr (user or kernel)
431 * @iwcq: cq ptr
432 */
433 static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
434 {
435 struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
436
437 ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
438 }
439
440 /**
441 * i40iw_destroy_qp - destroy qp
442 * @ibqp: qp's ib pointer also to get to device's qp address
443 */
444 static int i40iw_destroy_qp(struct ib_qp *ibqp)
445 {
446 struct i40iw_qp *iwqp = to_iwqp(ibqp);
447
448 iwqp->destroyed = 1;
449
450 if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
451 i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
452
453 if (!iwqp->user_mode) {
454 if (iwqp->iwscq) {
455 i40iw_clean_cqes(iwqp, iwqp->iwscq);
456 if (iwqp->iwrcq != iwqp->iwscq)
457 i40iw_clean_cqes(iwqp, iwqp->iwrcq);
458 }
459 }
460
461 i40iw_rem_ref(&iwqp->ibqp);
462 return 0;
463 }
464
465 /**
466 * i40iw_setup_virt_qp - setup for allocation of virtual qp
467 * @dev: iwarp device
468 * @qp: qp ptr
469 * @init_info: initialize info to return
470 */
471 static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
472 struct i40iw_qp *iwqp,
473 struct i40iw_qp_init_info *init_info)
474 {
475 struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
476 struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
477
478 iwqp->page = qpmr->sq_page;
479 init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
480 if (iwpbl->pbl_allocated) {
481 init_info->virtual_map = true;
482 init_info->sq_pa = qpmr->sq_pbl.idx;
483 init_info->rq_pa = qpmr->rq_pbl.idx;
484 } else {
485 init_info->sq_pa = qpmr->sq_pbl.addr;
486 init_info->rq_pa = qpmr->rq_pbl.addr;
487 }
488 return 0;
489 }
490
491 /**
492 * i40iw_setup_kmode_qp - setup initialization for kernel mode qp
493 * @iwdev: iwarp device
494 * @iwqp: qp ptr (user or kernel)
495 * @info: initialize info to return
496 */
497 static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
498 struct i40iw_qp *iwqp,
499 struct i40iw_qp_init_info *info)
500 {
501 struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
502 u32 sqdepth, rqdepth;
503 u8 sqshift;
504 u32 size;
505 enum i40iw_status_code status;
506 struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
507
508 i40iw_get_wqe_shift(ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
509 status = i40iw_get_sqdepth(ukinfo->sq_size, sqshift, &sqdepth);
510 if (status)
511 return -ENOMEM;
512
513 status = i40iw_get_rqdepth(ukinfo->rq_size, I40IW_MAX_RQ_WQE_SHIFT, &rqdepth);
514 if (status)
515 return -ENOMEM;
516
517 size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
518 iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
519
520 ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
521 if (!ukinfo->sq_wrtrk_array)
522 return -ENOMEM;
523
524 ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
525
526 size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
527 size += (I40IW_SHADOW_AREA_SIZE << 3);
528
529 status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
530 if (status) {
531 kfree(ukinfo->sq_wrtrk_array);
532 ukinfo->sq_wrtrk_array = NULL;
533 return -ENOMEM;
534 }
535
536 ukinfo->sq = mem->va;
537 info->sq_pa = mem->pa;
538
539 ukinfo->rq = &ukinfo->sq[sqdepth];
540 info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
541
542 ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
543 info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
544
545 ukinfo->sq_size = sqdepth >> sqshift;
546 ukinfo->rq_size = rqdepth >> I40IW_MAX_RQ_WQE_SHIFT;
547 ukinfo->qp_id = iwqp->ibqp.qp_num;
548 return 0;
549 }
550
551 /**
552 * i40iw_create_qp - create qp
553 * @ibpd: ptr of pd
554 * @init_attr: attributes for qp
555 * @udata: user data for create qp
556 */
557 static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
558 struct ib_qp_init_attr *init_attr,
559 struct ib_udata *udata)
560 {
561 struct i40iw_pd *iwpd = to_iwpd(ibpd);
562 struct i40iw_device *iwdev = to_iwdev(ibpd->device);
563 struct i40iw_cqp *iwcqp = &iwdev->cqp;
564 struct i40iw_qp *iwqp;
565 struct i40iw_ucontext *ucontext;
566 struct i40iw_create_qp_req req;
567 struct i40iw_create_qp_resp uresp;
568 u32 qp_num = 0;
569 void *mem;
570 enum i40iw_status_code ret;
571 int err_code;
572 int sq_size;
573 int rq_size;
574 struct i40iw_sc_qp *qp;
575 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
576 struct i40iw_qp_init_info init_info;
577 struct i40iw_create_qp_info *qp_info;
578 struct i40iw_cqp_request *cqp_request;
579 struct cqp_commands_info *cqp_info;
580
581 struct i40iw_qp_host_ctx_info *ctx_info;
582 struct i40iwarp_offload_info *iwarp_info;
583 unsigned long flags;
584
585 if (iwdev->closing)
586 return ERR_PTR(-ENODEV);
587
588 if (init_attr->create_flags)
589 return ERR_PTR(-EINVAL);
590 if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
591 init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
592
593 if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
594 init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
595
596 if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
597 init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
598
599 memset(&init_info, 0, sizeof(init_info));
600
601 sq_size = init_attr->cap.max_send_wr;
602 rq_size = init_attr->cap.max_recv_wr;
603
604 init_info.vsi = &iwdev->vsi;
605 init_info.qp_uk_init_info.sq_size = sq_size;
606 init_info.qp_uk_init_info.rq_size = rq_size;
607 init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
608 init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
609 init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
610
611 mem = kzalloc(sizeof(*iwqp), GFP_KERNEL);
612 if (!mem)
613 return ERR_PTR(-ENOMEM);
614
615 iwqp = (struct i40iw_qp *)mem;
616 qp = &iwqp->sc_qp;
617 qp->back_qp = (void *)iwqp;
618 qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
619
620 iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
621
622 if (i40iw_allocate_dma_mem(dev->hw,
623 &iwqp->q2_ctx_mem,
624 I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
625 256)) {
626 i40iw_pr_err("dma_mem failed\n");
627 err_code = -ENOMEM;
628 goto error;
629 }
630
631 init_info.q2 = iwqp->q2_ctx_mem.va;
632 init_info.q2_pa = iwqp->q2_ctx_mem.pa;
633
634 init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
635 init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
636
637 err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
638 &qp_num, &iwdev->next_qp);
639 if (err_code) {
640 i40iw_pr_err("qp resource\n");
641 goto error;
642 }
643
644 iwqp->allocated_buffer = mem;
645 iwqp->iwdev = iwdev;
646 iwqp->iwpd = iwpd;
647 iwqp->ibqp.qp_num = qp_num;
648 qp = &iwqp->sc_qp;
649 iwqp->iwscq = to_iwcq(init_attr->send_cq);
650 iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
651
652 iwqp->host_ctx.va = init_info.host_ctx;
653 iwqp->host_ctx.pa = init_info.host_ctx_pa;
654 iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
655
656 init_info.pd = &iwpd->sc_pd;
657 init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
658 iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
659
660 if (init_attr->qp_type != IB_QPT_RC) {
661 err_code = -EINVAL;
662 goto error;
663 }
664 if (iwdev->push_mode)
665 i40iw_alloc_push_page(iwdev, qp);
666 if (udata) {
667 err_code = ib_copy_from_udata(&req, udata, sizeof(req));
668 if (err_code) {
669 i40iw_pr_err("ib_copy_from_data\n");
670 goto error;
671 }
672 iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
673 if (ibpd->uobject && ibpd->uobject->context) {
674 iwqp->user_mode = 1;
675 ucontext = to_ucontext(ibpd->uobject->context);
676
677 if (req.user_wqe_buffers) {
678 struct i40iw_pbl *iwpbl;
679
680 spin_lock_irqsave(
681 &ucontext->qp_reg_mem_list_lock, flags);
682 iwpbl = i40iw_get_pbl(
683 (unsigned long)req.user_wqe_buffers,
684 &ucontext->qp_reg_mem_list);
685 spin_unlock_irqrestore(
686 &ucontext->qp_reg_mem_list_lock, flags);
687
688 if (!iwpbl) {
689 err_code = -ENODATA;
690 i40iw_pr_err("no pbl info\n");
691 goto error;
692 }
693 memcpy(&iwqp->iwpbl, iwpbl, sizeof(iwqp->iwpbl));
694 }
695 }
696 err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
697 } else {
698 err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
699 }
700
701 if (err_code) {
702 i40iw_pr_err("setup qp failed\n");
703 goto error;
704 }
705
706 init_info.type = I40IW_QP_TYPE_IWARP;
707 ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
708 if (ret) {
709 err_code = -EPROTO;
710 i40iw_pr_err("qp_init fail\n");
711 goto error;
712 }
713 ctx_info = &iwqp->ctx_info;
714 iwarp_info = &iwqp->iwarp_info;
715 iwarp_info->rd_enable = true;
716 iwarp_info->wr_rdresp_en = true;
717 if (!iwqp->user_mode) {
718 iwarp_info->fast_reg_en = true;
719 iwarp_info->priv_mode_en = true;
720 }
721 iwarp_info->ddp_ver = 1;
722 iwarp_info->rdmap_ver = 1;
723
724 ctx_info->iwarp_info_valid = true;
725 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
726 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
727 if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) {
728 ctx_info->push_mode_en = false;
729 } else {
730 ctx_info->push_mode_en = true;
731 ctx_info->push_idx = qp->push_idx;
732 }
733
734 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
735 (u64 *)iwqp->host_ctx.va,
736 ctx_info);
737 ctx_info->iwarp_info_valid = false;
738 cqp_request = i40iw_get_cqp_request(iwcqp, true);
739 if (!cqp_request) {
740 err_code = -ENOMEM;
741 goto error;
742 }
743 cqp_info = &cqp_request->info;
744 qp_info = &cqp_request->info.in.u.qp_create.info;
745
746 memset(qp_info, 0, sizeof(*qp_info));
747
748 qp_info->cq_num_valid = true;
749 qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
750
751 cqp_info->cqp_cmd = OP_QP_CREATE;
752 cqp_info->post_sq = 1;
753 cqp_info->in.u.qp_create.qp = qp;
754 cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
755 ret = i40iw_handle_cqp_op(iwdev, cqp_request);
756 if (ret) {
757 i40iw_pr_err("CQP-OP QP create fail");
758 err_code = -EACCES;
759 goto error;
760 }
761
762 i40iw_add_ref(&iwqp->ibqp);
763 spin_lock_init(&iwqp->lock);
764 iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
765 iwdev->qp_table[qp_num] = iwqp;
766 i40iw_add_pdusecount(iwqp->iwpd);
767 i40iw_add_devusecount(iwdev);
768 if (ibpd->uobject && udata) {
769 memset(&uresp, 0, sizeof(uresp));
770 uresp.actual_sq_size = sq_size;
771 uresp.actual_rq_size = rq_size;
772 uresp.qp_id = qp_num;
773 uresp.push_idx = qp->push_idx;
774 err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
775 if (err_code) {
776 i40iw_pr_err("copy_to_udata failed\n");
777 i40iw_destroy_qp(&iwqp->ibqp);
778 /* let the completion of the qp destroy free the qp */
779 return ERR_PTR(err_code);
780 }
781 }
782 init_completion(&iwqp->sq_drained);
783 init_completion(&iwqp->rq_drained);
784
785 return &iwqp->ibqp;
786 error:
787 i40iw_free_qp_resources(iwdev, iwqp, qp_num);
788 return ERR_PTR(err_code);
789 }
790
791 /**
792 * i40iw_query - query qp attributes
793 * @ibqp: qp pointer
794 * @attr: attributes pointer
795 * @attr_mask: Not used
796 * @init_attr: qp attributes to return
797 */
798 static int i40iw_query_qp(struct ib_qp *ibqp,
799 struct ib_qp_attr *attr,
800 int attr_mask,
801 struct ib_qp_init_attr *init_attr)
802 {
803 struct i40iw_qp *iwqp = to_iwqp(ibqp);
804 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
805
806 attr->qp_access_flags = 0;
807 attr->cap.max_send_wr = qp->qp_uk.sq_size;
808 attr->cap.max_recv_wr = qp->qp_uk.rq_size;
809 attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
810 attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
811 attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
812 attr->port_num = 1;
813 init_attr->event_handler = iwqp->ibqp.event_handler;
814 init_attr->qp_context = iwqp->ibqp.qp_context;
815 init_attr->send_cq = iwqp->ibqp.send_cq;
816 init_attr->recv_cq = iwqp->ibqp.recv_cq;
817 init_attr->srq = iwqp->ibqp.srq;
818 init_attr->cap = attr->cap;
819 init_attr->port_num = 1;
820 return 0;
821 }
822
823 /**
824 * i40iw_hw_modify_qp - setup cqp for modify qp
825 * @iwdev: iwarp device
826 * @iwqp: qp ptr (user or kernel)
827 * @info: info for modify qp
828 * @wait: flag to wait or not for modify qp completion
829 */
830 void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
831 struct i40iw_modify_qp_info *info, bool wait)
832 {
833 enum i40iw_status_code status;
834 struct i40iw_cqp_request *cqp_request;
835 struct cqp_commands_info *cqp_info;
836 struct i40iw_modify_qp_info *m_info;
837
838 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
839 if (!cqp_request)
840 return;
841
842 cqp_info = &cqp_request->info;
843 m_info = &cqp_info->in.u.qp_modify.info;
844 memcpy(m_info, info, sizeof(*m_info));
845 cqp_info->cqp_cmd = OP_QP_MODIFY;
846 cqp_info->post_sq = 1;
847 cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
848 cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
849 status = i40iw_handle_cqp_op(iwdev, cqp_request);
850 if (status)
851 i40iw_pr_err("CQP-OP Modify QP fail");
852 }
853
854 /**
855 * i40iw_modify_qp - modify qp request
856 * @ibqp: qp's pointer for modify
857 * @attr: access attributes
858 * @attr_mask: state mask
859 * @udata: user data
860 */
861 int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
862 int attr_mask, struct ib_udata *udata)
863 {
864 struct i40iw_qp *iwqp = to_iwqp(ibqp);
865 struct i40iw_device *iwdev = iwqp->iwdev;
866 struct i40iw_qp_host_ctx_info *ctx_info;
867 struct i40iwarp_offload_info *iwarp_info;
868 struct i40iw_modify_qp_info info;
869 u8 issue_modify_qp = 0;
870 u8 dont_wait = 0;
871 u32 err;
872 unsigned long flags;
873
874 memset(&info, 0, sizeof(info));
875 ctx_info = &iwqp->ctx_info;
876 iwarp_info = &iwqp->iwarp_info;
877
878 spin_lock_irqsave(&iwqp->lock, flags);
879
880 if (attr_mask & IB_QP_STATE) {
881 if (iwdev->closing && attr->qp_state != IB_QPS_ERR) {
882 err = -EINVAL;
883 goto exit;
884 }
885
886 switch (attr->qp_state) {
887 case IB_QPS_INIT:
888 case IB_QPS_RTR:
889 if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
890 err = -EINVAL;
891 goto exit;
892 }
893 if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
894 info.next_iwarp_state = I40IW_QP_STATE_IDLE;
895 issue_modify_qp = 1;
896 }
897 break;
898 case IB_QPS_RTS:
899 if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
900 (!iwqp->cm_id)) {
901 err = -EINVAL;
902 goto exit;
903 }
904
905 issue_modify_qp = 1;
906 iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
907 iwqp->hte_added = 1;
908 info.next_iwarp_state = I40IW_QP_STATE_RTS;
909 info.tcp_ctx_valid = true;
910 info.ord_valid = true;
911 info.arp_cache_idx_valid = true;
912 info.cq_num_valid = true;
913 break;
914 case IB_QPS_SQD:
915 if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
916 err = 0;
917 goto exit;
918 }
919 if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
920 (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
921 err = 0;
922 goto exit;
923 }
924 if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
925 err = -EINVAL;
926 goto exit;
927 }
928 info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
929 issue_modify_qp = 1;
930 break;
931 case IB_QPS_SQE:
932 if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
933 err = -EINVAL;
934 goto exit;
935 }
936 info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
937 issue_modify_qp = 1;
938 break;
939 case IB_QPS_ERR:
940 case IB_QPS_RESET:
941 if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
942 err = -EINVAL;
943 goto exit;
944 }
945 if (iwqp->sc_qp.term_flags)
946 i40iw_terminate_del_timer(&iwqp->sc_qp);
947 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
948 if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
949 iwdev->iw_status &&
950 (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
951 info.reset_tcp_conn = true;
952 else
953 dont_wait = 1;
954 issue_modify_qp = 1;
955 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
956 break;
957 default:
958 err = -EINVAL;
959 goto exit;
960 }
961
962 iwqp->ibqp_state = attr->qp_state;
963
964 if (issue_modify_qp)
965 iwqp->iwarp_state = info.next_iwarp_state;
966 else
967 info.next_iwarp_state = iwqp->iwarp_state;
968 }
969 if (attr_mask & IB_QP_ACCESS_FLAGS) {
970 ctx_info->iwarp_info_valid = true;
971 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
972 iwarp_info->wr_rdresp_en = true;
973 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
974 iwarp_info->wr_rdresp_en = true;
975 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
976 iwarp_info->rd_enable = true;
977 if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
978 iwarp_info->bind_en = true;
979
980 if (iwqp->user_mode) {
981 iwarp_info->rd_enable = true;
982 iwarp_info->wr_rdresp_en = true;
983 iwarp_info->priv_mode_en = false;
984 }
985 }
986
987 if (ctx_info->iwarp_info_valid) {
988 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
989 int ret;
990
991 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
992 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
993 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
994 (u64 *)iwqp->host_ctx.va,
995 ctx_info);
996 if (ret) {
997 i40iw_pr_err("setting QP context\n");
998 err = -EINVAL;
999 goto exit;
1000 }
1001 }
1002
1003 spin_unlock_irqrestore(&iwqp->lock, flags);
1004
1005 if (issue_modify_qp)
1006 i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
1007
1008 if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
1009 if (dont_wait) {
1010 if (iwqp->cm_id && iwqp->hw_tcp_state) {
1011 spin_lock_irqsave(&iwqp->lock, flags);
1012 iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
1013 iwqp->last_aeq = I40IW_AE_RESET_SENT;
1014 spin_unlock_irqrestore(&iwqp->lock, flags);
1015 i40iw_cm_disconn(iwqp);
1016 }
1017 } else {
1018 spin_lock_irqsave(&iwqp->lock, flags);
1019 if (iwqp->cm_id) {
1020 if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
1021 iwqp->cm_id->add_ref(iwqp->cm_id);
1022 i40iw_schedule_cm_timer(iwqp->cm_node,
1023 (struct i40iw_puda_buf *)iwqp,
1024 I40IW_TIMER_TYPE_CLOSE, 1, 0);
1025 }
1026 }
1027 spin_unlock_irqrestore(&iwqp->lock, flags);
1028 }
1029 }
1030 return 0;
1031 exit:
1032 spin_unlock_irqrestore(&iwqp->lock, flags);
1033 return err;
1034 }
1035
1036 /**
1037 * cq_free_resources - free up recources for cq
1038 * @iwdev: iwarp device
1039 * @iwcq: cq ptr
1040 */
1041 static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
1042 {
1043 struct i40iw_sc_cq *cq = &iwcq->sc_cq;
1044
1045 if (!iwcq->user_mode)
1046 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
1047 i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
1048 }
1049
1050 /**
1051 * i40iw_cq_wq_destroy - send cq destroy cqp
1052 * @iwdev: iwarp device
1053 * @cq: hardware control cq
1054 */
1055 void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
1056 {
1057 enum i40iw_status_code status;
1058 struct i40iw_cqp_request *cqp_request;
1059 struct cqp_commands_info *cqp_info;
1060
1061 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1062 if (!cqp_request)
1063 return;
1064
1065 cqp_info = &cqp_request->info;
1066
1067 cqp_info->cqp_cmd = OP_CQ_DESTROY;
1068 cqp_info->post_sq = 1;
1069 cqp_info->in.u.cq_destroy.cq = cq;
1070 cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
1071 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1072 if (status)
1073 i40iw_pr_err("CQP-OP Destroy QP fail");
1074 }
1075
1076 /**
1077 * i40iw_destroy_cq - destroy cq
1078 * @ib_cq: cq pointer
1079 */
1080 static int i40iw_destroy_cq(struct ib_cq *ib_cq)
1081 {
1082 struct i40iw_cq *iwcq;
1083 struct i40iw_device *iwdev;
1084 struct i40iw_sc_cq *cq;
1085
1086 if (!ib_cq) {
1087 i40iw_pr_err("ib_cq == NULL\n");
1088 return 0;
1089 }
1090
1091 iwcq = to_iwcq(ib_cq);
1092 iwdev = to_iwdev(ib_cq->device);
1093 cq = &iwcq->sc_cq;
1094 i40iw_cq_wq_destroy(iwdev, cq);
1095 cq_free_resources(iwdev, iwcq);
1096 kfree(iwcq);
1097 i40iw_rem_devusecount(iwdev);
1098 return 0;
1099 }
1100
1101 /**
1102 * i40iw_create_cq - create cq
1103 * @ibdev: device pointer from stack
1104 * @attr: attributes for cq
1105 * @context: user context created during alloc
1106 * @udata: user data
1107 */
1108 static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
1109 const struct ib_cq_init_attr *attr,
1110 struct ib_ucontext *context,
1111 struct ib_udata *udata)
1112 {
1113 struct i40iw_device *iwdev = to_iwdev(ibdev);
1114 struct i40iw_cq *iwcq;
1115 struct i40iw_pbl *iwpbl;
1116 u32 cq_num = 0;
1117 struct i40iw_sc_cq *cq;
1118 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1119 struct i40iw_cq_init_info info;
1120 enum i40iw_status_code status;
1121 struct i40iw_cqp_request *cqp_request;
1122 struct cqp_commands_info *cqp_info;
1123 struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
1124 unsigned long flags;
1125 int err_code;
1126 int entries = attr->cqe;
1127
1128 if (iwdev->closing)
1129 return ERR_PTR(-ENODEV);
1130
1131 if (entries > iwdev->max_cqe)
1132 return ERR_PTR(-EINVAL);
1133
1134 iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL);
1135 if (!iwcq)
1136 return ERR_PTR(-ENOMEM);
1137
1138 memset(&info, 0, sizeof(info));
1139
1140 err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
1141 iwdev->max_cq, &cq_num,
1142 &iwdev->next_cq);
1143 if (err_code)
1144 goto error;
1145
1146 cq = &iwcq->sc_cq;
1147 cq->back_cq = (void *)iwcq;
1148 spin_lock_init(&iwcq->lock);
1149
1150 info.dev = dev;
1151 ukinfo->cq_size = max(entries, 4);
1152 ukinfo->cq_id = cq_num;
1153 iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
1154 info.ceqe_mask = 0;
1155 if (attr->comp_vector < iwdev->ceqs_count)
1156 info.ceq_id = attr->comp_vector;
1157 info.ceq_id_valid = true;
1158 info.ceqe_mask = 1;
1159 info.type = I40IW_CQ_TYPE_IWARP;
1160 if (context) {
1161 struct i40iw_ucontext *ucontext;
1162 struct i40iw_create_cq_req req;
1163 struct i40iw_cq_mr *cqmr;
1164
1165 memset(&req, 0, sizeof(req));
1166 iwcq->user_mode = true;
1167 ucontext = to_ucontext(context);
1168 if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req))) {
1169 err_code = -EFAULT;
1170 goto cq_free_resources;
1171 }
1172
1173 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1174 iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
1175 &ucontext->cq_reg_mem_list);
1176 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1177 if (!iwpbl) {
1178 err_code = -EPROTO;
1179 goto cq_free_resources;
1180 }
1181
1182 iwcq->iwpbl = iwpbl;
1183 iwcq->cq_mem_size = 0;
1184 cqmr = &iwpbl->cq_mr;
1185 info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
1186 if (iwpbl->pbl_allocated) {
1187 info.virtual_map = true;
1188 info.pbl_chunk_size = 1;
1189 info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
1190 } else {
1191 info.cq_base_pa = cqmr->cq_pbl.addr;
1192 }
1193 } else {
1194 /* Kmode allocations */
1195 int rsize;
1196 int shadow;
1197
1198 rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
1199 rsize = round_up(rsize, 256);
1200 shadow = I40IW_SHADOW_AREA_SIZE << 3;
1201 status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
1202 rsize + shadow, 256);
1203 if (status) {
1204 err_code = -ENOMEM;
1205 goto cq_free_resources;
1206 }
1207 ukinfo->cq_base = iwcq->kmem.va;
1208 info.cq_base_pa = iwcq->kmem.pa;
1209 info.shadow_area_pa = info.cq_base_pa + rsize;
1210 ukinfo->shadow_area = iwcq->kmem.va + rsize;
1211 }
1212
1213 if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
1214 i40iw_pr_err("init cq fail\n");
1215 err_code = -EPROTO;
1216 goto cq_free_resources;
1217 }
1218
1219 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1220 if (!cqp_request) {
1221 err_code = -ENOMEM;
1222 goto cq_free_resources;
1223 }
1224
1225 cqp_info = &cqp_request->info;
1226 cqp_info->cqp_cmd = OP_CQ_CREATE;
1227 cqp_info->post_sq = 1;
1228 cqp_info->in.u.cq_create.cq = cq;
1229 cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
1230 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1231 if (status) {
1232 i40iw_pr_err("CQP-OP Create QP fail");
1233 err_code = -EPROTO;
1234 goto cq_free_resources;
1235 }
1236
1237 if (context) {
1238 struct i40iw_create_cq_resp resp;
1239
1240 memset(&resp, 0, sizeof(resp));
1241 resp.cq_id = info.cq_uk_init_info.cq_id;
1242 resp.cq_size = info.cq_uk_init_info.cq_size;
1243 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1244 i40iw_pr_err("copy to user data\n");
1245 err_code = -EPROTO;
1246 goto cq_destroy;
1247 }
1248 }
1249
1250 i40iw_add_devusecount(iwdev);
1251 return (struct ib_cq *)iwcq;
1252
1253 cq_destroy:
1254 i40iw_cq_wq_destroy(iwdev, cq);
1255 cq_free_resources:
1256 cq_free_resources(iwdev, iwcq);
1257 error:
1258 kfree(iwcq);
1259 return ERR_PTR(err_code);
1260 }
1261
1262 /**
1263 * i40iw_get_user_access - get hw access from IB access
1264 * @acc: IB access to return hw access
1265 */
1266 static inline u16 i40iw_get_user_access(int acc)
1267 {
1268 u16 access = 0;
1269
1270 access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
1271 access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
1272 access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
1273 access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
1274 return access;
1275 }
1276
1277 /**
1278 * i40iw_free_stag - free stag resource
1279 * @iwdev: iwarp device
1280 * @stag: stag to free
1281 */
1282 static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
1283 {
1284 u32 stag_idx;
1285
1286 stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1287 i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
1288 i40iw_rem_devusecount(iwdev);
1289 }
1290
1291 /**
1292 * i40iw_create_stag - create random stag
1293 * @iwdev: iwarp device
1294 */
1295 static u32 i40iw_create_stag(struct i40iw_device *iwdev)
1296 {
1297 u32 stag = 0;
1298 u32 stag_index = 0;
1299 u32 next_stag_index;
1300 u32 driver_key;
1301 u32 random;
1302 u8 consumer_key;
1303 int ret;
1304
1305 get_random_bytes(&random, sizeof(random));
1306 consumer_key = (u8)random;
1307
1308 driver_key = random & ~iwdev->mr_stagmask;
1309 next_stag_index = (random & iwdev->mr_stagmask) >> 8;
1310 next_stag_index %= iwdev->max_mr;
1311
1312 ret = i40iw_alloc_resource(iwdev,
1313 iwdev->allocated_mrs, iwdev->max_mr,
1314 &stag_index, &next_stag_index);
1315 if (!ret) {
1316 stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
1317 stag |= driver_key;
1318 stag += (u32)consumer_key;
1319 i40iw_add_devusecount(iwdev);
1320 }
1321 return stag;
1322 }
1323
1324 /**
1325 * i40iw_next_pbl_addr - Get next pbl address
1326 * @pbl: pointer to a pble
1327 * @pinfo: info pointer
1328 * @idx: index
1329 */
1330 static inline u64 *i40iw_next_pbl_addr(u64 *pbl,
1331 struct i40iw_pble_info **pinfo,
1332 u32 *idx)
1333 {
1334 *idx += 1;
1335 if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
1336 return ++pbl;
1337 *idx = 0;
1338 (*pinfo)++;
1339 return (u64 *)(*pinfo)->addr;
1340 }
1341
1342 /**
1343 * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally
1344 * @iwmr: iwmr for IB's user page addresses
1345 * @pbl: ple pointer to save 1 level or 0 level pble
1346 * @level: indicated level 0, 1 or 2
1347 */
1348 static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
1349 u64 *pbl,
1350 enum i40iw_pble_level level)
1351 {
1352 struct ib_umem *region = iwmr->region;
1353 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1354 int chunk_pages, entry, i;
1355 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1356 struct i40iw_pble_info *pinfo;
1357 struct scatterlist *sg;
1358 u64 pg_addr = 0;
1359 u32 idx = 0;
1360
1361 pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
1362
1363 for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
1364 chunk_pages = sg_dma_len(sg) >> region->page_shift;
1365 if ((iwmr->type == IW_MEMREG_TYPE_QP) &&
1366 !iwpbl->qp_mr.sq_page)
1367 iwpbl->qp_mr.sq_page = sg_page(sg);
1368 for (i = 0; i < chunk_pages; i++) {
1369 pg_addr = sg_dma_address(sg) +
1370 (i << region->page_shift);
1371
1372 if ((entry + i) == 0)
1373 *pbl = cpu_to_le64(pg_addr & iwmr->page_msk);
1374 else if (!(pg_addr & ~iwmr->page_msk))
1375 *pbl = cpu_to_le64(pg_addr);
1376 else
1377 continue;
1378 pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx);
1379 }
1380 }
1381 }
1382
1383 /**
1384 * i40iw_set_hugetlb_params - set MR pg size and mask to huge pg values.
1385 * @addr: virtual address
1386 * @iwmr: mr pointer for this memory registration
1387 */
1388 static void i40iw_set_hugetlb_values(u64 addr, struct i40iw_mr *iwmr)
1389 {
1390 struct vm_area_struct *vma;
1391 struct hstate *h;
1392
1393 vma = find_vma(current->mm, addr);
1394 if (vma && is_vm_hugetlb_page(vma)) {
1395 h = hstate_vma(vma);
1396 if (huge_page_size(h) == 0x200000) {
1397 iwmr->page_size = huge_page_size(h);
1398 iwmr->page_msk = huge_page_mask(h);
1399 }
1400 }
1401 }
1402
1403 /**
1404 * i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous
1405 * @arr: lvl1 pbl array
1406 * @npages: page count
1407 * pg_size: page size
1408 *
1409 */
1410 static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
1411 {
1412 u32 pg_idx;
1413
1414 for (pg_idx = 0; pg_idx < npages; pg_idx++) {
1415 if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
1416 return false;
1417 }
1418 return true;
1419 }
1420
1421 /**
1422 * i40iw_check_mr_contiguous - check if MR is physically contiguous
1423 * @palloc: pbl allocation struct
1424 * pg_size: page size
1425 */
1426 static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size)
1427 {
1428 struct i40iw_pble_level2 *lvl2 = &palloc->level2;
1429 struct i40iw_pble_info *leaf = lvl2->leaf;
1430 u64 *arr = NULL;
1431 u64 *start_addr = NULL;
1432 int i;
1433 bool ret;
1434
1435 if (palloc->level == I40IW_LEVEL_1) {
1436 arr = (u64 *)palloc->level1.addr;
1437 ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size);
1438 return ret;
1439 }
1440
1441 start_addr = (u64 *)leaf->addr;
1442
1443 for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
1444 arr = (u64 *)leaf->addr;
1445 if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
1446 return false;
1447 ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size);
1448 if (!ret)
1449 return false;
1450 }
1451
1452 return true;
1453 }
1454
1455 /**
1456 * i40iw_setup_pbles - copy user pg address to pble's
1457 * @iwdev: iwarp device
1458 * @iwmr: mr pointer for this memory registration
1459 * @use_pbles: flag if to use pble's
1460 */
1461 static int i40iw_setup_pbles(struct i40iw_device *iwdev,
1462 struct i40iw_mr *iwmr,
1463 bool use_pbles)
1464 {
1465 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1466 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1467 struct i40iw_pble_info *pinfo;
1468 u64 *pbl;
1469 enum i40iw_status_code status;
1470 enum i40iw_pble_level level = I40IW_LEVEL_1;
1471
1472 if (use_pbles) {
1473 mutex_lock(&iwdev->pbl_mutex);
1474 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
1475 mutex_unlock(&iwdev->pbl_mutex);
1476 if (status)
1477 return -ENOMEM;
1478
1479 iwpbl->pbl_allocated = true;
1480 level = palloc->level;
1481 pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
1482 pbl = (u64 *)pinfo->addr;
1483 } else {
1484 pbl = iwmr->pgaddrmem;
1485 }
1486
1487 i40iw_copy_user_pgaddrs(iwmr, pbl, level);
1488
1489 if (use_pbles)
1490 iwmr->pgaddrmem[0] = *pbl;
1491
1492 return 0;
1493 }
1494
1495 /**
1496 * i40iw_handle_q_mem - handle memory for qp and cq
1497 * @iwdev: iwarp device
1498 * @req: information for q memory management
1499 * @iwpbl: pble struct
1500 * @use_pbles: flag to use pble
1501 */
1502 static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
1503 struct i40iw_mem_reg_req *req,
1504 struct i40iw_pbl *iwpbl,
1505 bool use_pbles)
1506 {
1507 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1508 struct i40iw_mr *iwmr = iwpbl->iwmr;
1509 struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
1510 struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
1511 struct i40iw_hmc_pble *hmc_p;
1512 u64 *arr = iwmr->pgaddrmem;
1513 u32 pg_size;
1514 int err;
1515 int total;
1516 bool ret = true;
1517
1518 total = req->sq_pages + req->rq_pages + req->cq_pages;
1519 pg_size = iwmr->page_size;
1520
1521 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1522 if (err)
1523 return err;
1524
1525 if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
1526 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1527 iwpbl->pbl_allocated = false;
1528 return -ENOMEM;
1529 }
1530
1531 if (use_pbles)
1532 arr = (u64 *)palloc->level1.addr;
1533
1534 if (iwmr->type == IW_MEMREG_TYPE_QP) {
1535 hmc_p = &qpmr->sq_pbl;
1536 qpmr->shadow = (dma_addr_t)arr[total];
1537
1538 if (use_pbles) {
1539 ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size);
1540 if (ret)
1541 ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size);
1542 }
1543
1544 if (!ret) {
1545 hmc_p->idx = palloc->level1.idx;
1546 hmc_p = &qpmr->rq_pbl;
1547 hmc_p->idx = palloc->level1.idx + req->sq_pages;
1548 } else {
1549 hmc_p->addr = arr[0];
1550 hmc_p = &qpmr->rq_pbl;
1551 hmc_p->addr = arr[req->sq_pages];
1552 }
1553 } else { /* CQ */
1554 hmc_p = &cqmr->cq_pbl;
1555 cqmr->shadow = (dma_addr_t)arr[total];
1556
1557 if (use_pbles)
1558 ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size);
1559
1560 if (!ret)
1561 hmc_p->idx = palloc->level1.idx;
1562 else
1563 hmc_p->addr = arr[0];
1564 }
1565
1566 if (use_pbles && ret) {
1567 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1568 iwpbl->pbl_allocated = false;
1569 }
1570
1571 return err;
1572 }
1573
1574 /**
1575 * i40iw_hw_alloc_stag - cqp command to allocate stag
1576 * @iwdev: iwarp device
1577 * @iwmr: iwarp mr pointer
1578 */
1579 static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr)
1580 {
1581 struct i40iw_allocate_stag_info *info;
1582 struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1583 enum i40iw_status_code status;
1584 int err = 0;
1585 struct i40iw_cqp_request *cqp_request;
1586 struct cqp_commands_info *cqp_info;
1587
1588 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1589 if (!cqp_request)
1590 return -ENOMEM;
1591
1592 cqp_info = &cqp_request->info;
1593 info = &cqp_info->in.u.alloc_stag.info;
1594 memset(info, 0, sizeof(*info));
1595 info->page_size = PAGE_SIZE;
1596 info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1597 info->pd_id = iwpd->sc_pd.pd_id;
1598 info->total_len = iwmr->length;
1599 info->remote_access = true;
1600 cqp_info->cqp_cmd = OP_ALLOC_STAG;
1601 cqp_info->post_sq = 1;
1602 cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev;
1603 cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
1604
1605 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1606 if (status) {
1607 err = -ENOMEM;
1608 i40iw_pr_err("CQP-OP MR Reg fail");
1609 }
1610 return err;
1611 }
1612
1613 /**
1614 * i40iw_alloc_mr - register stag for fast memory registration
1615 * @pd: ibpd pointer
1616 * @mr_type: memory for stag registrion
1617 * @max_num_sg: man number of pages
1618 */
1619 static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd,
1620 enum ib_mr_type mr_type,
1621 u32 max_num_sg)
1622 {
1623 struct i40iw_pd *iwpd = to_iwpd(pd);
1624 struct i40iw_device *iwdev = to_iwdev(pd->device);
1625 struct i40iw_pble_alloc *palloc;
1626 struct i40iw_pbl *iwpbl;
1627 struct i40iw_mr *iwmr;
1628 enum i40iw_status_code status;
1629 u32 stag;
1630 int err_code = -ENOMEM;
1631
1632 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1633 if (!iwmr)
1634 return ERR_PTR(-ENOMEM);
1635
1636 stag = i40iw_create_stag(iwdev);
1637 if (!stag) {
1638 err_code = -EOVERFLOW;
1639 goto err;
1640 }
1641 stag &= ~I40IW_CQPSQ_STAG_KEY_MASK;
1642 iwmr->stag = stag;
1643 iwmr->ibmr.rkey = stag;
1644 iwmr->ibmr.lkey = stag;
1645 iwmr->ibmr.pd = pd;
1646 iwmr->ibmr.device = pd->device;
1647 iwpbl = &iwmr->iwpbl;
1648 iwpbl->iwmr = iwmr;
1649 iwmr->type = IW_MEMREG_TYPE_MEM;
1650 palloc = &iwpbl->pble_alloc;
1651 iwmr->page_cnt = max_num_sg;
1652 mutex_lock(&iwdev->pbl_mutex);
1653 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
1654 mutex_unlock(&iwdev->pbl_mutex);
1655 if (status)
1656 goto err1;
1657
1658 if (palloc->level != I40IW_LEVEL_1)
1659 goto err2;
1660 err_code = i40iw_hw_alloc_stag(iwdev, iwmr);
1661 if (err_code)
1662 goto err2;
1663 iwpbl->pbl_allocated = true;
1664 i40iw_add_pdusecount(iwpd);
1665 return &iwmr->ibmr;
1666 err2:
1667 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1668 err1:
1669 i40iw_free_stag(iwdev, stag);
1670 err:
1671 kfree(iwmr);
1672 return ERR_PTR(err_code);
1673 }
1674
1675 /**
1676 * i40iw_set_page - populate pbl list for fmr
1677 * @ibmr: ib mem to access iwarp mr pointer
1678 * @addr: page dma address fro pbl list
1679 */
1680 static int i40iw_set_page(struct ib_mr *ibmr, u64 addr)
1681 {
1682 struct i40iw_mr *iwmr = to_iwmr(ibmr);
1683 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1684 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1685 u64 *pbl;
1686
1687 if (unlikely(iwmr->npages == iwmr->page_cnt))
1688 return -ENOMEM;
1689
1690 pbl = (u64 *)palloc->level1.addr;
1691 pbl[iwmr->npages++] = cpu_to_le64(addr);
1692 return 0;
1693 }
1694
1695 /**
1696 * i40iw_map_mr_sg - map of sg list for fmr
1697 * @ibmr: ib mem to access iwarp mr pointer
1698 * @sg: scatter gather list for fmr
1699 * @sg_nents: number of sg pages
1700 */
1701 static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
1702 int sg_nents, unsigned int *sg_offset)
1703 {
1704 struct i40iw_mr *iwmr = to_iwmr(ibmr);
1705
1706 iwmr->npages = 0;
1707 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page);
1708 }
1709
1710 /**
1711 * i40iw_drain_sq - drain the send queue
1712 * @ibqp: ib qp pointer
1713 */
1714 static void i40iw_drain_sq(struct ib_qp *ibqp)
1715 {
1716 struct i40iw_qp *iwqp = to_iwqp(ibqp);
1717 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
1718
1719 if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
1720 wait_for_completion(&iwqp->sq_drained);
1721 }
1722
1723 /**
1724 * i40iw_drain_rq - drain the receive queue
1725 * @ibqp: ib qp pointer
1726 */
1727 static void i40iw_drain_rq(struct ib_qp *ibqp)
1728 {
1729 struct i40iw_qp *iwqp = to_iwqp(ibqp);
1730 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
1731
1732 if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
1733 wait_for_completion(&iwqp->rq_drained);
1734 }
1735
1736 /**
1737 * i40iw_hwreg_mr - send cqp command for memory registration
1738 * @iwdev: iwarp device
1739 * @iwmr: iwarp mr pointer
1740 * @access: access for MR
1741 */
1742 static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
1743 struct i40iw_mr *iwmr,
1744 u16 access)
1745 {
1746 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1747 struct i40iw_reg_ns_stag_info *stag_info;
1748 struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1749 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1750 enum i40iw_status_code status;
1751 int err = 0;
1752 struct i40iw_cqp_request *cqp_request;
1753 struct cqp_commands_info *cqp_info;
1754
1755 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1756 if (!cqp_request)
1757 return -ENOMEM;
1758
1759 cqp_info = &cqp_request->info;
1760 stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
1761 memset(stag_info, 0, sizeof(*stag_info));
1762 stag_info->va = (void *)(unsigned long)iwpbl->user_base;
1763 stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1764 stag_info->stag_key = (u8)iwmr->stag;
1765 stag_info->total_len = iwmr->length;
1766 stag_info->access_rights = access;
1767 stag_info->pd_id = iwpd->sc_pd.pd_id;
1768 stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
1769 stag_info->page_size = iwmr->page_size;
1770
1771 if (iwpbl->pbl_allocated) {
1772 if (palloc->level == I40IW_LEVEL_1) {
1773 stag_info->first_pm_pbl_index = palloc->level1.idx;
1774 stag_info->chunk_size = 1;
1775 } else {
1776 stag_info->first_pm_pbl_index = palloc->level2.root.idx;
1777 stag_info->chunk_size = 3;
1778 }
1779 } else {
1780 stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
1781 }
1782
1783 cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
1784 cqp_info->post_sq = 1;
1785 cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
1786 cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
1787
1788 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1789 if (status) {
1790 err = -ENOMEM;
1791 i40iw_pr_err("CQP-OP MR Reg fail");
1792 }
1793 return err;
1794 }
1795
1796 /**
1797 * i40iw_reg_user_mr - Register a user memory region
1798 * @pd: ptr of pd
1799 * @start: virtual start address
1800 * @length: length of mr
1801 * @virt: virtual address
1802 * @acc: access of mr
1803 * @udata: user data
1804 */
1805 static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1806 u64 start,
1807 u64 length,
1808 u64 virt,
1809 int acc,
1810 struct ib_udata *udata)
1811 {
1812 struct i40iw_pd *iwpd = to_iwpd(pd);
1813 struct i40iw_device *iwdev = to_iwdev(pd->device);
1814 struct i40iw_ucontext *ucontext;
1815 struct i40iw_pble_alloc *palloc;
1816 struct i40iw_pbl *iwpbl;
1817 struct i40iw_mr *iwmr;
1818 struct ib_umem *region;
1819 struct i40iw_mem_reg_req req;
1820 u64 pbl_depth = 0;
1821 u32 stag = 0;
1822 u16 access;
1823 u64 region_length;
1824 bool use_pbles = false;
1825 unsigned long flags;
1826 int err = -ENOSYS;
1827 int ret;
1828 int pg_shift;
1829
1830 if (iwdev->closing)
1831 return ERR_PTR(-ENODEV);
1832
1833 if (length > I40IW_MAX_MR_SIZE)
1834 return ERR_PTR(-EINVAL);
1835 region = ib_umem_get(pd->uobject->context, start, length, acc, 0);
1836 if (IS_ERR(region))
1837 return (struct ib_mr *)region;
1838
1839 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
1840 ib_umem_release(region);
1841 return ERR_PTR(-EFAULT);
1842 }
1843
1844 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1845 if (!iwmr) {
1846 ib_umem_release(region);
1847 return ERR_PTR(-ENOMEM);
1848 }
1849
1850 iwpbl = &iwmr->iwpbl;
1851 iwpbl->iwmr = iwmr;
1852 iwmr->region = region;
1853 iwmr->ibmr.pd = pd;
1854 iwmr->ibmr.device = pd->device;
1855 ucontext = to_ucontext(pd->uobject->context);
1856
1857 iwmr->page_size = PAGE_SIZE;
1858 iwmr->page_msk = PAGE_MASK;
1859
1860 if (region->hugetlb && (req.reg_type == IW_MEMREG_TYPE_MEM))
1861 i40iw_set_hugetlb_values(start, iwmr);
1862
1863 region_length = region->length + (start & (iwmr->page_size - 1));
1864 pg_shift = ffs(iwmr->page_size) - 1;
1865 pbl_depth = region_length >> pg_shift;
1866 pbl_depth += (region_length & (iwmr->page_size - 1)) ? 1 : 0;
1867 iwmr->length = region->length;
1868
1869 iwpbl->user_base = virt;
1870 palloc = &iwpbl->pble_alloc;
1871
1872 iwmr->type = req.reg_type;
1873 iwmr->page_cnt = (u32)pbl_depth;
1874
1875 switch (req.reg_type) {
1876 case IW_MEMREG_TYPE_QP:
1877 use_pbles = ((req.sq_pages + req.rq_pages) > 2);
1878 err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
1879 if (err)
1880 goto error;
1881 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
1882 list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
1883 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
1884 break;
1885 case IW_MEMREG_TYPE_CQ:
1886 use_pbles = (req.cq_pages > 1);
1887 err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
1888 if (err)
1889 goto error;
1890
1891 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1892 list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
1893 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1894 break;
1895 case IW_MEMREG_TYPE_MEM:
1896 use_pbles = (iwmr->page_cnt != 1);
1897 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1898
1899 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1900 if (err)
1901 goto error;
1902
1903 if (use_pbles) {
1904 ret = i40iw_check_mr_contiguous(palloc, iwmr->page_size);
1905 if (ret) {
1906 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1907 iwpbl->pbl_allocated = false;
1908 }
1909 }
1910
1911 access |= i40iw_get_user_access(acc);
1912 stag = i40iw_create_stag(iwdev);
1913 if (!stag) {
1914 err = -ENOMEM;
1915 goto error;
1916 }
1917
1918 iwmr->stag = stag;
1919 iwmr->ibmr.rkey = stag;
1920 iwmr->ibmr.lkey = stag;
1921
1922 err = i40iw_hwreg_mr(iwdev, iwmr, access);
1923 if (err) {
1924 i40iw_free_stag(iwdev, stag);
1925 goto error;
1926 }
1927
1928 break;
1929 default:
1930 goto error;
1931 }
1932
1933 iwmr->type = req.reg_type;
1934 if (req.reg_type == IW_MEMREG_TYPE_MEM)
1935 i40iw_add_pdusecount(iwpd);
1936 return &iwmr->ibmr;
1937
1938 error:
1939 if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated)
1940 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1941 ib_umem_release(region);
1942 kfree(iwmr);
1943 return ERR_PTR(err);
1944 }
1945
1946 /**
1947 * i40iw_reg_phys_mr - register kernel physical memory
1948 * @pd: ibpd pointer
1949 * @addr: physical address of memory to register
1950 * @size: size of memory to register
1951 * @acc: Access rights
1952 * @iova_start: start of virtual address for physical buffers
1953 */
1954 struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
1955 u64 addr,
1956 u64 size,
1957 int acc,
1958 u64 *iova_start)
1959 {
1960 struct i40iw_pd *iwpd = to_iwpd(pd);
1961 struct i40iw_device *iwdev = to_iwdev(pd->device);
1962 struct i40iw_pbl *iwpbl;
1963 struct i40iw_mr *iwmr;
1964 enum i40iw_status_code status;
1965 u32 stag;
1966 u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1967 int ret;
1968
1969 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1970 if (!iwmr)
1971 return ERR_PTR(-ENOMEM);
1972 iwmr->ibmr.pd = pd;
1973 iwmr->ibmr.device = pd->device;
1974 iwpbl = &iwmr->iwpbl;
1975 iwpbl->iwmr = iwmr;
1976 iwmr->type = IW_MEMREG_TYPE_MEM;
1977 iwpbl->user_base = *iova_start;
1978 stag = i40iw_create_stag(iwdev);
1979 if (!stag) {
1980 ret = -EOVERFLOW;
1981 goto err;
1982 }
1983 access |= i40iw_get_user_access(acc);
1984 iwmr->stag = stag;
1985 iwmr->ibmr.rkey = stag;
1986 iwmr->ibmr.lkey = stag;
1987 iwmr->page_cnt = 1;
1988 iwmr->pgaddrmem[0] = addr;
1989 iwmr->length = size;
1990 status = i40iw_hwreg_mr(iwdev, iwmr, access);
1991 if (status) {
1992 i40iw_free_stag(iwdev, stag);
1993 ret = -ENOMEM;
1994 goto err;
1995 }
1996
1997 i40iw_add_pdusecount(iwpd);
1998 return &iwmr->ibmr;
1999 err:
2000 kfree(iwmr);
2001 return ERR_PTR(ret);
2002 }
2003
2004 /**
2005 * i40iw_get_dma_mr - register physical mem
2006 * @pd: ptr of pd
2007 * @acc: access for memory
2008 */
2009 static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
2010 {
2011 u64 kva = 0;
2012
2013 return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva);
2014 }
2015
2016 /**
2017 * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP
2018 * @iwmr: iwmr for IB's user page addresses
2019 * @ucontext: ptr to user context
2020 */
2021 static void i40iw_del_memlist(struct i40iw_mr *iwmr,
2022 struct i40iw_ucontext *ucontext)
2023 {
2024 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
2025 unsigned long flags;
2026
2027 switch (iwmr->type) {
2028 case IW_MEMREG_TYPE_CQ:
2029 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
2030 if (!list_empty(&ucontext->cq_reg_mem_list))
2031 list_del(&iwpbl->list);
2032 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
2033 break;
2034 case IW_MEMREG_TYPE_QP:
2035 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
2036 if (!list_empty(&ucontext->qp_reg_mem_list))
2037 list_del(&iwpbl->list);
2038 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
2039 break;
2040 default:
2041 break;
2042 }
2043 }
2044
2045 /**
2046 * i40iw_dereg_mr - deregister mr
2047 * @ib_mr: mr ptr for dereg
2048 */
2049 static int i40iw_dereg_mr(struct ib_mr *ib_mr)
2050 {
2051 struct ib_pd *ibpd = ib_mr->pd;
2052 struct i40iw_pd *iwpd = to_iwpd(ibpd);
2053 struct i40iw_mr *iwmr = to_iwmr(ib_mr);
2054 struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
2055 enum i40iw_status_code status;
2056 struct i40iw_dealloc_stag_info *info;
2057 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
2058 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
2059 struct i40iw_cqp_request *cqp_request;
2060 struct cqp_commands_info *cqp_info;
2061 u32 stag_idx;
2062
2063 if (iwmr->region)
2064 ib_umem_release(iwmr->region);
2065
2066 if (iwmr->type != IW_MEMREG_TYPE_MEM) {
2067 if (ibpd->uobject) {
2068 struct i40iw_ucontext *ucontext;
2069
2070 ucontext = to_ucontext(ibpd->uobject->context);
2071 i40iw_del_memlist(iwmr, ucontext);
2072 }
2073 if (iwpbl->pbl_allocated && iwmr->type != IW_MEMREG_TYPE_QP)
2074 i40iw_free_pble(iwdev->pble_rsrc, palloc);
2075 kfree(iwmr);
2076 return 0;
2077 }
2078
2079 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
2080 if (!cqp_request)
2081 return -ENOMEM;
2082
2083 cqp_info = &cqp_request->info;
2084 info = &cqp_info->in.u.dealloc_stag.info;
2085 memset(info, 0, sizeof(*info));
2086
2087 info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
2088 info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
2089 stag_idx = info->stag_idx;
2090 info->mr = true;
2091 if (iwpbl->pbl_allocated)
2092 info->dealloc_pbl = true;
2093
2094 cqp_info->cqp_cmd = OP_DEALLOC_STAG;
2095 cqp_info->post_sq = 1;
2096 cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
2097 cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
2098 status = i40iw_handle_cqp_op(iwdev, cqp_request);
2099 if (status)
2100 i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
2101 i40iw_rem_pdusecount(iwpd, iwdev);
2102 i40iw_free_stag(iwdev, iwmr->stag);
2103 if (iwpbl->pbl_allocated)
2104 i40iw_free_pble(iwdev->pble_rsrc, palloc);
2105 kfree(iwmr);
2106 return 0;
2107 }
2108
2109 /**
2110 * i40iw_show_rev
2111 */
2112 static ssize_t i40iw_show_rev(struct device *dev,
2113 struct device_attribute *attr, char *buf)
2114 {
2115 struct i40iw_ib_device *iwibdev = container_of(dev,
2116 struct i40iw_ib_device,
2117 ibdev.dev);
2118 u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
2119
2120 return sprintf(buf, "%x\n", hw_rev);
2121 }
2122
2123 /**
2124 * i40iw_show_hca
2125 */
2126 static ssize_t i40iw_show_hca(struct device *dev,
2127 struct device_attribute *attr, char *buf)
2128 {
2129 return sprintf(buf, "I40IW\n");
2130 }
2131
2132 /**
2133 * i40iw_show_board
2134 */
2135 static ssize_t i40iw_show_board(struct device *dev,
2136 struct device_attribute *attr,
2137 char *buf)
2138 {
2139 return sprintf(buf, "%.*s\n", 32, "I40IW Board ID");
2140 }
2141
2142 static DEVICE_ATTR(hw_rev, S_IRUGO, i40iw_show_rev, NULL);
2143 static DEVICE_ATTR(hca_type, S_IRUGO, i40iw_show_hca, NULL);
2144 static DEVICE_ATTR(board_id, S_IRUGO, i40iw_show_board, NULL);
2145
2146 static struct device_attribute *i40iw_dev_attributes[] = {
2147 &dev_attr_hw_rev,
2148 &dev_attr_hca_type,
2149 &dev_attr_board_id
2150 };
2151
2152 /**
2153 * i40iw_copy_sg_list - copy sg list for qp
2154 * @sg_list: copied into sg_list
2155 * @sgl: copy from sgl
2156 * @num_sges: count of sg entries
2157 */
2158 static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
2159 {
2160 unsigned int i;
2161
2162 for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
2163 sg_list[i].tag_off = sgl[i].addr;
2164 sg_list[i].len = sgl[i].length;
2165 sg_list[i].stag = sgl[i].lkey;
2166 }
2167 }
2168
2169 /**
2170 * i40iw_post_send - kernel application wr
2171 * @ibqp: qp ptr for wr
2172 * @ib_wr: work request ptr
2173 * @bad_wr: return of bad wr if err
2174 */
2175 static int i40iw_post_send(struct ib_qp *ibqp,
2176 struct ib_send_wr *ib_wr,
2177 struct ib_send_wr **bad_wr)
2178 {
2179 struct i40iw_qp *iwqp;
2180 struct i40iw_qp_uk *ukqp;
2181 struct i40iw_post_sq_info info;
2182 enum i40iw_status_code ret;
2183 int err = 0;
2184 unsigned long flags;
2185 bool inv_stag;
2186
2187 iwqp = (struct i40iw_qp *)ibqp;
2188 ukqp = &iwqp->sc_qp.qp_uk;
2189
2190 spin_lock_irqsave(&iwqp->lock, flags);
2191
2192 if (iwqp->flush_issued) {
2193 err = -EINVAL;
2194 goto out;
2195 }
2196
2197 while (ib_wr) {
2198 inv_stag = false;
2199 memset(&info, 0, sizeof(info));
2200 info.wr_id = (u64)(ib_wr->wr_id);
2201 if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
2202 info.signaled = true;
2203 if (ib_wr->send_flags & IB_SEND_FENCE)
2204 info.read_fence = true;
2205
2206 switch (ib_wr->opcode) {
2207 case IB_WR_SEND:
2208 /* fall-through */
2209 case IB_WR_SEND_WITH_INV:
2210 if (ib_wr->opcode == IB_WR_SEND) {
2211 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2212 info.op_type = I40IW_OP_TYPE_SEND_SOL;
2213 else
2214 info.op_type = I40IW_OP_TYPE_SEND;
2215 } else {
2216 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2217 info.op_type = I40IW_OP_TYPE_SEND_SOL_INV;
2218 else
2219 info.op_type = I40IW_OP_TYPE_SEND_INV;
2220 }
2221
2222 if (ib_wr->send_flags & IB_SEND_INLINE) {
2223 info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
2224 info.op.inline_send.len = ib_wr->sg_list[0].length;
2225 ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
2226 } else {
2227 info.op.send.num_sges = ib_wr->num_sge;
2228 info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
2229 ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
2230 }
2231
2232 if (ret) {
2233 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2234 err = -ENOMEM;
2235 else
2236 err = -EINVAL;
2237 }
2238 break;
2239 case IB_WR_RDMA_WRITE:
2240 info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
2241
2242 if (ib_wr->send_flags & IB_SEND_INLINE) {
2243 info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
2244 info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
2245 info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2246 info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2247 ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
2248 } else {
2249 info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
2250 info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
2251 info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2252 info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2253 ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
2254 }
2255
2256 if (ret) {
2257 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2258 err = -ENOMEM;
2259 else
2260 err = -EINVAL;
2261 }
2262 break;
2263 case IB_WR_RDMA_READ_WITH_INV:
2264 inv_stag = true;
2265 /* fall-through*/
2266 case IB_WR_RDMA_READ:
2267 if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
2268 err = -EINVAL;
2269 break;
2270 }
2271 info.op_type = I40IW_OP_TYPE_RDMA_READ;
2272 info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2273 info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2274 info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
2275 info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
2276 info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
2277 ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false);
2278 if (ret) {
2279 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2280 err = -ENOMEM;
2281 else
2282 err = -EINVAL;
2283 }
2284 break;
2285 case IB_WR_LOCAL_INV:
2286 info.op_type = I40IW_OP_TYPE_INV_STAG;
2287 info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
2288 ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true);
2289 if (ret)
2290 err = -ENOMEM;
2291 break;
2292 case IB_WR_REG_MR:
2293 {
2294 struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
2295 int flags = reg_wr(ib_wr)->access;
2296 struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
2297 struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
2298 struct i40iw_fast_reg_stag_info info;
2299
2300 memset(&info, 0, sizeof(info));
2301 info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD;
2302 info.access_rights |= i40iw_get_user_access(flags);
2303 info.stag_key = reg_wr(ib_wr)->key & 0xff;
2304 info.stag_idx = reg_wr(ib_wr)->key >> 8;
2305 info.page_size = reg_wr(ib_wr)->mr->page_size;
2306 info.wr_id = ib_wr->wr_id;
2307
2308 info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
2309 info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
2310 info.total_len = iwmr->ibmr.length;
2311 info.reg_addr_pa = *(u64 *)palloc->level1.addr;
2312 info.first_pm_pbl_index = palloc->level1.idx;
2313 info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
2314 info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED;
2315
2316 if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
2317 info.chunk_size = 1;
2318
2319 ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
2320 if (ret)
2321 err = -ENOMEM;
2322 break;
2323 }
2324 default:
2325 err = -EINVAL;
2326 i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
2327 ib_wr->opcode);
2328 break;
2329 }
2330
2331 if (err)
2332 break;
2333 ib_wr = ib_wr->next;
2334 }
2335
2336 out:
2337 if (err)
2338 *bad_wr = ib_wr;
2339 else
2340 ukqp->ops.iw_qp_post_wr(ukqp);
2341 spin_unlock_irqrestore(&iwqp->lock, flags);
2342
2343 return err;
2344 }
2345
2346 /**
2347 * i40iw_post_recv - post receive wr for kernel application
2348 * @ibqp: ib qp pointer
2349 * @ib_wr: work request for receive
2350 * @bad_wr: bad wr caused an error
2351 */
2352 static int i40iw_post_recv(struct ib_qp *ibqp,
2353 struct ib_recv_wr *ib_wr,
2354 struct ib_recv_wr **bad_wr)
2355 {
2356 struct i40iw_qp *iwqp;
2357 struct i40iw_qp_uk *ukqp;
2358 struct i40iw_post_rq_info post_recv;
2359 struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
2360 enum i40iw_status_code ret = 0;
2361 unsigned long flags;
2362 int err = 0;
2363
2364 iwqp = (struct i40iw_qp *)ibqp;
2365 ukqp = &iwqp->sc_qp.qp_uk;
2366
2367 memset(&post_recv, 0, sizeof(post_recv));
2368 spin_lock_irqsave(&iwqp->lock, flags);
2369
2370 if (iwqp->flush_issued) {
2371 err = -EINVAL;
2372 goto out;
2373 }
2374
2375 while (ib_wr) {
2376 post_recv.num_sges = ib_wr->num_sge;
2377 post_recv.wr_id = ib_wr->wr_id;
2378 i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
2379 post_recv.sg_list = sg_list;
2380 ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
2381 if (ret) {
2382 i40iw_pr_err(" post_recv err %d\n", ret);
2383 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2384 err = -ENOMEM;
2385 else
2386 err = -EINVAL;
2387 *bad_wr = ib_wr;
2388 goto out;
2389 }
2390 ib_wr = ib_wr->next;
2391 }
2392 out:
2393 spin_unlock_irqrestore(&iwqp->lock, flags);
2394 return err;
2395 }
2396
2397 /**
2398 * i40iw_poll_cq - poll cq for completion (kernel apps)
2399 * @ibcq: cq to poll
2400 * @num_entries: number of entries to poll
2401 * @entry: wr of entry completed
2402 */
2403 static int i40iw_poll_cq(struct ib_cq *ibcq,
2404 int num_entries,
2405 struct ib_wc *entry)
2406 {
2407 struct i40iw_cq *iwcq;
2408 int cqe_count = 0;
2409 struct i40iw_cq_poll_info cq_poll_info;
2410 enum i40iw_status_code ret;
2411 struct i40iw_cq_uk *ukcq;
2412 struct i40iw_sc_qp *qp;
2413 struct i40iw_qp *iwqp;
2414 unsigned long flags;
2415
2416 iwcq = (struct i40iw_cq *)ibcq;
2417 ukcq = &iwcq->sc_cq.cq_uk;
2418
2419 spin_lock_irqsave(&iwcq->lock, flags);
2420 while (cqe_count < num_entries) {
2421 ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info);
2422 if (ret == I40IW_ERR_QUEUE_EMPTY) {
2423 break;
2424 } else if (ret == I40IW_ERR_QUEUE_DESTROYED) {
2425 continue;
2426 } else if (ret) {
2427 if (!cqe_count)
2428 cqe_count = -1;
2429 break;
2430 }
2431 entry->wc_flags = 0;
2432 entry->wr_id = cq_poll_info.wr_id;
2433 if (cq_poll_info.error) {
2434 entry->status = IB_WC_WR_FLUSH_ERR;
2435 entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
2436 } else {
2437 entry->status = IB_WC_SUCCESS;
2438 }
2439
2440 switch (cq_poll_info.op_type) {
2441 case I40IW_OP_TYPE_RDMA_WRITE:
2442 entry->opcode = IB_WC_RDMA_WRITE;
2443 break;
2444 case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
2445 case I40IW_OP_TYPE_RDMA_READ:
2446 entry->opcode = IB_WC_RDMA_READ;
2447 break;
2448 case I40IW_OP_TYPE_SEND_SOL:
2449 case I40IW_OP_TYPE_SEND_SOL_INV:
2450 case I40IW_OP_TYPE_SEND_INV:
2451 case I40IW_OP_TYPE_SEND:
2452 entry->opcode = IB_WC_SEND;
2453 break;
2454 case I40IW_OP_TYPE_REC:
2455 entry->opcode = IB_WC_RECV;
2456 break;
2457 default:
2458 entry->opcode = IB_WC_RECV;
2459 break;
2460 }
2461
2462 entry->ex.imm_data = 0;
2463 qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
2464 entry->qp = (struct ib_qp *)qp->back_qp;
2465 entry->src_qp = cq_poll_info.qp_id;
2466 iwqp = (struct i40iw_qp *)qp->back_qp;
2467 if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) {
2468 if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
2469 complete(&iwqp->sq_drained);
2470 if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
2471 complete(&iwqp->rq_drained);
2472 }
2473 entry->byte_len = cq_poll_info.bytes_xfered;
2474 entry++;
2475 cqe_count++;
2476 }
2477 spin_unlock_irqrestore(&iwcq->lock, flags);
2478 return cqe_count;
2479 }
2480
2481 /**
2482 * i40iw_req_notify_cq - arm cq kernel application
2483 * @ibcq: cq to arm
2484 * @notify_flags: notofication flags
2485 */
2486 static int i40iw_req_notify_cq(struct ib_cq *ibcq,
2487 enum ib_cq_notify_flags notify_flags)
2488 {
2489 struct i40iw_cq *iwcq;
2490 struct i40iw_cq_uk *ukcq;
2491 unsigned long flags;
2492 enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT;
2493
2494 iwcq = (struct i40iw_cq *)ibcq;
2495 ukcq = &iwcq->sc_cq.cq_uk;
2496 if (notify_flags == IB_CQ_SOLICITED)
2497 cq_notify = IW_CQ_COMPL_SOLICITED;
2498 spin_lock_irqsave(&iwcq->lock, flags);
2499 ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
2500 spin_unlock_irqrestore(&iwcq->lock, flags);
2501 return 0;
2502 }
2503
2504 /**
2505 * i40iw_port_immutable - return port's immutable data
2506 * @ibdev: ib dev struct
2507 * @port_num: port number
2508 * @immutable: immutable data for the port return
2509 */
2510 static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
2511 struct ib_port_immutable *immutable)
2512 {
2513 struct ib_port_attr attr;
2514 int err;
2515
2516 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
2517
2518 err = ib_query_port(ibdev, port_num, &attr);
2519
2520 if (err)
2521 return err;
2522
2523 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2524 immutable->gid_tbl_len = attr.gid_tbl_len;
2525
2526 return 0;
2527 }
2528
2529 static const char * const i40iw_hw_stat_names[] = {
2530 // 32bit names
2531 [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards",
2532 [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts",
2533 [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes",
2534 [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards",
2535 [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts",
2536 [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes",
2537 [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs",
2538 [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors",
2539 [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors",
2540 // 64bit names
2541 [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2542 "ip4InOctets",
2543 [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2544 "ip4InPkts",
2545 [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2546 "ip4InReasmRqd",
2547 [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2548 "ip4InMcastPkts",
2549 [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2550 "ip4OutOctets",
2551 [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2552 "ip4OutPkts",
2553 [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2554 "ip4OutSegRqd",
2555 [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2556 "ip4OutMcastPkts",
2557 [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2558 "ip6InOctets",
2559 [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2560 "ip6InPkts",
2561 [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2562 "ip6InReasmRqd",
2563 [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2564 "ip6InMcastPkts",
2565 [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2566 "ip6OutOctets",
2567 [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2568 "ip6OutPkts",
2569 [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2570 "ip6OutSegRqd",
2571 [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2572 "ip6OutMcastPkts",
2573 [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] =
2574 "tcpInSegs",
2575 [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] =
2576 "tcpOutSegs",
2577 [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
2578 "iwInRdmaReads",
2579 [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
2580 "iwInRdmaSends",
2581 [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
2582 "iwInRdmaWrites",
2583 [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
2584 "iwOutRdmaReads",
2585 [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
2586 "iwOutRdmaSends",
2587 [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
2588 "iwOutRdmaWrites",
2589 [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] =
2590 "iwRdmaBnd",
2591 [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] =
2592 "iwRdmaInv"
2593 };
2594
2595 static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str)
2596 {
2597 u32 firmware_version = I40IW_FW_VERSION;
2598
2599 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u", firmware_version,
2600 (firmware_version & 0x000000ff));
2601 }
2602
2603 /**
2604 * i40iw_alloc_hw_stats - Allocate a hw stats structure
2605 * @ibdev: device pointer from stack
2606 * @port_num: port number
2607 */
2608 static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev,
2609 u8 port_num)
2610 {
2611 struct i40iw_device *iwdev = to_iwdev(ibdev);
2612 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2613 int num_counters = I40IW_HW_STAT_INDEX_MAX_32 +
2614 I40IW_HW_STAT_INDEX_MAX_64;
2615 unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
2616
2617 BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) !=
2618 (I40IW_HW_STAT_INDEX_MAX_32 +
2619 I40IW_HW_STAT_INDEX_MAX_64));
2620
2621 /*
2622 * PFs get the default update lifespan, but VFs only update once
2623 * per second
2624 */
2625 if (!dev->is_pf)
2626 lifespan = 1000;
2627 return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters,
2628 lifespan);
2629 }
2630
2631 /**
2632 * i40iw_get_hw_stats - Populates the rdma_hw_stats structure
2633 * @ibdev: device pointer from stack
2634 * @stats: stats pointer from stack
2635 * @port_num: port number
2636 * @index: which hw counter the stack is requesting we update
2637 */
2638 static int i40iw_get_hw_stats(struct ib_device *ibdev,
2639 struct rdma_hw_stats *stats,
2640 u8 port_num, int index)
2641 {
2642 struct i40iw_device *iwdev = to_iwdev(ibdev);
2643 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2644 struct i40iw_vsi_pestat *devstat = iwdev->vsi.pestat;
2645 struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
2646
2647 if (dev->is_pf) {
2648 i40iw_hw_stats_read_all(devstat, &devstat->hw_stats);
2649 } else {
2650 if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
2651 return -ENOSYS;
2652 }
2653
2654 memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats));
2655
2656 return stats->num_counters;
2657 }
2658
2659 /**
2660 * i40iw_query_gid - Query port GID
2661 * @ibdev: device pointer from stack
2662 * @port: port number
2663 * @index: Entry index
2664 * @gid: Global ID
2665 */
2666 static int i40iw_query_gid(struct ib_device *ibdev,
2667 u8 port,
2668 int index,
2669 union ib_gid *gid)
2670 {
2671 struct i40iw_device *iwdev = to_iwdev(ibdev);
2672
2673 memset(gid->raw, 0, sizeof(gid->raw));
2674 ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
2675 return 0;
2676 }
2677
2678 /**
2679 * i40iw_modify_port Modify port properties
2680 * @ibdev: device pointer from stack
2681 * @port: port number
2682 * @port_modify_mask: mask for port modifications
2683 * @props: port properties
2684 */
2685 static int i40iw_modify_port(struct ib_device *ibdev,
2686 u8 port,
2687 int port_modify_mask,
2688 struct ib_port_modify *props)
2689 {
2690 return -ENOSYS;
2691 }
2692
2693 /**
2694 * i40iw_query_pkey - Query partition key
2695 * @ibdev: device pointer from stack
2696 * @port: port number
2697 * @index: index of pkey
2698 * @pkey: pointer to store the pkey
2699 */
2700 static int i40iw_query_pkey(struct ib_device *ibdev,
2701 u8 port,
2702 u16 index,
2703 u16 *pkey)
2704 {
2705 *pkey = 0;
2706 return 0;
2707 }
2708
2709 /**
2710 * i40iw_create_ah - create address handle
2711 * @ibpd: ptr of pd
2712 * @ah_attr: address handle attributes
2713 */
2714 static struct ib_ah *i40iw_create_ah(struct ib_pd *ibpd,
2715 struct rdma_ah_attr *attr,
2716 struct ib_udata *udata)
2717
2718 {
2719 return ERR_PTR(-ENOSYS);
2720 }
2721
2722 /**
2723 * i40iw_destroy_ah - Destroy address handle
2724 * @ah: pointer to address handle
2725 */
2726 static int i40iw_destroy_ah(struct ib_ah *ah)
2727 {
2728 return -ENOSYS;
2729 }
2730
2731 /**
2732 * i40iw_init_rdma_device - initialization of iwarp device
2733 * @iwdev: iwarp device
2734 */
2735 static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
2736 {
2737 struct i40iw_ib_device *iwibdev;
2738 struct net_device *netdev = iwdev->netdev;
2739 struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context;
2740
2741 iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev));
2742 if (!iwibdev) {
2743 i40iw_pr_err("iwdev == NULL\n");
2744 return NULL;
2745 }
2746 strlcpy(iwibdev->ibdev.name, "i40iw%d", IB_DEVICE_NAME_MAX);
2747 iwibdev->ibdev.owner = THIS_MODULE;
2748 iwdev->iwibdev = iwibdev;
2749 iwibdev->iwdev = iwdev;
2750
2751 iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
2752 ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
2753
2754 iwibdev->ibdev.uverbs_cmd_mask =
2755 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2756 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2757 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2758 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2759 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2760 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2761 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2762 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2763 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2764 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2765 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2766 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2767 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2768 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2769 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2770 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2771 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2772 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2773 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2774 (1ull << IB_USER_VERBS_CMD_POST_SEND);
2775 iwibdev->ibdev.phys_port_cnt = 1;
2776 iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count;
2777 iwibdev->ibdev.dev.parent = &pcidev->dev;
2778 iwibdev->ibdev.query_port = i40iw_query_port;
2779 iwibdev->ibdev.modify_port = i40iw_modify_port;
2780 iwibdev->ibdev.query_pkey = i40iw_query_pkey;
2781 iwibdev->ibdev.query_gid = i40iw_query_gid;
2782 iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext;
2783 iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext;
2784 iwibdev->ibdev.mmap = i40iw_mmap;
2785 iwibdev->ibdev.alloc_pd = i40iw_alloc_pd;
2786 iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd;
2787 iwibdev->ibdev.create_qp = i40iw_create_qp;
2788 iwibdev->ibdev.modify_qp = i40iw_modify_qp;
2789 iwibdev->ibdev.query_qp = i40iw_query_qp;
2790 iwibdev->ibdev.destroy_qp = i40iw_destroy_qp;
2791 iwibdev->ibdev.create_cq = i40iw_create_cq;
2792 iwibdev->ibdev.destroy_cq = i40iw_destroy_cq;
2793 iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr;
2794 iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr;
2795 iwibdev->ibdev.dereg_mr = i40iw_dereg_mr;
2796 iwibdev->ibdev.alloc_hw_stats = i40iw_alloc_hw_stats;
2797 iwibdev->ibdev.get_hw_stats = i40iw_get_hw_stats;
2798 iwibdev->ibdev.query_device = i40iw_query_device;
2799 iwibdev->ibdev.create_ah = i40iw_create_ah;
2800 iwibdev->ibdev.destroy_ah = i40iw_destroy_ah;
2801 iwibdev->ibdev.drain_sq = i40iw_drain_sq;
2802 iwibdev->ibdev.drain_rq = i40iw_drain_rq;
2803 iwibdev->ibdev.alloc_mr = i40iw_alloc_mr;
2804 iwibdev->ibdev.map_mr_sg = i40iw_map_mr_sg;
2805 iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
2806 if (!iwibdev->ibdev.iwcm) {
2807 ib_dealloc_device(&iwibdev->ibdev);
2808 return NULL;
2809 }
2810
2811 iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref;
2812 iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref;
2813 iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp;
2814 iwibdev->ibdev.iwcm->connect = i40iw_connect;
2815 iwibdev->ibdev.iwcm->accept = i40iw_accept;
2816 iwibdev->ibdev.iwcm->reject = i40iw_reject;
2817 iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen;
2818 iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen;
2819 memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name,
2820 sizeof(iwibdev->ibdev.iwcm->ifname));
2821 iwibdev->ibdev.get_port_immutable = i40iw_port_immutable;
2822 iwibdev->ibdev.get_dev_fw_str = i40iw_get_dev_fw_str;
2823 iwibdev->ibdev.poll_cq = i40iw_poll_cq;
2824 iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq;
2825 iwibdev->ibdev.post_send = i40iw_post_send;
2826 iwibdev->ibdev.post_recv = i40iw_post_recv;
2827
2828 return iwibdev;
2829 }
2830
2831 /**
2832 * i40iw_port_ibevent - indicate port event
2833 * @iwdev: iwarp device
2834 */
2835 void i40iw_port_ibevent(struct i40iw_device *iwdev)
2836 {
2837 struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
2838 struct ib_event event;
2839
2840 event.device = &iwibdev->ibdev;
2841 event.element.port_num = 1;
2842 event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2843 ib_dispatch_event(&event);
2844 }
2845
2846 /**
2847 * i40iw_unregister_rdma_device - unregister of iwarp from IB
2848 * @iwibdev: rdma device ptr
2849 */
2850 static void i40iw_unregister_rdma_device(struct i40iw_ib_device *iwibdev)
2851 {
2852 int i;
2853
2854 for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i)
2855 device_remove_file(&iwibdev->ibdev.dev,
2856 i40iw_dev_attributes[i]);
2857 ib_unregister_device(&iwibdev->ibdev);
2858 }
2859
2860 /**
2861 * i40iw_destroy_rdma_device - destroy rdma device and free resources
2862 * @iwibdev: IB device ptr
2863 */
2864 void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
2865 {
2866 if (!iwibdev)
2867 return;
2868
2869 i40iw_unregister_rdma_device(iwibdev);
2870 kfree(iwibdev->ibdev.iwcm);
2871 iwibdev->ibdev.iwcm = NULL;
2872 wait_event_timeout(iwibdev->iwdev->close_wq,
2873 !atomic64_read(&iwibdev->iwdev->use_count),
2874 I40IW_EVENT_TIMEOUT);
2875 ib_dealloc_device(&iwibdev->ibdev);
2876 }
2877
2878 /**
2879 * i40iw_register_rdma_device - register iwarp device to IB
2880 * @iwdev: iwarp device
2881 */
2882 int i40iw_register_rdma_device(struct i40iw_device *iwdev)
2883 {
2884 int i, ret;
2885 struct i40iw_ib_device *iwibdev;
2886
2887 iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
2888 if (!iwdev->iwibdev)
2889 return -ENOMEM;
2890 iwibdev = iwdev->iwibdev;
2891
2892 ret = ib_register_device(&iwibdev->ibdev, NULL);
2893 if (ret)
2894 goto error;
2895
2896 for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) {
2897 ret =
2898 device_create_file(&iwibdev->ibdev.dev,
2899 i40iw_dev_attributes[i]);
2900 if (ret) {
2901 while (i > 0) {
2902 i--;
2903 device_remove_file(&iwibdev->ibdev.dev, i40iw_dev_attributes[i]);
2904 }
2905 ib_unregister_device(&iwibdev->ibdev);
2906 goto error;
2907 }
2908 }
2909 return 0;
2910 error:
2911 kfree(iwdev->iwibdev->ibdev.iwcm);
2912 iwdev->iwibdev->ibdev.iwcm = NULL;
2913 ib_dealloc_device(&iwdev->iwibdev->ibdev);
2914 return ret;
2915 }
CRIS linux kernel tree