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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / infiniband / hw / mlx5 / qp.c
blob39d24bf694a864788f2d3dc806c3019bb4b12b8b
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_ib.h"
39
40 /* not supported currently */
41 static int wq_signature;
42
43 enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45 };
46
47 enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52 };
53
54 enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 };
57
58 static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73 };
74
75 struct mlx5_wqe_eth_pad {
76 u8 rsvd0[16];
77 };
78
79 enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
82 };
83
84 struct mlx5_modify_raw_qp_param {
85 u16 operation;
86
87 u32 set_mask; /* raw_qp_set_mask_map */
88 u32 rate_limit;
89 u8 rq_q_ctr_id;
90 };
91
92 static void get_cqs(enum ib_qp_type qp_type,
93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
95
96 static int is_qp0(enum ib_qp_type qp_type)
97 {
98 return qp_type == IB_QPT_SMI;
99 }
100
101 static int is_sqp(enum ib_qp_type qp_type)
102 {
103 return is_qp0(qp_type) || is_qp1(qp_type);
104 }
105
106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
107 {
108 return mlx5_buf_offset(&qp->buf, offset);
109 }
110
111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
112 {
113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
114 }
115
116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
117 {
118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
119 }
120
121 /**
122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
123 *
124 * @qp: QP to copy from.
125 * @send: copy from the send queue when non-zero, use the receive queue
126 * otherwise.
127 * @wqe_index: index to start copying from. For send work queues, the
128 * wqe_index is in units of MLX5_SEND_WQE_BB.
129 * For receive work queue, it is the number of work queue
130 * element in the queue.
131 * @buffer: destination buffer.
132 * @length: maximum number of bytes to copy.
133 *
134 * Copies at least a single WQE, but may copy more data.
135 *
136 * Return: the number of bytes copied, or an error code.
137 */
138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
139 void *buffer, u32 length,
140 struct mlx5_ib_qp_base *base)
141 {
142 struct ib_device *ibdev = qp->ibqp.device;
143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
145 size_t offset;
146 size_t wq_end;
147 struct ib_umem *umem = base->ubuffer.umem;
148 u32 first_copy_length;
149 int wqe_length;
150 int ret;
151
152 if (wq->wqe_cnt == 0) {
153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
154 qp->ibqp.qp_type);
155 return -EINVAL;
156 }
157
158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
160
161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
162 return -EINVAL;
163
164 if (offset > umem->length ||
165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
166 return -EINVAL;
167
168 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
170 if (ret)
171 return ret;
172
173 if (send) {
174 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
176
177 wqe_length = ds * MLX5_WQE_DS_UNITS;
178 } else {
179 wqe_length = 1 << wq->wqe_shift;
180 }
181
182 if (wqe_length <= first_copy_length)
183 return first_copy_length;
184
185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
186 wqe_length - first_copy_length);
187 if (ret)
188 return ret;
189
190 return wqe_length;
191 }
192
193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
194 {
195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
196 struct ib_event event;
197
198 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
199 /* This event is only valid for trans_qps */
200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
201 }
202
203 if (ibqp->event_handler) {
204 event.device = ibqp->device;
205 event.element.qp = ibqp;
206 switch (type) {
207 case MLX5_EVENT_TYPE_PATH_MIG:
208 event.event = IB_EVENT_PATH_MIG;
209 break;
210 case MLX5_EVENT_TYPE_COMM_EST:
211 event.event = IB_EVENT_COMM_EST;
212 break;
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 event.event = IB_EVENT_SQ_DRAINED;
215 break;
216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
217 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
218 break;
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 event.event = IB_EVENT_QP_FATAL;
221 break;
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 event.event = IB_EVENT_PATH_MIG_ERR;
224 break;
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 event.event = IB_EVENT_QP_REQ_ERR;
227 break;
228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
229 event.event = IB_EVENT_QP_ACCESS_ERR;
230 break;
231 default:
232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
233 return;
234 }
235
236 ibqp->event_handler(&event, ibqp->qp_context);
237 }
238 }
239
240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
242 {
243 int wqe_size;
244 int wq_size;
245
246 /* Sanity check RQ size before proceeding */
247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
248 return -EINVAL;
249
250 if (!has_rq) {
251 qp->rq.max_gs = 0;
252 qp->rq.wqe_cnt = 0;
253 qp->rq.wqe_shift = 0;
254 cap->max_recv_wr = 0;
255 cap->max_recv_sge = 0;
256 } else {
257 if (ucmd) {
258 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
259 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
261 qp->rq.max_post = qp->rq.wqe_cnt;
262 } else {
263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
265 wqe_size = roundup_pow_of_two(wqe_size);
266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
268 qp->rq.wqe_cnt = wq_size / wqe_size;
269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
271 wqe_size,
272 MLX5_CAP_GEN(dev->mdev,
273 max_wqe_sz_rq));
274 return -EINVAL;
275 }
276 qp->rq.wqe_shift = ilog2(wqe_size);
277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
278 qp->rq.max_post = qp->rq.wqe_cnt;
279 }
280 }
281
282 return 0;
283 }
284
285 static int sq_overhead(struct ib_qp_init_attr *attr)
286 {
287 int size = 0;
288
289 switch (attr->qp_type) {
290 case IB_QPT_XRC_INI:
291 size += sizeof(struct mlx5_wqe_xrc_seg);
292 /* fall through */
293 case IB_QPT_RC:
294 size += sizeof(struct mlx5_wqe_ctrl_seg) +
295 max(sizeof(struct mlx5_wqe_atomic_seg) +
296 sizeof(struct mlx5_wqe_raddr_seg),
297 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
298 sizeof(struct mlx5_mkey_seg));
299 break;
300
301 case IB_QPT_XRC_TGT:
302 return 0;
303
304 case IB_QPT_UC:
305 size += sizeof(struct mlx5_wqe_ctrl_seg) +
306 max(sizeof(struct mlx5_wqe_raddr_seg),
307 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
308 sizeof(struct mlx5_mkey_seg));
309 break;
310
311 case IB_QPT_UD:
312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
313 size += sizeof(struct mlx5_wqe_eth_pad) +
314 sizeof(struct mlx5_wqe_eth_seg);
315 /* fall through */
316 case IB_QPT_SMI:
317 case MLX5_IB_QPT_HW_GSI:
318 size += sizeof(struct mlx5_wqe_ctrl_seg) +
319 sizeof(struct mlx5_wqe_datagram_seg);
320 break;
321
322 case MLX5_IB_QPT_REG_UMR:
323 size += sizeof(struct mlx5_wqe_ctrl_seg) +
324 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
325 sizeof(struct mlx5_mkey_seg);
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 return size;
333 }
334
335 static int calc_send_wqe(struct ib_qp_init_attr *attr)
336 {
337 int inl_size = 0;
338 int size;
339
340 size = sq_overhead(attr);
341 if (size < 0)
342 return size;
343
344 if (attr->cap.max_inline_data) {
345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
346 attr->cap.max_inline_data;
347 }
348
349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
352 return MLX5_SIG_WQE_SIZE;
353 else
354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
355 }
356
357 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
358 {
359 int max_sge;
360
361 if (attr->qp_type == IB_QPT_RC)
362 max_sge = (min_t(int, wqe_size, 512) -
363 sizeof(struct mlx5_wqe_ctrl_seg) -
364 sizeof(struct mlx5_wqe_raddr_seg)) /
365 sizeof(struct mlx5_wqe_data_seg);
366 else if (attr->qp_type == IB_QPT_XRC_INI)
367 max_sge = (min_t(int, wqe_size, 512) -
368 sizeof(struct mlx5_wqe_ctrl_seg) -
369 sizeof(struct mlx5_wqe_xrc_seg) -
370 sizeof(struct mlx5_wqe_raddr_seg)) /
371 sizeof(struct mlx5_wqe_data_seg);
372 else
373 max_sge = (wqe_size - sq_overhead(attr)) /
374 sizeof(struct mlx5_wqe_data_seg);
375
376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
377 sizeof(struct mlx5_wqe_data_seg));
378 }
379
380 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
381 struct mlx5_ib_qp *qp)
382 {
383 int wqe_size;
384 int wq_size;
385
386 if (!attr->cap.max_send_wr)
387 return 0;
388
389 wqe_size = calc_send_wqe(attr);
390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
391 if (wqe_size < 0)
392 return wqe_size;
393
394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
397 return -EINVAL;
398 }
399
400 qp->max_inline_data = wqe_size - sq_overhead(attr) -
401 sizeof(struct mlx5_wqe_inline_seg);
402 attr->cap.max_inline_data = qp->max_inline_data;
403
404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
405 qp->signature_en = true;
406
407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
414 return -ENOMEM;
415 }
416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
417 qp->sq.max_gs = get_send_sge(attr, wqe_size);
418 if (qp->sq.max_gs < attr->cap.max_send_sge)
419 return -ENOMEM;
420
421 attr->cap.max_send_sge = qp->sq.max_gs;
422 qp->sq.max_post = wq_size / wqe_size;
423 attr->cap.max_send_wr = qp->sq.max_post;
424
425 return wq_size;
426 }
427
428 static int set_user_buf_size(struct mlx5_ib_dev *dev,
429 struct mlx5_ib_qp *qp,
430 struct mlx5_ib_create_qp *ucmd,
431 struct mlx5_ib_qp_base *base,
432 struct ib_qp_init_attr *attr)
433 {
434 int desc_sz = 1 << qp->sq.wqe_shift;
435
436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
439 return -EINVAL;
440 }
441
442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
444 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
445 return -EINVAL;
446 }
447
448 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
449
450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
452 qp->sq.wqe_cnt,
453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
454 return -EINVAL;
455 }
456
457 if (attr->qp_type == IB_QPT_RAW_PACKET ||
458 qp->flags & MLX5_IB_QP_UNDERLAY) {
459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
461 } else {
462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
463 (qp->sq.wqe_cnt << 6);
464 }
465
466 return 0;
467 }
468
469 static int qp_has_rq(struct ib_qp_init_attr *attr)
470 {
471 if (attr->qp_type == IB_QPT_XRC_INI ||
472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
473 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
474 !attr->cap.max_recv_wr)
475 return 0;
476
477 return 1;
478 }
479
480 static int first_med_bfreg(void)
481 {
482 return 1;
483 }
484
485 enum {
486 /* this is the first blue flame register in the array of bfregs assigned
487 * to a processes. Since we do not use it for blue flame but rather
488 * regular 64 bit doorbells, we do not need a lock for maintaiing
489 * "odd/even" order
490 */
491 NUM_NON_BLUE_FLAME_BFREGS = 1,
492 };
493
494 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
495 {
496 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
497 }
498
499 static int num_med_bfreg(struct mlx5_ib_dev *dev,
500 struct mlx5_bfreg_info *bfregi)
501 {
502 int n;
503
504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
505 NUM_NON_BLUE_FLAME_BFREGS;
506
507 return n >= 0 ? n : 0;
508 }
509
510 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
511 struct mlx5_bfreg_info *bfregi)
512 {
513 int med;
514
515 med = num_med_bfreg(dev, bfregi);
516 return ++med;
517 }
518
519 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
520 struct mlx5_bfreg_info *bfregi)
521 {
522 int i;
523
524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
525 if (!bfregi->count[i]) {
526 bfregi->count[i]++;
527 return i;
528 }
529 }
530
531 return -ENOMEM;
532 }
533
534 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
535 struct mlx5_bfreg_info *bfregi)
536 {
537 int minidx = first_med_bfreg();
538 int i;
539
540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
541 if (bfregi->count[i] < bfregi->count[minidx])
542 minidx = i;
543 if (!bfregi->count[minidx])
544 break;
545 }
546
547 bfregi->count[minidx]++;
548 return minidx;
549 }
550
551 static int alloc_bfreg(struct mlx5_ib_dev *dev,
552 struct mlx5_bfreg_info *bfregi,
553 enum mlx5_ib_latency_class lat)
554 {
555 int bfregn = -EINVAL;
556
557 mutex_lock(&bfregi->lock);
558 switch (lat) {
559 case MLX5_IB_LATENCY_CLASS_LOW:
560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
561 bfregn = 0;
562 bfregi->count[bfregn]++;
563 break;
564
565 case MLX5_IB_LATENCY_CLASS_MEDIUM:
566 if (bfregi->ver < 2)
567 bfregn = -ENOMEM;
568 else
569 bfregn = alloc_med_class_bfreg(dev, bfregi);
570 break;
571
572 case MLX5_IB_LATENCY_CLASS_HIGH:
573 if (bfregi->ver < 2)
574 bfregn = -ENOMEM;
575 else
576 bfregn = alloc_high_class_bfreg(dev, bfregi);
577 break;
578 }
579 mutex_unlock(&bfregi->lock);
580
581 return bfregn;
582 }
583
584 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
585 {
586 mutex_lock(&bfregi->lock);
587 bfregi->count[bfregn]--;
588 mutex_unlock(&bfregi->lock);
589 }
590
591 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
592 {
593 switch (state) {
594 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
601 default: return -1;
602 }
603 }
604
605 static int to_mlx5_st(enum ib_qp_type type)
606 {
607 switch (type) {
608 case IB_QPT_RC: return MLX5_QP_ST_RC;
609 case IB_QPT_UC: return MLX5_QP_ST_UC;
610 case IB_QPT_UD: return MLX5_QP_ST_UD;
611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
612 case IB_QPT_XRC_INI:
613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
614 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
616 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
617 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
618 case IB_QPT_RAW_PACKET:
619 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
620 case IB_QPT_MAX:
621 default: return -EINVAL;
622 }
623 }
624
625 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
626 struct mlx5_ib_cq *recv_cq);
627 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
628 struct mlx5_ib_cq *recv_cq);
629
630 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
631 struct mlx5_bfreg_info *bfregi, int bfregn,
632 bool dyn_bfreg)
633 {
634 int bfregs_per_sys_page;
635 int index_of_sys_page;
636 int offset;
637
638 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
639 MLX5_NON_FP_BFREGS_PER_UAR;
640 index_of_sys_page = bfregn / bfregs_per_sys_page;
641
642 if (dyn_bfreg) {
643 index_of_sys_page += bfregi->num_static_sys_pages;
644 if (bfregn > bfregi->num_dyn_bfregs ||
645 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
646 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
647 return -EINVAL;
648 }
649 }
650
651 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
652 return bfregi->sys_pages[index_of_sys_page] + offset;
653 }
654
655 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
656 struct ib_pd *pd,
657 unsigned long addr, size_t size,
658 struct ib_umem **umem,
659 int *npages, int *page_shift, int *ncont,
660 u32 *offset)
661 {
662 int err;
663
664 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
665 if (IS_ERR(*umem)) {
666 mlx5_ib_dbg(dev, "umem_get failed\n");
667 return PTR_ERR(*umem);
668 }
669
670 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
671
672 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
673 if (err) {
674 mlx5_ib_warn(dev, "bad offset\n");
675 goto err_umem;
676 }
677
678 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
679 addr, size, *npages, *page_shift, *ncont, *offset);
680
681 return 0;
682
683 err_umem:
684 ib_umem_release(*umem);
685 *umem = NULL;
686
687 return err;
688 }
689
690 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
691 struct mlx5_ib_rwq *rwq)
692 {
693 struct mlx5_ib_ucontext *context;
694
695 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
696 atomic_dec(&dev->delay_drop.rqs_cnt);
697
698 context = to_mucontext(pd->uobject->context);
699 mlx5_ib_db_unmap_user(context, &rwq->db);
700 if (rwq->umem)
701 ib_umem_release(rwq->umem);
702 }
703
704 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
705 struct mlx5_ib_rwq *rwq,
706 struct mlx5_ib_create_wq *ucmd)
707 {
708 struct mlx5_ib_ucontext *context;
709 int page_shift = 0;
710 int npages;
711 u32 offset = 0;
712 int ncont = 0;
713 int err;
714
715 if (!ucmd->buf_addr)
716 return -EINVAL;
717
718 context = to_mucontext(pd->uobject->context);
719 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
720 rwq->buf_size, 0, 0);
721 if (IS_ERR(rwq->umem)) {
722 mlx5_ib_dbg(dev, "umem_get failed\n");
723 err = PTR_ERR(rwq->umem);
724 return err;
725 }
726
727 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
728 &ncont, NULL);
729 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
730 &rwq->rq_page_offset);
731 if (err) {
732 mlx5_ib_warn(dev, "bad offset\n");
733 goto err_umem;
734 }
735
736 rwq->rq_num_pas = ncont;
737 rwq->page_shift = page_shift;
738 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
739 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
740
741 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
742 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
743 npages, page_shift, ncont, offset);
744
745 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
746 if (err) {
747 mlx5_ib_dbg(dev, "map failed\n");
748 goto err_umem;
749 }
750
751 rwq->create_type = MLX5_WQ_USER;
752 return 0;
753
754 err_umem:
755 ib_umem_release(rwq->umem);
756 return err;
757 }
758
759 static int adjust_bfregn(struct mlx5_ib_dev *dev,
760 struct mlx5_bfreg_info *bfregi, int bfregn)
761 {
762 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
763 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
764 }
765
766 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
767 struct mlx5_ib_qp *qp, struct ib_udata *udata,
768 struct ib_qp_init_attr *attr,
769 u32 **in,
770 struct mlx5_ib_create_qp_resp *resp, int *inlen,
771 struct mlx5_ib_qp_base *base)
772 {
773 struct mlx5_ib_ucontext *context;
774 struct mlx5_ib_create_qp ucmd;
775 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
776 int page_shift = 0;
777 int uar_index = 0;
778 int npages;
779 u32 offset = 0;
780 int bfregn;
781 int ncont = 0;
782 __be64 *pas;
783 void *qpc;
784 int err;
785
786 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
787 if (err) {
788 mlx5_ib_dbg(dev, "copy failed\n");
789 return err;
790 }
791
792 context = to_mucontext(pd->uobject->context);
793 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
794 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
795 ucmd.bfreg_index, true);
796 if (uar_index < 0)
797 return uar_index;
798
799 bfregn = MLX5_IB_INVALID_BFREG;
800 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
801 /*
802 * TBD: should come from the verbs when we have the API
803 */
804 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
805 bfregn = MLX5_CROSS_CHANNEL_BFREG;
806 }
807 else {
808 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
809 if (bfregn < 0) {
810 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
811 mlx5_ib_dbg(dev, "reverting to medium latency\n");
812 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
813 if (bfregn < 0) {
814 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
815 mlx5_ib_dbg(dev, "reverting to high latency\n");
816 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
817 if (bfregn < 0) {
818 mlx5_ib_warn(dev, "bfreg allocation failed\n");
819 return bfregn;
820 }
821 }
822 }
823 }
824
825 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
826 if (bfregn != MLX5_IB_INVALID_BFREG)
827 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
828 false);
829
830 qp->rq.offset = 0;
831 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
832 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
833
834 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
835 if (err)
836 goto err_bfreg;
837
838 if (ucmd.buf_addr && ubuffer->buf_size) {
839 ubuffer->buf_addr = ucmd.buf_addr;
840 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
841 ubuffer->buf_size,
842 &ubuffer->umem, &npages, &page_shift,
843 &ncont, &offset);
844 if (err)
845 goto err_bfreg;
846 } else {
847 ubuffer->umem = NULL;
848 }
849
850 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
851 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
852 *in = kvzalloc(*inlen, GFP_KERNEL);
853 if (!*in) {
854 err = -ENOMEM;
855 goto err_umem;
856 }
857
858 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
859 if (ubuffer->umem)
860 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
861
862 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
863
864 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
865 MLX5_SET(qpc, qpc, page_offset, offset);
866
867 MLX5_SET(qpc, qpc, uar_page, uar_index);
868 if (bfregn != MLX5_IB_INVALID_BFREG)
869 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
870 else
871 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
872 qp->bfregn = bfregn;
873
874 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
875 if (err) {
876 mlx5_ib_dbg(dev, "map failed\n");
877 goto err_free;
878 }
879
880 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
881 if (err) {
882 mlx5_ib_dbg(dev, "copy failed\n");
883 goto err_unmap;
884 }
885 qp->create_type = MLX5_QP_USER;
886
887 return 0;
888
889 err_unmap:
890 mlx5_ib_db_unmap_user(context, &qp->db);
891
892 err_free:
893 kvfree(*in);
894
895 err_umem:
896 if (ubuffer->umem)
897 ib_umem_release(ubuffer->umem);
898
899 err_bfreg:
900 if (bfregn != MLX5_IB_INVALID_BFREG)
901 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
902 return err;
903 }
904
905 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
906 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
907 {
908 struct mlx5_ib_ucontext *context;
909
910 context = to_mucontext(pd->uobject->context);
911 mlx5_ib_db_unmap_user(context, &qp->db);
912 if (base->ubuffer.umem)
913 ib_umem_release(base->ubuffer.umem);
914
915 /*
916 * Free only the BFREGs which are handled by the kernel.
917 * BFREGs of UARs allocated dynamically are handled by user.
918 */
919 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
920 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
921 }
922
923 static int create_kernel_qp(struct mlx5_ib_dev *dev,
924 struct ib_qp_init_attr *init_attr,
925 struct mlx5_ib_qp *qp,
926 u32 **in, int *inlen,
927 struct mlx5_ib_qp_base *base)
928 {
929 int uar_index;
930 void *qpc;
931 int err;
932
933 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
934 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
935 IB_QP_CREATE_IPOIB_UD_LSO |
936 IB_QP_CREATE_NETIF_QP |
937 mlx5_ib_create_qp_sqpn_qp1()))
938 return -EINVAL;
939
940 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
941 qp->bf.bfreg = &dev->fp_bfreg;
942 else
943 qp->bf.bfreg = &dev->bfreg;
944
945 /* We need to divide by two since each register is comprised of
946 * two buffers of identical size, namely odd and even
947 */
948 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
949 uar_index = qp->bf.bfreg->index;
950
951 err = calc_sq_size(dev, init_attr, qp);
952 if (err < 0) {
953 mlx5_ib_dbg(dev, "err %d\n", err);
954 return err;
955 }
956
957 qp->rq.offset = 0;
958 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
959 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
960
961 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
962 if (err) {
963 mlx5_ib_dbg(dev, "err %d\n", err);
964 return err;
965 }
966
967 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
968 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
969 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
970 *in = kvzalloc(*inlen, GFP_KERNEL);
971 if (!*in) {
972 err = -ENOMEM;
973 goto err_buf;
974 }
975
976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
977 MLX5_SET(qpc, qpc, uar_page, uar_index);
978 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
979
980 /* Set "fast registration enabled" for all kernel QPs */
981 MLX5_SET(qpc, qpc, fre, 1);
982 MLX5_SET(qpc, qpc, rlky, 1);
983
984 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
985 MLX5_SET(qpc, qpc, deth_sqpn, 1);
986 qp->flags |= MLX5_IB_QP_SQPN_QP1;
987 }
988
989 mlx5_fill_page_array(&qp->buf,
990 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
991
992 err = mlx5_db_alloc(dev->mdev, &qp->db);
993 if (err) {
994 mlx5_ib_dbg(dev, "err %d\n", err);
995 goto err_free;
996 }
997
998 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
999 sizeof(*qp->sq.wrid), GFP_KERNEL);
1000 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1001 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1002 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1003 sizeof(*qp->rq.wrid), GFP_KERNEL);
1004 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1005 sizeof(*qp->sq.w_list), GFP_KERNEL);
1006 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1007 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1008
1009 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1010 !qp->sq.w_list || !qp->sq.wqe_head) {
1011 err = -ENOMEM;
1012 goto err_wrid;
1013 }
1014 qp->create_type = MLX5_QP_KERNEL;
1015
1016 return 0;
1017
1018 err_wrid:
1019 kvfree(qp->sq.wqe_head);
1020 kvfree(qp->sq.w_list);
1021 kvfree(qp->sq.wrid);
1022 kvfree(qp->sq.wr_data);
1023 kvfree(qp->rq.wrid);
1024 mlx5_db_free(dev->mdev, &qp->db);
1025
1026 err_free:
1027 kvfree(*in);
1028
1029 err_buf:
1030 mlx5_buf_free(dev->mdev, &qp->buf);
1031 return err;
1032 }
1033
1034 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1035 {
1036 kvfree(qp->sq.wqe_head);
1037 kvfree(qp->sq.w_list);
1038 kvfree(qp->sq.wrid);
1039 kvfree(qp->sq.wr_data);
1040 kvfree(qp->rq.wrid);
1041 mlx5_db_free(dev->mdev, &qp->db);
1042 mlx5_buf_free(dev->mdev, &qp->buf);
1043 }
1044
1045 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1046 {
1047 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1048 (attr->qp_type == MLX5_IB_QPT_DCI) ||
1049 (attr->qp_type == IB_QPT_XRC_INI))
1050 return MLX5_SRQ_RQ;
1051 else if (!qp->has_rq)
1052 return MLX5_ZERO_LEN_RQ;
1053 else
1054 return MLX5_NON_ZERO_RQ;
1055 }
1056
1057 static int is_connected(enum ib_qp_type qp_type)
1058 {
1059 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1060 return 1;
1061
1062 return 0;
1063 }
1064
1065 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1066 struct mlx5_ib_qp *qp,
1067 struct mlx5_ib_sq *sq, u32 tdn)
1068 {
1069 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1070 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1071
1072 MLX5_SET(tisc, tisc, transport_domain, tdn);
1073 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1074 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1075
1076 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1077 }
1078
1079 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1080 struct mlx5_ib_sq *sq)
1081 {
1082 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1083 }
1084
1085 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1086 struct mlx5_ib_sq *sq, void *qpin,
1087 struct ib_pd *pd)
1088 {
1089 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1090 __be64 *pas;
1091 void *in;
1092 void *sqc;
1093 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1094 void *wq;
1095 int inlen;
1096 int err;
1097 int page_shift = 0;
1098 int npages;
1099 int ncont = 0;
1100 u32 offset = 0;
1101
1102 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1103 &sq->ubuffer.umem, &npages, &page_shift,
1104 &ncont, &offset);
1105 if (err)
1106 return err;
1107
1108 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1109 in = kvzalloc(inlen, GFP_KERNEL);
1110 if (!in) {
1111 err = -ENOMEM;
1112 goto err_umem;
1113 }
1114
1115 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1116 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1117 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1118 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1119 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1120 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1121 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1122 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1123 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1124 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1125 MLX5_CAP_ETH(dev->mdev, swp))
1126 MLX5_SET(sqc, sqc, allow_swp, 1);
1127
1128 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1129 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1130 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1131 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1132 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1133 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1134 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1135 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1136 MLX5_SET(wq, wq, page_offset, offset);
1137
1138 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1139 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1140
1141 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1142
1143 kvfree(in);
1144
1145 if (err)
1146 goto err_umem;
1147
1148 return 0;
1149
1150 err_umem:
1151 ib_umem_release(sq->ubuffer.umem);
1152 sq->ubuffer.umem = NULL;
1153
1154 return err;
1155 }
1156
1157 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1158 struct mlx5_ib_sq *sq)
1159 {
1160 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1161 ib_umem_release(sq->ubuffer.umem);
1162 }
1163
1164 static int get_rq_pas_size(void *qpc)
1165 {
1166 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1167 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1168 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1169 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1170 u32 po_quanta = 1 << (log_page_size - 6);
1171 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1172 u32 page_size = 1 << log_page_size;
1173 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1174 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1175
1176 return rq_num_pas * sizeof(u64);
1177 }
1178
1179 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1180 struct mlx5_ib_rq *rq, void *qpin)
1181 {
1182 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1183 __be64 *pas;
1184 __be64 *qp_pas;
1185 void *in;
1186 void *rqc;
1187 void *wq;
1188 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1189 int inlen;
1190 int err;
1191 u32 rq_pas_size = get_rq_pas_size(qpc);
1192
1193 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1194 in = kvzalloc(inlen, GFP_KERNEL);
1195 if (!in)
1196 return -ENOMEM;
1197
1198 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1199 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1200 MLX5_SET(rqc, rqc, vsd, 1);
1201 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1202 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1203 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1204 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1205 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1206
1207 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1208 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1209
1210 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1211 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1212 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1213 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1214 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1215 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1216 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1217 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1218 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1219 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1220
1221 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1222 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1223 memcpy(pas, qp_pas, rq_pas_size);
1224
1225 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1226
1227 kvfree(in);
1228
1229 return err;
1230 }
1231
1232 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1233 struct mlx5_ib_rq *rq)
1234 {
1235 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1236 }
1237
1238 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1239 {
1240 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1241 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1242 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1243 }
1244
1245 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1246 struct mlx5_ib_rq *rq, u32 tdn,
1247 bool tunnel_offload_en)
1248 {
1249 u32 *in;
1250 void *tirc;
1251 int inlen;
1252 int err;
1253
1254 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1255 in = kvzalloc(inlen, GFP_KERNEL);
1256 if (!in)
1257 return -ENOMEM;
1258
1259 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1260 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1261 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1262 MLX5_SET(tirc, tirc, transport_domain, tdn);
1263 if (tunnel_offload_en)
1264 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1265
1266 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1267
1268 kvfree(in);
1269
1270 return err;
1271 }
1272
1273 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1274 struct mlx5_ib_rq *rq)
1275 {
1276 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1277 }
1278
1279 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1280 u32 *in,
1281 struct ib_pd *pd)
1282 {
1283 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1284 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1285 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1286 struct ib_uobject *uobj = pd->uobject;
1287 struct ib_ucontext *ucontext = uobj->context;
1288 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1289 int err;
1290 u32 tdn = mucontext->tdn;
1291
1292 if (qp->sq.wqe_cnt) {
1293 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1294 if (err)
1295 return err;
1296
1297 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1298 if (err)
1299 goto err_destroy_tis;
1300
1301 sq->base.container_mibqp = qp;
1302 sq->base.mqp.event = mlx5_ib_qp_event;
1303 }
1304
1305 if (qp->rq.wqe_cnt) {
1306 rq->base.container_mibqp = qp;
1307
1308 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1309 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1310 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1311 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1312 err = create_raw_packet_qp_rq(dev, rq, in);
1313 if (err)
1314 goto err_destroy_sq;
1315
1316
1317 err = create_raw_packet_qp_tir(dev, rq, tdn,
1318 qp->tunnel_offload_en);
1319 if (err)
1320 goto err_destroy_rq;
1321 }
1322
1323 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1324 rq->base.mqp.qpn;
1325
1326 return 0;
1327
1328 err_destroy_rq:
1329 destroy_raw_packet_qp_rq(dev, rq);
1330 err_destroy_sq:
1331 if (!qp->sq.wqe_cnt)
1332 return err;
1333 destroy_raw_packet_qp_sq(dev, sq);
1334 err_destroy_tis:
1335 destroy_raw_packet_qp_tis(dev, sq);
1336
1337 return err;
1338 }
1339
1340 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1341 struct mlx5_ib_qp *qp)
1342 {
1343 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1344 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1345 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1346
1347 if (qp->rq.wqe_cnt) {
1348 destroy_raw_packet_qp_tir(dev, rq);
1349 destroy_raw_packet_qp_rq(dev, rq);
1350 }
1351
1352 if (qp->sq.wqe_cnt) {
1353 destroy_raw_packet_qp_sq(dev, sq);
1354 destroy_raw_packet_qp_tis(dev, sq);
1355 }
1356 }
1357
1358 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1359 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1360 {
1361 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1362 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1363
1364 sq->sq = &qp->sq;
1365 rq->rq = &qp->rq;
1366 sq->doorbell = &qp->db;
1367 rq->doorbell = &qp->db;
1368 }
1369
1370 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1371 {
1372 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1373 }
1374
1375 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1376 struct ib_pd *pd,
1377 struct ib_qp_init_attr *init_attr,
1378 struct ib_udata *udata)
1379 {
1380 struct ib_uobject *uobj = pd->uobject;
1381 struct ib_ucontext *ucontext = uobj->context;
1382 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1383 struct mlx5_ib_create_qp_resp resp = {};
1384 int inlen;
1385 int err;
1386 u32 *in;
1387 void *tirc;
1388 void *hfso;
1389 u32 selected_fields = 0;
1390 size_t min_resp_len;
1391 u32 tdn = mucontext->tdn;
1392 struct mlx5_ib_create_qp_rss ucmd = {};
1393 size_t required_cmd_sz;
1394
1395 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1396 return -EOPNOTSUPP;
1397
1398 if (init_attr->create_flags || init_attr->send_cq)
1399 return -EINVAL;
1400
1401 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1402 if (udata->outlen < min_resp_len)
1403 return -EINVAL;
1404
1405 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1406 if (udata->inlen < required_cmd_sz) {
1407 mlx5_ib_dbg(dev, "invalid inlen\n");
1408 return -EINVAL;
1409 }
1410
1411 if (udata->inlen > sizeof(ucmd) &&
1412 !ib_is_udata_cleared(udata, sizeof(ucmd),
1413 udata->inlen - sizeof(ucmd))) {
1414 mlx5_ib_dbg(dev, "inlen is not supported\n");
1415 return -EOPNOTSUPP;
1416 }
1417
1418 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1419 mlx5_ib_dbg(dev, "copy failed\n");
1420 return -EFAULT;
1421 }
1422
1423 if (ucmd.comp_mask) {
1424 mlx5_ib_dbg(dev, "invalid comp mask\n");
1425 return -EOPNOTSUPP;
1426 }
1427
1428 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1429 mlx5_ib_dbg(dev, "invalid flags\n");
1430 return -EOPNOTSUPP;
1431 }
1432
1433 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1434 !tunnel_offload_supported(dev->mdev)) {
1435 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1436 return -EOPNOTSUPP;
1437 }
1438
1439 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1440 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1441 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1442 return -EOPNOTSUPP;
1443 }
1444
1445 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1446 if (err) {
1447 mlx5_ib_dbg(dev, "copy failed\n");
1448 return -EINVAL;
1449 }
1450
1451 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1452 in = kvzalloc(inlen, GFP_KERNEL);
1453 if (!in)
1454 return -ENOMEM;
1455
1456 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1457 MLX5_SET(tirc, tirc, disp_type,
1458 MLX5_TIRC_DISP_TYPE_INDIRECT);
1459 MLX5_SET(tirc, tirc, indirect_table,
1460 init_attr->rwq_ind_tbl->ind_tbl_num);
1461 MLX5_SET(tirc, tirc, transport_domain, tdn);
1462
1463 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1464
1465 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1466 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1467
1468 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1469 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1470 else
1471 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1472
1473 switch (ucmd.rx_hash_function) {
1474 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1475 {
1476 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1477 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1478
1479 if (len != ucmd.rx_key_len) {
1480 err = -EINVAL;
1481 goto err;
1482 }
1483
1484 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1485 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1486 memcpy(rss_key, ucmd.rx_hash_key, len);
1487 break;
1488 }
1489 default:
1490 err = -EOPNOTSUPP;
1491 goto err;
1492 }
1493
1494 if (!ucmd.rx_hash_fields_mask) {
1495 /* special case when this TIR serves as steering entry without hashing */
1496 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1497 goto create_tir;
1498 err = -EINVAL;
1499 goto err;
1500 }
1501
1502 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1503 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1504 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1505 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1506 err = -EINVAL;
1507 goto err;
1508 }
1509
1510 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1511 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1512 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1513 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1514 MLX5_L3_PROT_TYPE_IPV4);
1515 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1516 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1517 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1518 MLX5_L3_PROT_TYPE_IPV6);
1519
1520 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1521 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1522 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1523 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1524 err = -EINVAL;
1525 goto err;
1526 }
1527
1528 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1529 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1530 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1531 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1532 MLX5_L4_PROT_TYPE_TCP);
1533 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1534 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1535 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1536 MLX5_L4_PROT_TYPE_UDP);
1537
1538 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1539 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1540 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1541
1542 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1544 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1545
1546 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1547 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1548 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1549
1550 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1551 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1552 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1553
1554 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1555
1556 create_tir:
1557 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1558
1559 if (err)
1560 goto err;
1561
1562 kvfree(in);
1563 /* qpn is reserved for that QP */
1564 qp->trans_qp.base.mqp.qpn = 0;
1565 qp->flags |= MLX5_IB_QP_RSS;
1566 return 0;
1567
1568 err:
1569 kvfree(in);
1570 return err;
1571 }
1572
1573 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1574 struct ib_qp_init_attr *init_attr,
1575 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1576 {
1577 struct mlx5_ib_resources *devr = &dev->devr;
1578 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1579 struct mlx5_core_dev *mdev = dev->mdev;
1580 struct mlx5_ib_create_qp_resp resp;
1581 struct mlx5_ib_cq *send_cq;
1582 struct mlx5_ib_cq *recv_cq;
1583 unsigned long flags;
1584 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1585 struct mlx5_ib_create_qp ucmd;
1586 struct mlx5_ib_qp_base *base;
1587 void *qpc;
1588 u32 *in;
1589 int err;
1590
1591 mutex_init(&qp->mutex);
1592 spin_lock_init(&qp->sq.lock);
1593 spin_lock_init(&qp->rq.lock);
1594
1595 if (init_attr->rwq_ind_tbl) {
1596 if (!udata)
1597 return -ENOSYS;
1598
1599 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1600 return err;
1601 }
1602
1603 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1604 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1605 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1606 return -EINVAL;
1607 } else {
1608 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1609 }
1610 }
1611
1612 if (init_attr->create_flags &
1613 (IB_QP_CREATE_CROSS_CHANNEL |
1614 IB_QP_CREATE_MANAGED_SEND |
1615 IB_QP_CREATE_MANAGED_RECV)) {
1616 if (!MLX5_CAP_GEN(mdev, cd)) {
1617 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1618 return -EINVAL;
1619 }
1620 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1621 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1622 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1623 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1624 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1625 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1626 }
1627
1628 if (init_attr->qp_type == IB_QPT_UD &&
1629 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1630 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1631 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1632 return -EOPNOTSUPP;
1633 }
1634
1635 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1636 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1637 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1638 return -EOPNOTSUPP;
1639 }
1640 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1641 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1642 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1643 return -EOPNOTSUPP;
1644 }
1645 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1646 }
1647
1648 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1649 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1650
1651 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1652 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1653 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1654 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1655 return -EOPNOTSUPP;
1656 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1657 }
1658
1659 if (pd && pd->uobject) {
1660 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1661 mlx5_ib_dbg(dev, "copy failed\n");
1662 return -EFAULT;
1663 }
1664
1665 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1666 &ucmd, udata->inlen, &uidx);
1667 if (err)
1668 return err;
1669
1670 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1671 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1672 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1673 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1674 !tunnel_offload_supported(mdev)) {
1675 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1676 return -EOPNOTSUPP;
1677 }
1678 qp->tunnel_offload_en = true;
1679 }
1680
1681 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1682 if (init_attr->qp_type != IB_QPT_UD ||
1683 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1684 MLX5_CAP_PORT_TYPE_IB) ||
1685 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1686 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1687 return -EOPNOTSUPP;
1688 }
1689
1690 qp->flags |= MLX5_IB_QP_UNDERLAY;
1691 qp->underlay_qpn = init_attr->source_qpn;
1692 }
1693 } else {
1694 qp->wq_sig = !!wq_signature;
1695 }
1696
1697 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1698 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1699 &qp->raw_packet_qp.rq.base :
1700 &qp->trans_qp.base;
1701
1702 qp->has_rq = qp_has_rq(init_attr);
1703 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1704 qp, (pd && pd->uobject) ? &ucmd : NULL);
1705 if (err) {
1706 mlx5_ib_dbg(dev, "err %d\n", err);
1707 return err;
1708 }
1709
1710 if (pd) {
1711 if (pd->uobject) {
1712 __u32 max_wqes =
1713 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1714 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1715 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1716 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1717 mlx5_ib_dbg(dev, "invalid rq params\n");
1718 return -EINVAL;
1719 }
1720 if (ucmd.sq_wqe_count > max_wqes) {
1721 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1722 ucmd.sq_wqe_count, max_wqes);
1723 return -EINVAL;
1724 }
1725 if (init_attr->create_flags &
1726 mlx5_ib_create_qp_sqpn_qp1()) {
1727 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1728 return -EINVAL;
1729 }
1730 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1731 &resp, &inlen, base);
1732 if (err)
1733 mlx5_ib_dbg(dev, "err %d\n", err);
1734 } else {
1735 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1736 base);
1737 if (err)
1738 mlx5_ib_dbg(dev, "err %d\n", err);
1739 }
1740
1741 if (err)
1742 return err;
1743 } else {
1744 in = kvzalloc(inlen, GFP_KERNEL);
1745 if (!in)
1746 return -ENOMEM;
1747
1748 qp->create_type = MLX5_QP_EMPTY;
1749 }
1750
1751 if (is_sqp(init_attr->qp_type))
1752 qp->port = init_attr->port_num;
1753
1754 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1755
1756 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1757 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1758
1759 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1760 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1761 else
1762 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1763
1764
1765 if (qp->wq_sig)
1766 MLX5_SET(qpc, qpc, wq_signature, 1);
1767
1768 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1769 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1770
1771 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1772 MLX5_SET(qpc, qpc, cd_master, 1);
1773 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1774 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1775 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1776 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1777
1778 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1779 int rcqe_sz;
1780 int scqe_sz;
1781
1782 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1783 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1784
1785 if (rcqe_sz == 128)
1786 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1787 else
1788 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1789
1790 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1791 if (scqe_sz == 128)
1792 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1793 else
1794 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1795 }
1796 }
1797
1798 if (qp->rq.wqe_cnt) {
1799 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1800 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1801 }
1802
1803 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1804
1805 if (qp->sq.wqe_cnt) {
1806 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1807 } else {
1808 MLX5_SET(qpc, qpc, no_sq, 1);
1809 if (init_attr->srq &&
1810 init_attr->srq->srq_type == IB_SRQT_TM)
1811 MLX5_SET(qpc, qpc, offload_type,
1812 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1813 }
1814
1815 /* Set default resources */
1816 switch (init_attr->qp_type) {
1817 case IB_QPT_XRC_TGT:
1818 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1819 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1820 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1821 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1822 break;
1823 case IB_QPT_XRC_INI:
1824 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1825 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1826 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1827 break;
1828 default:
1829 if (init_attr->srq) {
1830 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1831 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1832 } else {
1833 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1834 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1835 }
1836 }
1837
1838 if (init_attr->send_cq)
1839 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1840
1841 if (init_attr->recv_cq)
1842 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1843
1844 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1845
1846 /* 0xffffff means we ask to work with cqe version 0 */
1847 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1848 MLX5_SET(qpc, qpc, user_index, uidx);
1849
1850 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1851 if (init_attr->qp_type == IB_QPT_UD &&
1852 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1853 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1854 qp->flags |= MLX5_IB_QP_LSO;
1855 }
1856
1857 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1858 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1859 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1860 err = -EOPNOTSUPP;
1861 goto err;
1862 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1863 MLX5_SET(qpc, qpc, end_padding_mode,
1864 MLX5_WQ_END_PAD_MODE_ALIGN);
1865 } else {
1866 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1867 }
1868 }
1869
1870 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1871 qp->flags & MLX5_IB_QP_UNDERLAY) {
1872 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1873 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1874 err = create_raw_packet_qp(dev, qp, in, pd);
1875 } else {
1876 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1877 }
1878
1879 if (err) {
1880 mlx5_ib_dbg(dev, "create qp failed\n");
1881 goto err_create;
1882 }
1883
1884 kvfree(in);
1885
1886 base->container_mibqp = qp;
1887 base->mqp.event = mlx5_ib_qp_event;
1888
1889 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1890 &send_cq, &recv_cq);
1891 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1892 mlx5_ib_lock_cqs(send_cq, recv_cq);
1893 /* Maintain device to QPs access, needed for further handling via reset
1894 * flow
1895 */
1896 list_add_tail(&qp->qps_list, &dev->qp_list);
1897 /* Maintain CQ to QPs access, needed for further handling via reset flow
1898 */
1899 if (send_cq)
1900 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1901 if (recv_cq)
1902 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1903 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1904 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1905
1906 return 0;
1907
1908 err_create:
1909 if (qp->create_type == MLX5_QP_USER)
1910 destroy_qp_user(dev, pd, qp, base);
1911 else if (qp->create_type == MLX5_QP_KERNEL)
1912 destroy_qp_kernel(dev, qp);
1913
1914 err:
1915 kvfree(in);
1916 return err;
1917 }
1918
1919 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1920 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1921 {
1922 if (send_cq) {
1923 if (recv_cq) {
1924 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1925 spin_lock(&send_cq->lock);
1926 spin_lock_nested(&recv_cq->lock,
1927 SINGLE_DEPTH_NESTING);
1928 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1929 spin_lock(&send_cq->lock);
1930 __acquire(&recv_cq->lock);
1931 } else {
1932 spin_lock(&recv_cq->lock);
1933 spin_lock_nested(&send_cq->lock,
1934 SINGLE_DEPTH_NESTING);
1935 }
1936 } else {
1937 spin_lock(&send_cq->lock);
1938 __acquire(&recv_cq->lock);
1939 }
1940 } else if (recv_cq) {
1941 spin_lock(&recv_cq->lock);
1942 __acquire(&send_cq->lock);
1943 } else {
1944 __acquire(&send_cq->lock);
1945 __acquire(&recv_cq->lock);
1946 }
1947 }
1948
1949 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1950 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1951 {
1952 if (send_cq) {
1953 if (recv_cq) {
1954 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1955 spin_unlock(&recv_cq->lock);
1956 spin_unlock(&send_cq->lock);
1957 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1958 __release(&recv_cq->lock);
1959 spin_unlock(&send_cq->lock);
1960 } else {
1961 spin_unlock(&send_cq->lock);
1962 spin_unlock(&recv_cq->lock);
1963 }
1964 } else {
1965 __release(&recv_cq->lock);
1966 spin_unlock(&send_cq->lock);
1967 }
1968 } else if (recv_cq) {
1969 __release(&send_cq->lock);
1970 spin_unlock(&recv_cq->lock);
1971 } else {
1972 __release(&recv_cq->lock);
1973 __release(&send_cq->lock);
1974 }
1975 }
1976
1977 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1978 {
1979 return to_mpd(qp->ibqp.pd);
1980 }
1981
1982 static void get_cqs(enum ib_qp_type qp_type,
1983 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1984 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1985 {
1986 switch (qp_type) {
1987 case IB_QPT_XRC_TGT:
1988 *send_cq = NULL;
1989 *recv_cq = NULL;
1990 break;
1991 case MLX5_IB_QPT_REG_UMR:
1992 case IB_QPT_XRC_INI:
1993 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1994 *recv_cq = NULL;
1995 break;
1996
1997 case IB_QPT_SMI:
1998 case MLX5_IB_QPT_HW_GSI:
1999 case IB_QPT_RC:
2000 case IB_QPT_UC:
2001 case IB_QPT_UD:
2002 case IB_QPT_RAW_IPV6:
2003 case IB_QPT_RAW_ETHERTYPE:
2004 case IB_QPT_RAW_PACKET:
2005 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2006 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2007 break;
2008
2009 case IB_QPT_MAX:
2010 default:
2011 *send_cq = NULL;
2012 *recv_cq = NULL;
2013 break;
2014 }
2015 }
2016
2017 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2018 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2019 u8 lag_tx_affinity);
2020
2021 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2022 {
2023 struct mlx5_ib_cq *send_cq, *recv_cq;
2024 struct mlx5_ib_qp_base *base;
2025 unsigned long flags;
2026 int err;
2027
2028 if (qp->ibqp.rwq_ind_tbl) {
2029 destroy_rss_raw_qp_tir(dev, qp);
2030 return;
2031 }
2032
2033 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2034 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2035 &qp->raw_packet_qp.rq.base :
2036 &qp->trans_qp.base;
2037
2038 if (qp->state != IB_QPS_RESET) {
2039 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2040 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2041 err = mlx5_core_qp_modify(dev->mdev,
2042 MLX5_CMD_OP_2RST_QP, 0,
2043 NULL, &base->mqp);
2044 } else {
2045 struct mlx5_modify_raw_qp_param raw_qp_param = {
2046 .operation = MLX5_CMD_OP_2RST_QP
2047 };
2048
2049 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2050 }
2051 if (err)
2052 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2053 base->mqp.qpn);
2054 }
2055
2056 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2057 &send_cq, &recv_cq);
2058
2059 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2060 mlx5_ib_lock_cqs(send_cq, recv_cq);
2061 /* del from lists under both locks above to protect reset flow paths */
2062 list_del(&qp->qps_list);
2063 if (send_cq)
2064 list_del(&qp->cq_send_list);
2065
2066 if (recv_cq)
2067 list_del(&qp->cq_recv_list);
2068
2069 if (qp->create_type == MLX5_QP_KERNEL) {
2070 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2071 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2072 if (send_cq != recv_cq)
2073 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2074 NULL);
2075 }
2076 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2077 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2078
2079 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2080 qp->flags & MLX5_IB_QP_UNDERLAY) {
2081 destroy_raw_packet_qp(dev, qp);
2082 } else {
2083 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2084 if (err)
2085 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2086 base->mqp.qpn);
2087 }
2088
2089 if (qp->create_type == MLX5_QP_KERNEL)
2090 destroy_qp_kernel(dev, qp);
2091 else if (qp->create_type == MLX5_QP_USER)
2092 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2093 }
2094
2095 static const char *ib_qp_type_str(enum ib_qp_type type)
2096 {
2097 switch (type) {
2098 case IB_QPT_SMI:
2099 return "IB_QPT_SMI";
2100 case IB_QPT_GSI:
2101 return "IB_QPT_GSI";
2102 case IB_QPT_RC:
2103 return "IB_QPT_RC";
2104 case IB_QPT_UC:
2105 return "IB_QPT_UC";
2106 case IB_QPT_UD:
2107 return "IB_QPT_UD";
2108 case IB_QPT_RAW_IPV6:
2109 return "IB_QPT_RAW_IPV6";
2110 case IB_QPT_RAW_ETHERTYPE:
2111 return "IB_QPT_RAW_ETHERTYPE";
2112 case IB_QPT_XRC_INI:
2113 return "IB_QPT_XRC_INI";
2114 case IB_QPT_XRC_TGT:
2115 return "IB_QPT_XRC_TGT";
2116 case IB_QPT_RAW_PACKET:
2117 return "IB_QPT_RAW_PACKET";
2118 case MLX5_IB_QPT_REG_UMR:
2119 return "MLX5_IB_QPT_REG_UMR";
2120 case IB_QPT_DRIVER:
2121 return "IB_QPT_DRIVER";
2122 case IB_QPT_MAX:
2123 default:
2124 return "Invalid QP type";
2125 }
2126 }
2127
2128 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2129 struct ib_qp_init_attr *attr,
2130 struct mlx5_ib_create_qp *ucmd)
2131 {
2132 struct mlx5_ib_dev *dev;
2133 struct mlx5_ib_qp *qp;
2134 int err = 0;
2135 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2136 void *dctc;
2137
2138 if (!attr->srq || !attr->recv_cq)
2139 return ERR_PTR(-EINVAL);
2140
2141 dev = to_mdev(pd->device);
2142
2143 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2144 ucmd, sizeof(*ucmd), &uidx);
2145 if (err)
2146 return ERR_PTR(err);
2147
2148 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2149 if (!qp)
2150 return ERR_PTR(-ENOMEM);
2151
2152 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2153 if (!qp->dct.in) {
2154 err = -ENOMEM;
2155 goto err_free;
2156 }
2157
2158 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2159 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2160 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2161 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2162 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2163 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2164 MLX5_SET(dctc, dctc, user_index, uidx);
2165
2166 qp->state = IB_QPS_RESET;
2167
2168 return &qp->ibqp;
2169 err_free:
2170 kfree(qp);
2171 return ERR_PTR(err);
2172 }
2173
2174 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2175 struct ib_qp_init_attr *init_attr,
2176 struct mlx5_ib_create_qp *ucmd,
2177 struct ib_udata *udata)
2178 {
2179 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2180 int err;
2181
2182 if (!udata)
2183 return -EINVAL;
2184
2185 if (udata->inlen < sizeof(*ucmd)) {
2186 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2187 return -EINVAL;
2188 }
2189 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2190 if (err)
2191 return err;
2192
2193 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2194 init_attr->qp_type = MLX5_IB_QPT_DCI;
2195 } else {
2196 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2197 init_attr->qp_type = MLX5_IB_QPT_DCT;
2198 } else {
2199 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2200 return -EINVAL;
2201 }
2202 }
2203
2204 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2205 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2206 return -EOPNOTSUPP;
2207 }
2208
2209 return 0;
2210 }
2211
2212 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2213 struct ib_qp_init_attr *verbs_init_attr,
2214 struct ib_udata *udata)
2215 {
2216 struct mlx5_ib_dev *dev;
2217 struct mlx5_ib_qp *qp;
2218 u16 xrcdn = 0;
2219 int err;
2220 struct ib_qp_init_attr mlx_init_attr;
2221 struct ib_qp_init_attr *init_attr = verbs_init_attr;
2222
2223 if (pd) {
2224 dev = to_mdev(pd->device);
2225
2226 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2227 if (!pd->uobject) {
2228 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2229 return ERR_PTR(-EINVAL);
2230 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2231 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2232 return ERR_PTR(-EINVAL);
2233 }
2234 }
2235 } else {
2236 /* being cautious here */
2237 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2238 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2239 pr_warn("%s: no PD for transport %s\n", __func__,
2240 ib_qp_type_str(init_attr->qp_type));
2241 return ERR_PTR(-EINVAL);
2242 }
2243 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2244 }
2245
2246 if (init_attr->qp_type == IB_QPT_DRIVER) {
2247 struct mlx5_ib_create_qp ucmd;
2248
2249 init_attr = &mlx_init_attr;
2250 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2251 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2252 if (err)
2253 return ERR_PTR(err);
2254
2255 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2256 if (init_attr->cap.max_recv_wr ||
2257 init_attr->cap.max_recv_sge) {
2258 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2259 return ERR_PTR(-EINVAL);
2260 }
2261 } else {
2262 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2263 }
2264 }
2265
2266 switch (init_attr->qp_type) {
2267 case IB_QPT_XRC_TGT:
2268 case IB_QPT_XRC_INI:
2269 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2270 mlx5_ib_dbg(dev, "XRC not supported\n");
2271 return ERR_PTR(-ENOSYS);
2272 }
2273 init_attr->recv_cq = NULL;
2274 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2275 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2276 init_attr->send_cq = NULL;
2277 }
2278
2279 /* fall through */
2280 case IB_QPT_RAW_PACKET:
2281 case IB_QPT_RC:
2282 case IB_QPT_UC:
2283 case IB_QPT_UD:
2284 case IB_QPT_SMI:
2285 case MLX5_IB_QPT_HW_GSI:
2286 case MLX5_IB_QPT_REG_UMR:
2287 case MLX5_IB_QPT_DCI:
2288 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2289 if (!qp)
2290 return ERR_PTR(-ENOMEM);
2291
2292 err = create_qp_common(dev, pd, init_attr, udata, qp);
2293 if (err) {
2294 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2295 kfree(qp);
2296 return ERR_PTR(err);
2297 }
2298
2299 if (is_qp0(init_attr->qp_type))
2300 qp->ibqp.qp_num = 0;
2301 else if (is_qp1(init_attr->qp_type))
2302 qp->ibqp.qp_num = 1;
2303 else
2304 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2305
2306 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2307 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2308 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2309 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2310
2311 qp->trans_qp.xrcdn = xrcdn;
2312
2313 break;
2314
2315 case IB_QPT_GSI:
2316 return mlx5_ib_gsi_create_qp(pd, init_attr);
2317
2318 case IB_QPT_RAW_IPV6:
2319 case IB_QPT_RAW_ETHERTYPE:
2320 case IB_QPT_MAX:
2321 default:
2322 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2323 init_attr->qp_type);
2324 /* Don't support raw QPs */
2325 return ERR_PTR(-EINVAL);
2326 }
2327
2328 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2329 qp->qp_sub_type = init_attr->qp_type;
2330
2331 return &qp->ibqp;
2332 }
2333
2334 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2335 {
2336 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2337
2338 if (mqp->state == IB_QPS_RTR) {
2339 int err;
2340
2341 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2342 if (err) {
2343 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2344 return err;
2345 }
2346 }
2347
2348 kfree(mqp->dct.in);
2349 kfree(mqp);
2350 return 0;
2351 }
2352
2353 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2354 {
2355 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2356 struct mlx5_ib_qp *mqp = to_mqp(qp);
2357
2358 if (unlikely(qp->qp_type == IB_QPT_GSI))
2359 return mlx5_ib_gsi_destroy_qp(qp);
2360
2361 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2362 return mlx5_ib_destroy_dct(mqp);
2363
2364 destroy_qp_common(dev, mqp);
2365
2366 kfree(mqp);
2367
2368 return 0;
2369 }
2370
2371 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2372 int attr_mask)
2373 {
2374 u32 hw_access_flags = 0;
2375 u8 dest_rd_atomic;
2376 u32 access_flags;
2377
2378 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2379 dest_rd_atomic = attr->max_dest_rd_atomic;
2380 else
2381 dest_rd_atomic = qp->trans_qp.resp_depth;
2382
2383 if (attr_mask & IB_QP_ACCESS_FLAGS)
2384 access_flags = attr->qp_access_flags;
2385 else
2386 access_flags = qp->trans_qp.atomic_rd_en;
2387
2388 if (!dest_rd_atomic)
2389 access_flags &= IB_ACCESS_REMOTE_WRITE;
2390
2391 if (access_flags & IB_ACCESS_REMOTE_READ)
2392 hw_access_flags |= MLX5_QP_BIT_RRE;
2393 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2394 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2395 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2396 hw_access_flags |= MLX5_QP_BIT_RWE;
2397
2398 return cpu_to_be32(hw_access_flags);
2399 }
2400
2401 enum {
2402 MLX5_PATH_FLAG_FL = 1 << 0,
2403 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2404 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2405 };
2406
2407 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2408 {
2409 if (rate == IB_RATE_PORT_CURRENT) {
2410 return 0;
2411 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2412 return -EINVAL;
2413 } else {
2414 while (rate != IB_RATE_2_5_GBPS &&
2415 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2416 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2417 --rate;
2418 }
2419
2420 return rate + MLX5_STAT_RATE_OFFSET;
2421 }
2422
2423 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2424 struct mlx5_ib_sq *sq, u8 sl)
2425 {
2426 void *in;
2427 void *tisc;
2428 int inlen;
2429 int err;
2430
2431 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2432 in = kvzalloc(inlen, GFP_KERNEL);
2433 if (!in)
2434 return -ENOMEM;
2435
2436 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2437
2438 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2439 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2440
2441 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2442
2443 kvfree(in);
2444
2445 return err;
2446 }
2447
2448 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2449 struct mlx5_ib_sq *sq, u8 tx_affinity)
2450 {
2451 void *in;
2452 void *tisc;
2453 int inlen;
2454 int err;
2455
2456 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2457 in = kvzalloc(inlen, GFP_KERNEL);
2458 if (!in)
2459 return -ENOMEM;
2460
2461 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2462
2463 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2464 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2465
2466 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2467
2468 kvfree(in);
2469
2470 return err;
2471 }
2472
2473 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2474 const struct rdma_ah_attr *ah,
2475 struct mlx5_qp_path *path, u8 port, int attr_mask,
2476 u32 path_flags, const struct ib_qp_attr *attr,
2477 bool alt)
2478 {
2479 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2480 int err;
2481 enum ib_gid_type gid_type;
2482 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2483 u8 sl = rdma_ah_get_sl(ah);
2484
2485 if (attr_mask & IB_QP_PKEY_INDEX)
2486 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2487 attr->pkey_index);
2488
2489 if (ah_flags & IB_AH_GRH) {
2490 if (grh->sgid_index >=
2491 dev->mdev->port_caps[port - 1].gid_table_len) {
2492 pr_err("sgid_index (%u) too large. max is %d\n",
2493 grh->sgid_index,
2494 dev->mdev->port_caps[port - 1].gid_table_len);
2495 return -EINVAL;
2496 }
2497 }
2498
2499 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2500 if (!(ah_flags & IB_AH_GRH))
2501 return -EINVAL;
2502 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2503 &gid_type);
2504 if (err)
2505 return err;
2506 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2507 if (qp->ibqp.qp_type == IB_QPT_RC ||
2508 qp->ibqp.qp_type == IB_QPT_UC ||
2509 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2510 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2511 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2512 grh->sgid_index);
2513 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2514 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2515 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2516 } else {
2517 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2518 path->fl_free_ar |=
2519 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2520 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2521 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2522 if (ah_flags & IB_AH_GRH)
2523 path->grh_mlid |= 1 << 7;
2524 path->dci_cfi_prio_sl = sl & 0xf;
2525 }
2526
2527 if (ah_flags & IB_AH_GRH) {
2528 path->mgid_index = grh->sgid_index;
2529 path->hop_limit = grh->hop_limit;
2530 path->tclass_flowlabel =
2531 cpu_to_be32((grh->traffic_class << 20) |
2532 (grh->flow_label));
2533 memcpy(path->rgid, grh->dgid.raw, 16);
2534 }
2535
2536 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2537 if (err < 0)
2538 return err;
2539 path->static_rate = err;
2540 path->port = port;
2541
2542 if (attr_mask & IB_QP_TIMEOUT)
2543 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2544
2545 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2546 return modify_raw_packet_eth_prio(dev->mdev,
2547 &qp->raw_packet_qp.sq,
2548 sl & 0xf);
2549
2550 return 0;
2551 }
2552
2553 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2554 [MLX5_QP_STATE_INIT] = {
2555 [MLX5_QP_STATE_INIT] = {
2556 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2557 MLX5_QP_OPTPAR_RAE |
2558 MLX5_QP_OPTPAR_RWE |
2559 MLX5_QP_OPTPAR_PKEY_INDEX |
2560 MLX5_QP_OPTPAR_PRI_PORT,
2561 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2562 MLX5_QP_OPTPAR_PKEY_INDEX |
2563 MLX5_QP_OPTPAR_PRI_PORT,
2564 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2565 MLX5_QP_OPTPAR_Q_KEY |
2566 MLX5_QP_OPTPAR_PRI_PORT,
2567 },
2568 [MLX5_QP_STATE_RTR] = {
2569 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2570 MLX5_QP_OPTPAR_RRE |
2571 MLX5_QP_OPTPAR_RAE |
2572 MLX5_QP_OPTPAR_RWE |
2573 MLX5_QP_OPTPAR_PKEY_INDEX,
2574 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2575 MLX5_QP_OPTPAR_RWE |
2576 MLX5_QP_OPTPAR_PKEY_INDEX,
2577 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2578 MLX5_QP_OPTPAR_Q_KEY,
2579 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2580 MLX5_QP_OPTPAR_Q_KEY,
2581 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2582 MLX5_QP_OPTPAR_RRE |
2583 MLX5_QP_OPTPAR_RAE |
2584 MLX5_QP_OPTPAR_RWE |
2585 MLX5_QP_OPTPAR_PKEY_INDEX,
2586 },
2587 },
2588 [MLX5_QP_STATE_RTR] = {
2589 [MLX5_QP_STATE_RTS] = {
2590 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2591 MLX5_QP_OPTPAR_RRE |
2592 MLX5_QP_OPTPAR_RAE |
2593 MLX5_QP_OPTPAR_RWE |
2594 MLX5_QP_OPTPAR_PM_STATE |
2595 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2596 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2597 MLX5_QP_OPTPAR_RWE |
2598 MLX5_QP_OPTPAR_PM_STATE,
2599 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2600 },
2601 },
2602 [MLX5_QP_STATE_RTS] = {
2603 [MLX5_QP_STATE_RTS] = {
2604 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2605 MLX5_QP_OPTPAR_RAE |
2606 MLX5_QP_OPTPAR_RWE |
2607 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2608 MLX5_QP_OPTPAR_PM_STATE |
2609 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2610 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2611 MLX5_QP_OPTPAR_PM_STATE |
2612 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2613 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2614 MLX5_QP_OPTPAR_SRQN |
2615 MLX5_QP_OPTPAR_CQN_RCV,
2616 },
2617 },
2618 [MLX5_QP_STATE_SQER] = {
2619 [MLX5_QP_STATE_RTS] = {
2620 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2621 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2622 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2623 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2624 MLX5_QP_OPTPAR_RWE |
2625 MLX5_QP_OPTPAR_RAE |
2626 MLX5_QP_OPTPAR_RRE,
2627 },
2628 },
2629 };
2630
2631 static int ib_nr_to_mlx5_nr(int ib_mask)
2632 {
2633 switch (ib_mask) {
2634 case IB_QP_STATE:
2635 return 0;
2636 case IB_QP_CUR_STATE:
2637 return 0;
2638 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2639 return 0;
2640 case IB_QP_ACCESS_FLAGS:
2641 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2642 MLX5_QP_OPTPAR_RAE;
2643 case IB_QP_PKEY_INDEX:
2644 return MLX5_QP_OPTPAR_PKEY_INDEX;
2645 case IB_QP_PORT:
2646 return MLX5_QP_OPTPAR_PRI_PORT;
2647 case IB_QP_QKEY:
2648 return MLX5_QP_OPTPAR_Q_KEY;
2649 case IB_QP_AV:
2650 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2651 MLX5_QP_OPTPAR_PRI_PORT;
2652 case IB_QP_PATH_MTU:
2653 return 0;
2654 case IB_QP_TIMEOUT:
2655 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2656 case IB_QP_RETRY_CNT:
2657 return MLX5_QP_OPTPAR_RETRY_COUNT;
2658 case IB_QP_RNR_RETRY:
2659 return MLX5_QP_OPTPAR_RNR_RETRY;
2660 case IB_QP_RQ_PSN:
2661 return 0;
2662 case IB_QP_MAX_QP_RD_ATOMIC:
2663 return MLX5_QP_OPTPAR_SRA_MAX;
2664 case IB_QP_ALT_PATH:
2665 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2666 case IB_QP_MIN_RNR_TIMER:
2667 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2668 case IB_QP_SQ_PSN:
2669 return 0;
2670 case IB_QP_MAX_DEST_RD_ATOMIC:
2671 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2672 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2673 case IB_QP_PATH_MIG_STATE:
2674 return MLX5_QP_OPTPAR_PM_STATE;
2675 case IB_QP_CAP:
2676 return 0;
2677 case IB_QP_DEST_QPN:
2678 return 0;
2679 }
2680 return 0;
2681 }
2682
2683 static int ib_mask_to_mlx5_opt(int ib_mask)
2684 {
2685 int result = 0;
2686 int i;
2687
2688 for (i = 0; i < 8 * sizeof(int); i++) {
2689 if ((1 << i) & ib_mask)
2690 result |= ib_nr_to_mlx5_nr(1 << i);
2691 }
2692
2693 return result;
2694 }
2695
2696 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2697 struct mlx5_ib_rq *rq, int new_state,
2698 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2699 {
2700 void *in;
2701 void *rqc;
2702 int inlen;
2703 int err;
2704
2705 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2706 in = kvzalloc(inlen, GFP_KERNEL);
2707 if (!in)
2708 return -ENOMEM;
2709
2710 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2711
2712 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2713 MLX5_SET(rqc, rqc, state, new_state);
2714
2715 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2716 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2717 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2718 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2719 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2720 } else
2721 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2722 dev->ib_dev.name);
2723 }
2724
2725 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2726 if (err)
2727 goto out;
2728
2729 rq->state = new_state;
2730
2731 out:
2732 kvfree(in);
2733 return err;
2734 }
2735
2736 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2737 struct mlx5_ib_sq *sq,
2738 int new_state,
2739 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2740 {
2741 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2742 u32 old_rate = ibqp->rate_limit;
2743 u32 new_rate = old_rate;
2744 u16 rl_index = 0;
2745 void *in;
2746 void *sqc;
2747 int inlen;
2748 int err;
2749
2750 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2751 in = kvzalloc(inlen, GFP_KERNEL);
2752 if (!in)
2753 return -ENOMEM;
2754
2755 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2756
2757 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2758 MLX5_SET(sqc, sqc, state, new_state);
2759
2760 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2761 if (new_state != MLX5_SQC_STATE_RDY)
2762 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2763 __func__);
2764 else
2765 new_rate = raw_qp_param->rate_limit;
2766 }
2767
2768 if (old_rate != new_rate) {
2769 if (new_rate) {
2770 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2771 if (err) {
2772 pr_err("Failed configuring rate %u: %d\n",
2773 new_rate, err);
2774 goto out;
2775 }
2776 }
2777
2778 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2779 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2780 }
2781
2782 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2783 if (err) {
2784 /* Remove new rate from table if failed */
2785 if (new_rate &&
2786 old_rate != new_rate)
2787 mlx5_rl_remove_rate(dev, new_rate);
2788 goto out;
2789 }
2790
2791 /* Only remove the old rate after new rate was set */
2792 if ((old_rate &&
2793 (old_rate != new_rate)) ||
2794 (new_state != MLX5_SQC_STATE_RDY))
2795 mlx5_rl_remove_rate(dev, old_rate);
2796
2797 ibqp->rate_limit = new_rate;
2798 sq->state = new_state;
2799
2800 out:
2801 kvfree(in);
2802 return err;
2803 }
2804
2805 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2806 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2807 u8 tx_affinity)
2808 {
2809 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2810 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2811 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2812 int modify_rq = !!qp->rq.wqe_cnt;
2813 int modify_sq = !!qp->sq.wqe_cnt;
2814 int rq_state;
2815 int sq_state;
2816 int err;
2817
2818 switch (raw_qp_param->operation) {
2819 case MLX5_CMD_OP_RST2INIT_QP:
2820 rq_state = MLX5_RQC_STATE_RDY;
2821 sq_state = MLX5_SQC_STATE_RDY;
2822 break;
2823 case MLX5_CMD_OP_2ERR_QP:
2824 rq_state = MLX5_RQC_STATE_ERR;
2825 sq_state = MLX5_SQC_STATE_ERR;
2826 break;
2827 case MLX5_CMD_OP_2RST_QP:
2828 rq_state = MLX5_RQC_STATE_RST;
2829 sq_state = MLX5_SQC_STATE_RST;
2830 break;
2831 case MLX5_CMD_OP_RTR2RTS_QP:
2832 case MLX5_CMD_OP_RTS2RTS_QP:
2833 if (raw_qp_param->set_mask ==
2834 MLX5_RAW_QP_RATE_LIMIT) {
2835 modify_rq = 0;
2836 sq_state = sq->state;
2837 } else {
2838 return raw_qp_param->set_mask ? -EINVAL : 0;
2839 }
2840 break;
2841 case MLX5_CMD_OP_INIT2INIT_QP:
2842 case MLX5_CMD_OP_INIT2RTR_QP:
2843 if (raw_qp_param->set_mask)
2844 return -EINVAL;
2845 else
2846 return 0;
2847 default:
2848 WARN_ON(1);
2849 return -EINVAL;
2850 }
2851
2852 if (modify_rq) {
2853 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2854 if (err)
2855 return err;
2856 }
2857
2858 if (modify_sq) {
2859 if (tx_affinity) {
2860 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2861 tx_affinity);
2862 if (err)
2863 return err;
2864 }
2865
2866 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2867 }
2868
2869 return 0;
2870 }
2871
2872 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2873 const struct ib_qp_attr *attr, int attr_mask,
2874 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2875 {
2876 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2877 [MLX5_QP_STATE_RST] = {
2878 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2879 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2880 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2881 },
2882 [MLX5_QP_STATE_INIT] = {
2883 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2884 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2885 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2886 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2887 },
2888 [MLX5_QP_STATE_RTR] = {
2889 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2890 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2891 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2892 },
2893 [MLX5_QP_STATE_RTS] = {
2894 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2895 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2896 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2897 },
2898 [MLX5_QP_STATE_SQD] = {
2899 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2900 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2901 },
2902 [MLX5_QP_STATE_SQER] = {
2903 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2904 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2905 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2906 },
2907 [MLX5_QP_STATE_ERR] = {
2908 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2909 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2910 }
2911 };
2912
2913 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2914 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2915 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2916 struct mlx5_ib_cq *send_cq, *recv_cq;
2917 struct mlx5_qp_context *context;
2918 struct mlx5_ib_pd *pd;
2919 struct mlx5_ib_port *mibport = NULL;
2920 enum mlx5_qp_state mlx5_cur, mlx5_new;
2921 enum mlx5_qp_optpar optpar;
2922 int mlx5_st;
2923 int err;
2924 u16 op;
2925 u8 tx_affinity = 0;
2926
2927 context = kzalloc(sizeof(*context), GFP_KERNEL);
2928 if (!context)
2929 return -ENOMEM;
2930
2931 err = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2932 qp->qp_sub_type : ibqp->qp_type);
2933 if (err < 0) {
2934 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2935 goto out;
2936 }
2937
2938 context->flags = cpu_to_be32(err << 16);
2939
2940 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2941 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2942 } else {
2943 switch (attr->path_mig_state) {
2944 case IB_MIG_MIGRATED:
2945 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2946 break;
2947 case IB_MIG_REARM:
2948 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2949 break;
2950 case IB_MIG_ARMED:
2951 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2952 break;
2953 }
2954 }
2955
2956 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2957 if ((ibqp->qp_type == IB_QPT_RC) ||
2958 (ibqp->qp_type == IB_QPT_UD &&
2959 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2960 (ibqp->qp_type == IB_QPT_UC) ||
2961 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2962 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2963 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2964 if (mlx5_lag_is_active(dev->mdev)) {
2965 u8 p = mlx5_core_native_port_num(dev->mdev);
2966 tx_affinity = (unsigned int)atomic_add_return(1,
2967 &dev->roce[p].next_port) %
2968 MLX5_MAX_PORTS + 1;
2969 context->flags |= cpu_to_be32(tx_affinity << 24);
2970 }
2971 }
2972 }
2973
2974 if (is_sqp(ibqp->qp_type)) {
2975 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2976 } else if ((ibqp->qp_type == IB_QPT_UD &&
2977 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
2978 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2979 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2980 } else if (attr_mask & IB_QP_PATH_MTU) {
2981 if (attr->path_mtu < IB_MTU_256 ||
2982 attr->path_mtu > IB_MTU_4096) {
2983 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2984 err = -EINVAL;
2985 goto out;
2986 }
2987 context->mtu_msgmax = (attr->path_mtu << 5) |
2988 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2989 }
2990
2991 if (attr_mask & IB_QP_DEST_QPN)
2992 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2993
2994 if (attr_mask & IB_QP_PKEY_INDEX)
2995 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2996
2997 /* todo implement counter_index functionality */
2998
2999 if (is_sqp(ibqp->qp_type))
3000 context->pri_path.port = qp->port;
3001
3002 if (attr_mask & IB_QP_PORT)
3003 context->pri_path.port = attr->port_num;
3004
3005 if (attr_mask & IB_QP_AV) {
3006 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3007 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3008 attr_mask, 0, attr, false);
3009 if (err)
3010 goto out;
3011 }
3012
3013 if (attr_mask & IB_QP_TIMEOUT)
3014 context->pri_path.ackto_lt |= attr->timeout << 3;
3015
3016 if (attr_mask & IB_QP_ALT_PATH) {
3017 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3018 &context->alt_path,
3019 attr->alt_port_num,
3020 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3021 0, attr, true);
3022 if (err)
3023 goto out;
3024 }
3025
3026 pd = get_pd(qp);
3027 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3028 &send_cq, &recv_cq);
3029
3030 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3031 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3032 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3033 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3034
3035 if (attr_mask & IB_QP_RNR_RETRY)
3036 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3037
3038 if (attr_mask & IB_QP_RETRY_CNT)
3039 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3040
3041 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3042 if (attr->max_rd_atomic)
3043 context->params1 |=
3044 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3045 }
3046
3047 if (attr_mask & IB_QP_SQ_PSN)
3048 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3049
3050 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3051 if (attr->max_dest_rd_atomic)
3052 context->params2 |=
3053 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3054 }
3055
3056 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3057 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3058
3059 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3060 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3061
3062 if (attr_mask & IB_QP_RQ_PSN)
3063 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3064
3065 if (attr_mask & IB_QP_QKEY)
3066 context->qkey = cpu_to_be32(attr->qkey);
3067
3068 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3069 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3070
3071 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3072 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3073 qp->port) - 1;
3074
3075 /* Underlay port should be used - index 0 function per port */
3076 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3077 port_num = 0;
3078
3079 mibport = &dev->port[port_num];
3080 context->qp_counter_set_usr_page |=
3081 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3082 }
3083
3084 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3085 context->sq_crq_size |= cpu_to_be16(1 << 4);
3086
3087 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3088 context->deth_sqpn = cpu_to_be32(1);
3089
3090 mlx5_cur = to_mlx5_state(cur_state);
3091 mlx5_new = to_mlx5_state(new_state);
3092 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3093 qp->qp_sub_type : ibqp->qp_type);
3094 if (mlx5_st < 0)
3095 goto out;
3096
3097 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3098 !optab[mlx5_cur][mlx5_new])
3099 goto out;
3100
3101 op = optab[mlx5_cur][mlx5_new];
3102 optpar = ib_mask_to_mlx5_opt(attr_mask);
3103 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3104
3105 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3106 qp->flags & MLX5_IB_QP_UNDERLAY) {
3107 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3108
3109 raw_qp_param.operation = op;
3110 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3111 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3112 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3113 }
3114
3115 if (attr_mask & IB_QP_RATE_LIMIT) {
3116 raw_qp_param.rate_limit = attr->rate_limit;
3117 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3118 }
3119
3120 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3121 } else {
3122 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3123 &base->mqp);
3124 }
3125
3126 if (err)
3127 goto out;
3128
3129 qp->state = new_state;
3130
3131 if (attr_mask & IB_QP_ACCESS_FLAGS)
3132 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3133 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3134 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3135 if (attr_mask & IB_QP_PORT)
3136 qp->port = attr->port_num;
3137 if (attr_mask & IB_QP_ALT_PATH)
3138 qp->trans_qp.alt_port = attr->alt_port_num;
3139
3140 /*
3141 * If we moved a kernel QP to RESET, clean up all old CQ
3142 * entries and reinitialize the QP.
3143 */
3144 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3145 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3146 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3147 if (send_cq != recv_cq)
3148 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3149
3150 qp->rq.head = 0;
3151 qp->rq.tail = 0;
3152 qp->sq.head = 0;
3153 qp->sq.tail = 0;
3154 qp->sq.cur_post = 0;
3155 qp->sq.last_poll = 0;
3156 qp->db.db[MLX5_RCV_DBR] = 0;
3157 qp->db.db[MLX5_SND_DBR] = 0;
3158 }
3159
3160 out:
3161 kfree(context);
3162 return err;
3163 }
3164
3165 static inline bool is_valid_mask(int mask, int req, int opt)
3166 {
3167 if ((mask & req) != req)
3168 return false;
3169
3170 if (mask & ~(req | opt))
3171 return false;
3172
3173 return true;
3174 }
3175
3176 /* check valid transition for driver QP types
3177 * for now the only QP type that this function supports is DCI
3178 */
3179 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3180 enum ib_qp_attr_mask attr_mask)
3181 {
3182 int req = IB_QP_STATE;
3183 int opt = 0;
3184
3185 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3186 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3187 return is_valid_mask(attr_mask, req, opt);
3188 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3189 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3190 return is_valid_mask(attr_mask, req, opt);
3191 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3192 req |= IB_QP_PATH_MTU;
3193 opt = IB_QP_PKEY_INDEX;
3194 return is_valid_mask(attr_mask, req, opt);
3195 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3196 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3197 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3198 opt = IB_QP_MIN_RNR_TIMER;
3199 return is_valid_mask(attr_mask, req, opt);
3200 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3201 opt = IB_QP_MIN_RNR_TIMER;
3202 return is_valid_mask(attr_mask, req, opt);
3203 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3204 return is_valid_mask(attr_mask, req, opt);
3205 }
3206 return false;
3207 }
3208
3209 /* mlx5_ib_modify_dct: modify a DCT QP
3210 * valid transitions are:
3211 * RESET to INIT: must set access_flags, pkey_index and port
3212 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3213 * mtu, gid_index and hop_limit
3214 * Other transitions and attributes are illegal
3215 */
3216 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3217 int attr_mask, struct ib_udata *udata)
3218 {
3219 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3220 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3221 enum ib_qp_state cur_state, new_state;
3222 int err = 0;
3223 int required = IB_QP_STATE;
3224 void *dctc;
3225
3226 if (!(attr_mask & IB_QP_STATE))
3227 return -EINVAL;
3228
3229 cur_state = qp->state;
3230 new_state = attr->qp_state;
3231
3232 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3233 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3234 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3235 if (!is_valid_mask(attr_mask, required, 0))
3236 return -EINVAL;
3237
3238 if (attr->port_num == 0 ||
3239 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3240 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3241 attr->port_num, dev->num_ports);
3242 return -EINVAL;
3243 }
3244 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3245 MLX5_SET(dctc, dctc, rre, 1);
3246 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3247 MLX5_SET(dctc, dctc, rwe, 1);
3248 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3249 if (!mlx5_ib_dc_atomic_is_supported(dev))
3250 return -EOPNOTSUPP;
3251 MLX5_SET(dctc, dctc, rae, 1);
3252 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3253 }
3254 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3255 MLX5_SET(dctc, dctc, port, attr->port_num);
3256 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3257
3258 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3259 struct mlx5_ib_modify_qp_resp resp = {};
3260 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3261 sizeof(resp.dctn);
3262
3263 if (udata->outlen < min_resp_len)
3264 return -EINVAL;
3265 resp.response_length = min_resp_len;
3266
3267 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3268 if (!is_valid_mask(attr_mask, required, 0))
3269 return -EINVAL;
3270 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3271 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3272 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3273 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3274 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3275 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3276
3277 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3278 MLX5_ST_SZ_BYTES(create_dct_in));
3279 if (err)
3280 return err;
3281 resp.dctn = qp->dct.mdct.mqp.qpn;
3282 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3283 if (err) {
3284 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3285 return err;
3286 }
3287 } else {
3288 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3289 return -EINVAL;
3290 }
3291 if (err)
3292 qp->state = IB_QPS_ERR;
3293 else
3294 qp->state = new_state;
3295 return err;
3296 }
3297
3298 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3299 int attr_mask, struct ib_udata *udata)
3300 {
3301 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3302 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3303 enum ib_qp_type qp_type;
3304 enum ib_qp_state cur_state, new_state;
3305 int err = -EINVAL;
3306 int port;
3307 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3308
3309 if (ibqp->rwq_ind_tbl)
3310 return -ENOSYS;
3311
3312 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3313 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3314
3315 if (ibqp->qp_type == IB_QPT_DRIVER)
3316 qp_type = qp->qp_sub_type;
3317 else
3318 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3319 IB_QPT_GSI : ibqp->qp_type;
3320
3321 if (qp_type == MLX5_IB_QPT_DCT)
3322 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3323
3324 mutex_lock(&qp->mutex);
3325
3326 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3327 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3328
3329 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3330 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3331 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3332 }
3333
3334 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3335 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3336 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3337 attr_mask);
3338 goto out;
3339 }
3340 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3341 qp_type != MLX5_IB_QPT_DCI &&
3342 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3343 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3344 cur_state, new_state, ibqp->qp_type, attr_mask);
3345 goto out;
3346 } else if (qp_type == MLX5_IB_QPT_DCI &&
3347 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3348 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3349 cur_state, new_state, qp_type, attr_mask);
3350 goto out;
3351 }
3352
3353 if ((attr_mask & IB_QP_PORT) &&
3354 (attr->port_num == 0 ||
3355 attr->port_num > dev->num_ports)) {
3356 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3357 attr->port_num, dev->num_ports);
3358 goto out;
3359 }
3360
3361 if (attr_mask & IB_QP_PKEY_INDEX) {
3362 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3363 if (attr->pkey_index >=
3364 dev->mdev->port_caps[port - 1].pkey_table_len) {
3365 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3366 attr->pkey_index);
3367 goto out;
3368 }
3369 }
3370
3371 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3372 attr->max_rd_atomic >
3373 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3374 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3375 attr->max_rd_atomic);
3376 goto out;
3377 }
3378
3379 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3380 attr->max_dest_rd_atomic >
3381 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3382 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3383 attr->max_dest_rd_atomic);
3384 goto out;
3385 }
3386
3387 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3388 err = 0;
3389 goto out;
3390 }
3391
3392 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3393
3394 out:
3395 mutex_unlock(&qp->mutex);
3396 return err;
3397 }
3398
3399 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3400 {
3401 struct mlx5_ib_cq *cq;
3402 unsigned cur;
3403
3404 cur = wq->head - wq->tail;
3405 if (likely(cur + nreq < wq->max_post))
3406 return 0;
3407
3408 cq = to_mcq(ib_cq);
3409 spin_lock(&cq->lock);
3410 cur = wq->head - wq->tail;
3411 spin_unlock(&cq->lock);
3412
3413 return cur + nreq >= wq->max_post;
3414 }
3415
3416 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3417 u64 remote_addr, u32 rkey)
3418 {
3419 rseg->raddr = cpu_to_be64(remote_addr);
3420 rseg->rkey = cpu_to_be32(rkey);
3421 rseg->reserved = 0;
3422 }
3423
3424 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3425 struct ib_send_wr *wr, void *qend,
3426 struct mlx5_ib_qp *qp, int *size)
3427 {
3428 void *seg = eseg;
3429
3430 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3431
3432 if (wr->send_flags & IB_SEND_IP_CSUM)
3433 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3434 MLX5_ETH_WQE_L4_CSUM;
3435
3436 seg += sizeof(struct mlx5_wqe_eth_seg);
3437 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3438
3439 if (wr->opcode == IB_WR_LSO) {
3440 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3441 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3442 u64 left, leftlen, copysz;
3443 void *pdata = ud_wr->header;
3444
3445 left = ud_wr->hlen;
3446 eseg->mss = cpu_to_be16(ud_wr->mss);
3447 eseg->inline_hdr.sz = cpu_to_be16(left);
3448
3449 /*
3450 * check if there is space till the end of queue, if yes,
3451 * copy all in one shot, otherwise copy till the end of queue,
3452 * rollback and than the copy the left
3453 */
3454 leftlen = qend - (void *)eseg->inline_hdr.start;
3455 copysz = min_t(u64, leftlen, left);
3456
3457 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3458
3459 if (likely(copysz > size_of_inl_hdr_start)) {
3460 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3461 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3462 }
3463
3464 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3465 seg = mlx5_get_send_wqe(qp, 0);
3466 left -= copysz;
3467 pdata += copysz;
3468 memcpy(seg, pdata, left);
3469 seg += ALIGN(left, 16);
3470 *size += ALIGN(left, 16) / 16;
3471 }
3472 }
3473
3474 return seg;
3475 }
3476
3477 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3478 struct ib_send_wr *wr)
3479 {
3480 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3481 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3482 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3483 }
3484
3485 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3486 {
3487 dseg->byte_count = cpu_to_be32(sg->length);
3488 dseg->lkey = cpu_to_be32(sg->lkey);
3489 dseg->addr = cpu_to_be64(sg->addr);
3490 }
3491
3492 static u64 get_xlt_octo(u64 bytes)
3493 {
3494 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3495 MLX5_IB_UMR_OCTOWORD;
3496 }
3497
3498 static __be64 frwr_mkey_mask(void)
3499 {
3500 u64 result;
3501
3502 result = MLX5_MKEY_MASK_LEN |
3503 MLX5_MKEY_MASK_PAGE_SIZE |
3504 MLX5_MKEY_MASK_START_ADDR |
3505 MLX5_MKEY_MASK_EN_RINVAL |
3506 MLX5_MKEY_MASK_KEY |
3507 MLX5_MKEY_MASK_LR |
3508 MLX5_MKEY_MASK_LW |
3509 MLX5_MKEY_MASK_RR |
3510 MLX5_MKEY_MASK_RW |
3511 MLX5_MKEY_MASK_A |
3512 MLX5_MKEY_MASK_SMALL_FENCE |
3513 MLX5_MKEY_MASK_FREE;
3514
3515 return cpu_to_be64(result);
3516 }
3517
3518 static __be64 sig_mkey_mask(void)
3519 {
3520 u64 result;
3521
3522 result = MLX5_MKEY_MASK_LEN |
3523 MLX5_MKEY_MASK_PAGE_SIZE |
3524 MLX5_MKEY_MASK_START_ADDR |
3525 MLX5_MKEY_MASK_EN_SIGERR |
3526 MLX5_MKEY_MASK_EN_RINVAL |
3527 MLX5_MKEY_MASK_KEY |
3528 MLX5_MKEY_MASK_LR |
3529 MLX5_MKEY_MASK_LW |
3530 MLX5_MKEY_MASK_RR |
3531 MLX5_MKEY_MASK_RW |
3532 MLX5_MKEY_MASK_SMALL_FENCE |
3533 MLX5_MKEY_MASK_FREE |
3534 MLX5_MKEY_MASK_BSF_EN;
3535
3536 return cpu_to_be64(result);
3537 }
3538
3539 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3540 struct mlx5_ib_mr *mr)
3541 {
3542 int size = mr->ndescs * mr->desc_size;
3543
3544 memset(umr, 0, sizeof(*umr));
3545
3546 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3547 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3548 umr->mkey_mask = frwr_mkey_mask();
3549 }
3550
3551 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3552 {
3553 memset(umr, 0, sizeof(*umr));
3554 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3555 umr->flags = MLX5_UMR_INLINE;
3556 }
3557
3558 static __be64 get_umr_enable_mr_mask(void)
3559 {
3560 u64 result;
3561
3562 result = MLX5_MKEY_MASK_KEY |
3563 MLX5_MKEY_MASK_FREE;
3564
3565 return cpu_to_be64(result);
3566 }
3567
3568 static __be64 get_umr_disable_mr_mask(void)
3569 {
3570 u64 result;
3571
3572 result = MLX5_MKEY_MASK_FREE;
3573
3574 return cpu_to_be64(result);
3575 }
3576
3577 static __be64 get_umr_update_translation_mask(void)
3578 {
3579 u64 result;
3580
3581 result = MLX5_MKEY_MASK_LEN |
3582 MLX5_MKEY_MASK_PAGE_SIZE |
3583 MLX5_MKEY_MASK_START_ADDR;
3584
3585 return cpu_to_be64(result);
3586 }
3587
3588 static __be64 get_umr_update_access_mask(int atomic)
3589 {
3590 u64 result;
3591
3592 result = MLX5_MKEY_MASK_LR |
3593 MLX5_MKEY_MASK_LW |
3594 MLX5_MKEY_MASK_RR |
3595 MLX5_MKEY_MASK_RW;
3596
3597 if (atomic)
3598 result |= MLX5_MKEY_MASK_A;
3599
3600 return cpu_to_be64(result);
3601 }
3602
3603 static __be64 get_umr_update_pd_mask(void)
3604 {
3605 u64 result;
3606
3607 result = MLX5_MKEY_MASK_PD;
3608
3609 return cpu_to_be64(result);
3610 }
3611
3612 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3613 struct ib_send_wr *wr, int atomic)
3614 {
3615 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3616
3617 memset(umr, 0, sizeof(*umr));
3618
3619 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3620 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3621 else
3622 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3623
3624 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3625 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3626 u64 offset = get_xlt_octo(umrwr->offset);
3627
3628 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3629 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3630 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3631 }
3632 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3633 umr->mkey_mask |= get_umr_update_translation_mask();
3634 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3635 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3636 umr->mkey_mask |= get_umr_update_pd_mask();
3637 }
3638 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3639 umr->mkey_mask |= get_umr_enable_mr_mask();
3640 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3641 umr->mkey_mask |= get_umr_disable_mr_mask();
3642
3643 if (!wr->num_sge)
3644 umr->flags |= MLX5_UMR_INLINE;
3645 }
3646
3647 static u8 get_umr_flags(int acc)
3648 {
3649 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3650 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3651 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3652 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3653 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3654 }
3655
3656 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3657 struct mlx5_ib_mr *mr,
3658 u32 key, int access)
3659 {
3660 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3661
3662 memset(seg, 0, sizeof(*seg));
3663
3664 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3665 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3666 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3667 /* KLMs take twice the size of MTTs */
3668 ndescs *= 2;
3669
3670 seg->flags = get_umr_flags(access) | mr->access_mode;
3671 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3672 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3673 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3674 seg->len = cpu_to_be64(mr->ibmr.length);
3675 seg->xlt_oct_size = cpu_to_be32(ndescs);
3676 }
3677
3678 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3679 {
3680 memset(seg, 0, sizeof(*seg));
3681 seg->status = MLX5_MKEY_STATUS_FREE;
3682 }
3683
3684 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3685 {
3686 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3687
3688 memset(seg, 0, sizeof(*seg));
3689 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3690 seg->status = MLX5_MKEY_STATUS_FREE;
3691
3692 seg->flags = convert_access(umrwr->access_flags);
3693 if (umrwr->pd)
3694 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3695 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3696 !umrwr->length)
3697 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3698
3699 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3700 seg->len = cpu_to_be64(umrwr->length);
3701 seg->log2_page_size = umrwr->page_shift;
3702 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3703 mlx5_mkey_variant(umrwr->mkey));
3704 }
3705
3706 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3707 struct mlx5_ib_mr *mr,
3708 struct mlx5_ib_pd *pd)
3709 {
3710 int bcount = mr->desc_size * mr->ndescs;
3711
3712 dseg->addr = cpu_to_be64(mr->desc_map);
3713 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3714 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3715 }
3716
3717 static __be32 send_ieth(struct ib_send_wr *wr)
3718 {
3719 switch (wr->opcode) {
3720 case IB_WR_SEND_WITH_IMM:
3721 case IB_WR_RDMA_WRITE_WITH_IMM:
3722 return wr->ex.imm_data;
3723
3724 case IB_WR_SEND_WITH_INV:
3725 return cpu_to_be32(wr->ex.invalidate_rkey);
3726
3727 default:
3728 return 0;
3729 }
3730 }
3731
3732 static u8 calc_sig(void *wqe, int size)
3733 {
3734 u8 *p = wqe;
3735 u8 res = 0;
3736 int i;
3737
3738 for (i = 0; i < size; i++)
3739 res ^= p[i];
3740
3741 return ~res;
3742 }
3743
3744 static u8 wq_sig(void *wqe)
3745 {
3746 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3747 }
3748
3749 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3750 void *wqe, int *sz)
3751 {
3752 struct mlx5_wqe_inline_seg *seg;
3753 void *qend = qp->sq.qend;
3754 void *addr;
3755 int inl = 0;
3756 int copy;
3757 int len;
3758 int i;
3759
3760 seg = wqe;
3761 wqe += sizeof(*seg);
3762 for (i = 0; i < wr->num_sge; i++) {
3763 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3764 len = wr->sg_list[i].length;
3765 inl += len;
3766
3767 if (unlikely(inl > qp->max_inline_data))
3768 return -ENOMEM;
3769
3770 if (unlikely(wqe + len > qend)) {
3771 copy = qend - wqe;
3772 memcpy(wqe, addr, copy);
3773 addr += copy;
3774 len -= copy;
3775 wqe = mlx5_get_send_wqe(qp, 0);
3776 }
3777 memcpy(wqe, addr, len);
3778 wqe += len;
3779 }
3780
3781 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3782
3783 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3784
3785 return 0;
3786 }
3787
3788 static u16 prot_field_size(enum ib_signature_type type)
3789 {
3790 switch (type) {
3791 case IB_SIG_TYPE_T10_DIF:
3792 return MLX5_DIF_SIZE;
3793 default:
3794 return 0;
3795 }
3796 }
3797
3798 static u8 bs_selector(int block_size)
3799 {
3800 switch (block_size) {
3801 case 512: return 0x1;
3802 case 520: return 0x2;
3803 case 4096: return 0x3;
3804 case 4160: return 0x4;
3805 case 1073741824: return 0x5;
3806 default: return 0;
3807 }
3808 }
3809
3810 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3811 struct mlx5_bsf_inl *inl)
3812 {
3813 /* Valid inline section and allow BSF refresh */
3814 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3815 MLX5_BSF_REFRESH_DIF);
3816 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3817 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3818 /* repeating block */
3819 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3820 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3821 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3822
3823 if (domain->sig.dif.ref_remap)
3824 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3825
3826 if (domain->sig.dif.app_escape) {
3827 if (domain->sig.dif.ref_escape)
3828 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3829 else
3830 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3831 }
3832
3833 inl->dif_app_bitmask_check =
3834 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3835 }
3836
3837 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3838 struct ib_sig_attrs *sig_attrs,
3839 struct mlx5_bsf *bsf, u32 data_size)
3840 {
3841 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3842 struct mlx5_bsf_basic *basic = &bsf->basic;
3843 struct ib_sig_domain *mem = &sig_attrs->mem;
3844 struct ib_sig_domain *wire = &sig_attrs->wire;
3845
3846 memset(bsf, 0, sizeof(*bsf));
3847
3848 /* Basic + Extended + Inline */
3849 basic->bsf_size_sbs = 1 << 7;
3850 /* Input domain check byte mask */
3851 basic->check_byte_mask = sig_attrs->check_mask;
3852 basic->raw_data_size = cpu_to_be32(data_size);
3853
3854 /* Memory domain */
3855 switch (sig_attrs->mem.sig_type) {
3856 case IB_SIG_TYPE_NONE:
3857 break;
3858 case IB_SIG_TYPE_T10_DIF:
3859 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3860 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3861 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3862 break;
3863 default:
3864 return -EINVAL;
3865 }
3866
3867 /* Wire domain */
3868 switch (sig_attrs->wire.sig_type) {
3869 case IB_SIG_TYPE_NONE:
3870 break;
3871 case IB_SIG_TYPE_T10_DIF:
3872 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3873 mem->sig_type == wire->sig_type) {
3874 /* Same block structure */
3875 basic->bsf_size_sbs |= 1 << 4;
3876 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3877 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3878 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3879 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3880 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3881 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3882 } else
3883 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3884
3885 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3886 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3887 break;
3888 default:
3889 return -EINVAL;
3890 }
3891
3892 return 0;
3893 }
3894
3895 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3896 struct mlx5_ib_qp *qp, void **seg, int *size)
3897 {
3898 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3899 struct ib_mr *sig_mr = wr->sig_mr;
3900 struct mlx5_bsf *bsf;
3901 u32 data_len = wr->wr.sg_list->length;
3902 u32 data_key = wr->wr.sg_list->lkey;
3903 u64 data_va = wr->wr.sg_list->addr;
3904 int ret;
3905 int wqe_size;
3906
3907 if (!wr->prot ||
3908 (data_key == wr->prot->lkey &&
3909 data_va == wr->prot->addr &&
3910 data_len == wr->prot->length)) {
3911 /**
3912 * Source domain doesn't contain signature information
3913 * or data and protection are interleaved in memory.
3914 * So need construct:
3915 * ------------------
3916 * | data_klm |
3917 * ------------------
3918 * | BSF |
3919 * ------------------
3920 **/
3921 struct mlx5_klm *data_klm = *seg;
3922
3923 data_klm->bcount = cpu_to_be32(data_len);
3924 data_klm->key = cpu_to_be32(data_key);
3925 data_klm->va = cpu_to_be64(data_va);
3926 wqe_size = ALIGN(sizeof(*data_klm), 64);
3927 } else {
3928 /**
3929 * Source domain contains signature information
3930 * So need construct a strided block format:
3931 * ---------------------------
3932 * | stride_block_ctrl |
3933 * ---------------------------
3934 * | data_klm |
3935 * ---------------------------
3936 * | prot_klm |
3937 * ---------------------------
3938 * | BSF |
3939 * ---------------------------
3940 **/
3941 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3942 struct mlx5_stride_block_entry *data_sentry;
3943 struct mlx5_stride_block_entry *prot_sentry;
3944 u32 prot_key = wr->prot->lkey;
3945 u64 prot_va = wr->prot->addr;
3946 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3947 int prot_size;
3948
3949 sblock_ctrl = *seg;
3950 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3951 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3952
3953 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3954 if (!prot_size) {
3955 pr_err("Bad block size given: %u\n", block_size);
3956 return -EINVAL;
3957 }
3958 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3959 prot_size);
3960 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3961 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3962 sblock_ctrl->num_entries = cpu_to_be16(2);
3963
3964 data_sentry->bcount = cpu_to_be16(block_size);
3965 data_sentry->key = cpu_to_be32(data_key);
3966 data_sentry->va = cpu_to_be64(data_va);
3967 data_sentry->stride = cpu_to_be16(block_size);
3968
3969 prot_sentry->bcount = cpu_to_be16(prot_size);
3970 prot_sentry->key = cpu_to_be32(prot_key);
3971 prot_sentry->va = cpu_to_be64(prot_va);
3972 prot_sentry->stride = cpu_to_be16(prot_size);
3973
3974 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3975 sizeof(*prot_sentry), 64);
3976 }
3977
3978 *seg += wqe_size;
3979 *size += wqe_size / 16;
3980 if (unlikely((*seg == qp->sq.qend)))
3981 *seg = mlx5_get_send_wqe(qp, 0);
3982
3983 bsf = *seg;
3984 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3985 if (ret)
3986 return -EINVAL;
3987
3988 *seg += sizeof(*bsf);
3989 *size += sizeof(*bsf) / 16;
3990 if (unlikely((*seg == qp->sq.qend)))
3991 *seg = mlx5_get_send_wqe(qp, 0);
3992
3993 return 0;
3994 }
3995
3996 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3997 struct ib_sig_handover_wr *wr, u32 size,
3998 u32 length, u32 pdn)
3999 {
4000 struct ib_mr *sig_mr = wr->sig_mr;
4001 u32 sig_key = sig_mr->rkey;
4002 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4003
4004 memset(seg, 0, sizeof(*seg));
4005
4006 seg->flags = get_umr_flags(wr->access_flags) |
4007 MLX5_MKC_ACCESS_MODE_KLMS;
4008 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4009 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4010 MLX5_MKEY_BSF_EN | pdn);
4011 seg->len = cpu_to_be64(length);
4012 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4013 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4014 }
4015
4016 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4017 u32 size)
4018 {
4019 memset(umr, 0, sizeof(*umr));
4020
4021 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4022 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4023 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4024 umr->mkey_mask = sig_mkey_mask();
4025 }
4026
4027
4028 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
4029 void **seg, int *size)
4030 {
4031 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4032 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4033 u32 pdn = get_pd(qp)->pdn;
4034 u32 xlt_size;
4035 int region_len, ret;
4036
4037 if (unlikely(wr->wr.num_sge != 1) ||
4038 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4039 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4040 unlikely(!sig_mr->sig->sig_status_checked))
4041 return -EINVAL;
4042
4043 /* length of the protected region, data + protection */
4044 region_len = wr->wr.sg_list->length;
4045 if (wr->prot &&
4046 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4047 wr->prot->addr != wr->wr.sg_list->addr ||
4048 wr->prot->length != wr->wr.sg_list->length))
4049 region_len += wr->prot->length;
4050
4051 /**
4052 * KLM octoword size - if protection was provided
4053 * then we use strided block format (3 octowords),
4054 * else we use single KLM (1 octoword)
4055 **/
4056 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4057
4058 set_sig_umr_segment(*seg, xlt_size);
4059 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4060 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4061 if (unlikely((*seg == qp->sq.qend)))
4062 *seg = mlx5_get_send_wqe(qp, 0);
4063
4064 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4065 *seg += sizeof(struct mlx5_mkey_seg);
4066 *size += sizeof(struct mlx5_mkey_seg) / 16;
4067 if (unlikely((*seg == qp->sq.qend)))
4068 *seg = mlx5_get_send_wqe(qp, 0);
4069
4070 ret = set_sig_data_segment(wr, qp, seg, size);
4071 if (ret)
4072 return ret;
4073
4074 sig_mr->sig->sig_status_checked = false;
4075 return 0;
4076 }
4077
4078 static int set_psv_wr(struct ib_sig_domain *domain,
4079 u32 psv_idx, void **seg, int *size)
4080 {
4081 struct mlx5_seg_set_psv *psv_seg = *seg;
4082
4083 memset(psv_seg, 0, sizeof(*psv_seg));
4084 psv_seg->psv_num = cpu_to_be32(psv_idx);
4085 switch (domain->sig_type) {
4086 case IB_SIG_TYPE_NONE:
4087 break;
4088 case IB_SIG_TYPE_T10_DIF:
4089 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4090 domain->sig.dif.app_tag);
4091 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4092 break;
4093 default:
4094 pr_err("Bad signature type (%d) is given.\n",
4095 domain->sig_type);
4096 return -EINVAL;
4097 }
4098
4099 *seg += sizeof(*psv_seg);
4100 *size += sizeof(*psv_seg) / 16;
4101
4102 return 0;
4103 }
4104
4105 static int set_reg_wr(struct mlx5_ib_qp *qp,
4106 struct ib_reg_wr *wr,
4107 void **seg, int *size)
4108 {
4109 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4110 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4111
4112 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4113 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4114 "Invalid IB_SEND_INLINE send flag\n");
4115 return -EINVAL;
4116 }
4117
4118 set_reg_umr_seg(*seg, mr);
4119 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4120 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4121 if (unlikely((*seg == qp->sq.qend)))
4122 *seg = mlx5_get_send_wqe(qp, 0);
4123
4124 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4125 *seg += sizeof(struct mlx5_mkey_seg);
4126 *size += sizeof(struct mlx5_mkey_seg) / 16;
4127 if (unlikely((*seg == qp->sq.qend)))
4128 *seg = mlx5_get_send_wqe(qp, 0);
4129
4130 set_reg_data_seg(*seg, mr, pd);
4131 *seg += sizeof(struct mlx5_wqe_data_seg);
4132 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4133
4134 return 0;
4135 }
4136
4137 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4138 {
4139 set_linv_umr_seg(*seg);
4140 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4141 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4142 if (unlikely((*seg == qp->sq.qend)))
4143 *seg = mlx5_get_send_wqe(qp, 0);
4144 set_linv_mkey_seg(*seg);
4145 *seg += sizeof(struct mlx5_mkey_seg);
4146 *size += sizeof(struct mlx5_mkey_seg) / 16;
4147 if (unlikely((*seg == qp->sq.qend)))
4148 *seg = mlx5_get_send_wqe(qp, 0);
4149 }
4150
4151 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4152 {
4153 __be32 *p = NULL;
4154 int tidx = idx;
4155 int i, j;
4156
4157 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4158 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4159 if ((i & 0xf) == 0) {
4160 void *buf = mlx5_get_send_wqe(qp, tidx);
4161 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4162 p = buf;
4163 j = 0;
4164 }
4165 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4166 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4167 be32_to_cpu(p[j + 3]));
4168 }
4169 }
4170
4171 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4172 struct mlx5_wqe_ctrl_seg **ctrl,
4173 struct ib_send_wr *wr, unsigned *idx,
4174 int *size, int nreq)
4175 {
4176 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4177 return -ENOMEM;
4178
4179 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4180 *seg = mlx5_get_send_wqe(qp, *idx);
4181 *ctrl = *seg;
4182 *(uint32_t *)(*seg + 8) = 0;
4183 (*ctrl)->imm = send_ieth(wr);
4184 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4185 (wr->send_flags & IB_SEND_SIGNALED ?
4186 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4187 (wr->send_flags & IB_SEND_SOLICITED ?
4188 MLX5_WQE_CTRL_SOLICITED : 0);
4189
4190 *seg += sizeof(**ctrl);
4191 *size = sizeof(**ctrl) / 16;
4192
4193 return 0;
4194 }
4195
4196 static void finish_wqe(struct mlx5_ib_qp *qp,
4197 struct mlx5_wqe_ctrl_seg *ctrl,
4198 u8 size, unsigned idx, u64 wr_id,
4199 int nreq, u8 fence, u32 mlx5_opcode)
4200 {
4201 u8 opmod = 0;
4202
4203 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4204 mlx5_opcode | ((u32)opmod << 24));
4205 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4206 ctrl->fm_ce_se |= fence;
4207 if (unlikely(qp->wq_sig))
4208 ctrl->signature = wq_sig(ctrl);
4209
4210 qp->sq.wrid[idx] = wr_id;
4211 qp->sq.w_list[idx].opcode = mlx5_opcode;
4212 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4213 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4214 qp->sq.w_list[idx].next = qp->sq.cur_post;
4215 }
4216
4217
4218 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4219 struct ib_send_wr **bad_wr)
4220 {
4221 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4222 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4223 struct mlx5_core_dev *mdev = dev->mdev;
4224 struct mlx5_ib_qp *qp;
4225 struct mlx5_ib_mr *mr;
4226 struct mlx5_wqe_data_seg *dpseg;
4227 struct mlx5_wqe_xrc_seg *xrc;
4228 struct mlx5_bf *bf;
4229 int uninitialized_var(size);
4230 void *qend;
4231 unsigned long flags;
4232 unsigned idx;
4233 int err = 0;
4234 int num_sge;
4235 void *seg;
4236 int nreq;
4237 int i;
4238 u8 next_fence = 0;
4239 u8 fence;
4240
4241 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4242 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4243
4244 qp = to_mqp(ibqp);
4245 bf = &qp->bf;
4246 qend = qp->sq.qend;
4247
4248 spin_lock_irqsave(&qp->sq.lock, flags);
4249
4250 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4251 err = -EIO;
4252 *bad_wr = wr;
4253 nreq = 0;
4254 goto out;
4255 }
4256
4257 for (nreq = 0; wr; nreq++, wr = wr->next) {
4258 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4259 mlx5_ib_warn(dev, "\n");
4260 err = -EINVAL;
4261 *bad_wr = wr;
4262 goto out;
4263 }
4264
4265 num_sge = wr->num_sge;
4266 if (unlikely(num_sge > qp->sq.max_gs)) {
4267 mlx5_ib_warn(dev, "\n");
4268 err = -EINVAL;
4269 *bad_wr = wr;
4270 goto out;
4271 }
4272
4273 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4274 if (err) {
4275 mlx5_ib_warn(dev, "\n");
4276 err = -ENOMEM;
4277 *bad_wr = wr;
4278 goto out;
4279 }
4280
4281 if (wr->opcode == IB_WR_LOCAL_INV ||
4282 wr->opcode == IB_WR_REG_MR) {
4283 fence = dev->umr_fence;
4284 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4285 } else if (wr->send_flags & IB_SEND_FENCE) {
4286 if (qp->next_fence)
4287 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4288 else
4289 fence = MLX5_FENCE_MODE_FENCE;
4290 } else {
4291 fence = qp->next_fence;
4292 }
4293
4294 switch (ibqp->qp_type) {
4295 case IB_QPT_XRC_INI:
4296 xrc = seg;
4297 seg += sizeof(*xrc);
4298 size += sizeof(*xrc) / 16;
4299 /* fall through */
4300 case IB_QPT_RC:
4301 switch (wr->opcode) {
4302 case IB_WR_RDMA_READ:
4303 case IB_WR_RDMA_WRITE:
4304 case IB_WR_RDMA_WRITE_WITH_IMM:
4305 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4306 rdma_wr(wr)->rkey);
4307 seg += sizeof(struct mlx5_wqe_raddr_seg);
4308 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4309 break;
4310
4311 case IB_WR_ATOMIC_CMP_AND_SWP:
4312 case IB_WR_ATOMIC_FETCH_AND_ADD:
4313 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4314 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4315 err = -ENOSYS;
4316 *bad_wr = wr;
4317 goto out;
4318
4319 case IB_WR_LOCAL_INV:
4320 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4321 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4322 set_linv_wr(qp, &seg, &size);
4323 num_sge = 0;
4324 break;
4325
4326 case IB_WR_REG_MR:
4327 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4328 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4329 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4330 if (err) {
4331 *bad_wr = wr;
4332 goto out;
4333 }
4334 num_sge = 0;
4335 break;
4336
4337 case IB_WR_REG_SIG_MR:
4338 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4339 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4340
4341 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4342 err = set_sig_umr_wr(wr, qp, &seg, &size);
4343 if (err) {
4344 mlx5_ib_warn(dev, "\n");
4345 *bad_wr = wr;
4346 goto out;
4347 }
4348
4349 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4350 fence, MLX5_OPCODE_UMR);
4351 /*
4352 * SET_PSV WQEs are not signaled and solicited
4353 * on error
4354 */
4355 wr->send_flags &= ~IB_SEND_SIGNALED;
4356 wr->send_flags |= IB_SEND_SOLICITED;
4357 err = begin_wqe(qp, &seg, &ctrl, wr,
4358 &idx, &size, nreq);
4359 if (err) {
4360 mlx5_ib_warn(dev, "\n");
4361 err = -ENOMEM;
4362 *bad_wr = wr;
4363 goto out;
4364 }
4365
4366 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4367 mr->sig->psv_memory.psv_idx, &seg,
4368 &size);
4369 if (err) {
4370 mlx5_ib_warn(dev, "\n");
4371 *bad_wr = wr;
4372 goto out;
4373 }
4374
4375 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4376 fence, MLX5_OPCODE_SET_PSV);
4377 err = begin_wqe(qp, &seg, &ctrl, wr,
4378 &idx, &size, nreq);
4379 if (err) {
4380 mlx5_ib_warn(dev, "\n");
4381 err = -ENOMEM;
4382 *bad_wr = wr;
4383 goto out;
4384 }
4385
4386 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4387 mr->sig->psv_wire.psv_idx, &seg,
4388 &size);
4389 if (err) {
4390 mlx5_ib_warn(dev, "\n");
4391 *bad_wr = wr;
4392 goto out;
4393 }
4394
4395 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4396 fence, MLX5_OPCODE_SET_PSV);
4397 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4398 num_sge = 0;
4399 goto skip_psv;
4400
4401 default:
4402 break;
4403 }
4404 break;
4405
4406 case IB_QPT_UC:
4407 switch (wr->opcode) {
4408 case IB_WR_RDMA_WRITE:
4409 case IB_WR_RDMA_WRITE_WITH_IMM:
4410 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4411 rdma_wr(wr)->rkey);
4412 seg += sizeof(struct mlx5_wqe_raddr_seg);
4413 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4414 break;
4415
4416 default:
4417 break;
4418 }
4419 break;
4420
4421 case IB_QPT_SMI:
4422 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4423 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4424 err = -EPERM;
4425 *bad_wr = wr;
4426 goto out;
4427 }
4428 /* fall through */
4429 case MLX5_IB_QPT_HW_GSI:
4430 set_datagram_seg(seg, wr);
4431 seg += sizeof(struct mlx5_wqe_datagram_seg);
4432 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4433 if (unlikely((seg == qend)))
4434 seg = mlx5_get_send_wqe(qp, 0);
4435 break;
4436 case IB_QPT_UD:
4437 set_datagram_seg(seg, wr);
4438 seg += sizeof(struct mlx5_wqe_datagram_seg);
4439 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4440
4441 if (unlikely((seg == qend)))
4442 seg = mlx5_get_send_wqe(qp, 0);
4443
4444 /* handle qp that supports ud offload */
4445 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4446 struct mlx5_wqe_eth_pad *pad;
4447
4448 pad = seg;
4449 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4450 seg += sizeof(struct mlx5_wqe_eth_pad);
4451 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4452
4453 seg = set_eth_seg(seg, wr, qend, qp, &size);
4454
4455 if (unlikely((seg == qend)))
4456 seg = mlx5_get_send_wqe(qp, 0);
4457 }
4458 break;
4459 case MLX5_IB_QPT_REG_UMR:
4460 if (wr->opcode != MLX5_IB_WR_UMR) {
4461 err = -EINVAL;
4462 mlx5_ib_warn(dev, "bad opcode\n");
4463 goto out;
4464 }
4465 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4466 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4467 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4468 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4469 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4470 if (unlikely((seg == qend)))
4471 seg = mlx5_get_send_wqe(qp, 0);
4472 set_reg_mkey_segment(seg, wr);
4473 seg += sizeof(struct mlx5_mkey_seg);
4474 size += sizeof(struct mlx5_mkey_seg) / 16;
4475 if (unlikely((seg == qend)))
4476 seg = mlx5_get_send_wqe(qp, 0);
4477 break;
4478
4479 default:
4480 break;
4481 }
4482
4483 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4484 int uninitialized_var(sz);
4485
4486 err = set_data_inl_seg(qp, wr, seg, &sz);
4487 if (unlikely(err)) {
4488 mlx5_ib_warn(dev, "\n");
4489 *bad_wr = wr;
4490 goto out;
4491 }
4492 size += sz;
4493 } else {
4494 dpseg = seg;
4495 for (i = 0; i < num_sge; i++) {
4496 if (unlikely(dpseg == qend)) {
4497 seg = mlx5_get_send_wqe(qp, 0);
4498 dpseg = seg;
4499 }
4500 if (likely(wr->sg_list[i].length)) {
4501 set_data_ptr_seg(dpseg, wr->sg_list + i);
4502 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4503 dpseg++;
4504 }
4505 }
4506 }
4507
4508 qp->next_fence = next_fence;
4509 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4510 mlx5_ib_opcode[wr->opcode]);
4511 skip_psv:
4512 if (0)
4513 dump_wqe(qp, idx, size);
4514 }
4515
4516 out:
4517 if (likely(nreq)) {
4518 qp->sq.head += nreq;
4519
4520 /* Make sure that descriptors are written before
4521 * updating doorbell record and ringing the doorbell
4522 */
4523 wmb();
4524
4525 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4526
4527 /* Make sure doorbell record is visible to the HCA before
4528 * we hit doorbell */
4529 wmb();
4530
4531 /* currently we support only regular doorbells */
4532 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4533 /* Make sure doorbells don't leak out of SQ spinlock
4534 * and reach the HCA out of order.
4535 */
4536 mmiowb();
4537 bf->offset ^= bf->buf_size;
4538 }
4539
4540 spin_unlock_irqrestore(&qp->sq.lock, flags);
4541
4542 return err;
4543 }
4544
4545 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4546 {
4547 sig->signature = calc_sig(sig, size);
4548 }
4549
4550 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4551 struct ib_recv_wr **bad_wr)
4552 {
4553 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4554 struct mlx5_wqe_data_seg *scat;
4555 struct mlx5_rwqe_sig *sig;
4556 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4557 struct mlx5_core_dev *mdev = dev->mdev;
4558 unsigned long flags;
4559 int err = 0;
4560 int nreq;
4561 int ind;
4562 int i;
4563
4564 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4565 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4566
4567 spin_lock_irqsave(&qp->rq.lock, flags);
4568
4569 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4570 err = -EIO;
4571 *bad_wr = wr;
4572 nreq = 0;
4573 goto out;
4574 }
4575
4576 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4577
4578 for (nreq = 0; wr; nreq++, wr = wr->next) {
4579 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4580 err = -ENOMEM;
4581 *bad_wr = wr;
4582 goto out;
4583 }
4584
4585 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4586 err = -EINVAL;
4587 *bad_wr = wr;
4588 goto out;
4589 }
4590
4591 scat = get_recv_wqe(qp, ind);
4592 if (qp->wq_sig)
4593 scat++;
4594
4595 for (i = 0; i < wr->num_sge; i++)
4596 set_data_ptr_seg(scat + i, wr->sg_list + i);
4597
4598 if (i < qp->rq.max_gs) {
4599 scat[i].byte_count = 0;
4600 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4601 scat[i].addr = 0;
4602 }
4603
4604 if (qp->wq_sig) {
4605 sig = (struct mlx5_rwqe_sig *)scat;
4606 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4607 }
4608
4609 qp->rq.wrid[ind] = wr->wr_id;
4610
4611 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4612 }
4613
4614 out:
4615 if (likely(nreq)) {
4616 qp->rq.head += nreq;
4617
4618 /* Make sure that descriptors are written before
4619 * doorbell record.
4620 */
4621 wmb();
4622
4623 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4624 }
4625
4626 spin_unlock_irqrestore(&qp->rq.lock, flags);
4627
4628 return err;
4629 }
4630
4631 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4632 {
4633 switch (mlx5_state) {
4634 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4635 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4636 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4637 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4638 case MLX5_QP_STATE_SQ_DRAINING:
4639 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4640 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4641 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4642 default: return -1;
4643 }
4644 }
4645
4646 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4647 {
4648 switch (mlx5_mig_state) {
4649 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4650 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4651 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4652 default: return -1;
4653 }
4654 }
4655
4656 static int to_ib_qp_access_flags(int mlx5_flags)
4657 {
4658 int ib_flags = 0;
4659
4660 if (mlx5_flags & MLX5_QP_BIT_RRE)
4661 ib_flags |= IB_ACCESS_REMOTE_READ;
4662 if (mlx5_flags & MLX5_QP_BIT_RWE)
4663 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4664 if (mlx5_flags & MLX5_QP_BIT_RAE)
4665 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4666
4667 return ib_flags;
4668 }
4669
4670 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4671 struct rdma_ah_attr *ah_attr,
4672 struct mlx5_qp_path *path)
4673 {
4674
4675 memset(ah_attr, 0, sizeof(*ah_attr));
4676
4677 if (!path->port || path->port > ibdev->num_ports)
4678 return;
4679
4680 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4681
4682 rdma_ah_set_port_num(ah_attr, path->port);
4683 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4684
4685 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4686 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4687 rdma_ah_set_static_rate(ah_attr,
4688 path->static_rate ? path->static_rate - 5 : 0);
4689 if (path->grh_mlid & (1 << 7)) {
4690 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4691
4692 rdma_ah_set_grh(ah_attr, NULL,
4693 tc_fl & 0xfffff,
4694 path->mgid_index,
4695 path->hop_limit,
4696 (tc_fl >> 20) & 0xff);
4697 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4698 }
4699 }
4700
4701 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4702 struct mlx5_ib_sq *sq,
4703 u8 *sq_state)
4704 {
4705 void *out;
4706 void *sqc;
4707 int inlen;
4708 int err;
4709
4710 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4711 out = kvzalloc(inlen, GFP_KERNEL);
4712 if (!out)
4713 return -ENOMEM;
4714
4715 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4716 if (err)
4717 goto out;
4718
4719 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4720 *sq_state = MLX5_GET(sqc, sqc, state);
4721 sq->state = *sq_state;
4722
4723 out:
4724 kvfree(out);
4725 return err;
4726 }
4727
4728 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4729 struct mlx5_ib_rq *rq,
4730 u8 *rq_state)
4731 {
4732 void *out;
4733 void *rqc;
4734 int inlen;
4735 int err;
4736
4737 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4738 out = kvzalloc(inlen, GFP_KERNEL);
4739 if (!out)
4740 return -ENOMEM;
4741
4742 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4743 if (err)
4744 goto out;
4745
4746 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4747 *rq_state = MLX5_GET(rqc, rqc, state);
4748 rq->state = *rq_state;
4749
4750 out:
4751 kvfree(out);
4752 return err;
4753 }
4754
4755 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4756 struct mlx5_ib_qp *qp, u8 *qp_state)
4757 {
4758 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4759 [MLX5_RQC_STATE_RST] = {
4760 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4761 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4762 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4763 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4764 },
4765 [MLX5_RQC_STATE_RDY] = {
4766 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4767 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4768 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4769 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4770 },
4771 [MLX5_RQC_STATE_ERR] = {
4772 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4773 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4774 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4775 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4776 },
4777 [MLX5_RQ_STATE_NA] = {
4778 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4779 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4780 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4781 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4782 },
4783 };
4784
4785 *qp_state = sqrq_trans[rq_state][sq_state];
4786
4787 if (*qp_state == MLX5_QP_STATE_BAD) {
4788 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4789 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4790 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4791 return -EINVAL;
4792 }
4793
4794 if (*qp_state == MLX5_QP_STATE)
4795 *qp_state = qp->state;
4796
4797 return 0;
4798 }
4799
4800 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4801 struct mlx5_ib_qp *qp,
4802 u8 *raw_packet_qp_state)
4803 {
4804 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4805 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4806 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4807 int err;
4808 u8 sq_state = MLX5_SQ_STATE_NA;
4809 u8 rq_state = MLX5_RQ_STATE_NA;
4810
4811 if (qp->sq.wqe_cnt) {
4812 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4813 if (err)
4814 return err;
4815 }
4816
4817 if (qp->rq.wqe_cnt) {
4818 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4819 if (err)
4820 return err;
4821 }
4822
4823 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4824 raw_packet_qp_state);
4825 }
4826
4827 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4828 struct ib_qp_attr *qp_attr)
4829 {
4830 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4831 struct mlx5_qp_context *context;
4832 int mlx5_state;
4833 u32 *outb;
4834 int err = 0;
4835
4836 outb = kzalloc(outlen, GFP_KERNEL);
4837 if (!outb)
4838 return -ENOMEM;
4839
4840 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4841 outlen);
4842 if (err)
4843 goto out;
4844
4845 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4846 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4847
4848 mlx5_state = be32_to_cpu(context->flags) >> 28;
4849
4850 qp->state = to_ib_qp_state(mlx5_state);
4851 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4852 qp_attr->path_mig_state =
4853 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4854 qp_attr->qkey = be32_to_cpu(context->qkey);
4855 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4856 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4857 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4858 qp_attr->qp_access_flags =
4859 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4860
4861 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4862 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4863 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4864 qp_attr->alt_pkey_index =
4865 be16_to_cpu(context->alt_path.pkey_index);
4866 qp_attr->alt_port_num =
4867 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4868 }
4869
4870 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4871 qp_attr->port_num = context->pri_path.port;
4872
4873 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4874 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4875
4876 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4877
4878 qp_attr->max_dest_rd_atomic =
4879 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4880 qp_attr->min_rnr_timer =
4881 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4882 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4883 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4884 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4885 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
4886
4887 out:
4888 kfree(outb);
4889 return err;
4890 }
4891
4892 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4893 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4894 struct ib_qp_init_attr *qp_init_attr)
4895 {
4896 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4897 u32 *out;
4898 u32 access_flags = 0;
4899 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4900 void *dctc;
4901 int err;
4902 int supported_mask = IB_QP_STATE |
4903 IB_QP_ACCESS_FLAGS |
4904 IB_QP_PORT |
4905 IB_QP_MIN_RNR_TIMER |
4906 IB_QP_AV |
4907 IB_QP_PATH_MTU |
4908 IB_QP_PKEY_INDEX;
4909
4910 if (qp_attr_mask & ~supported_mask)
4911 return -EINVAL;
4912 if (mqp->state != IB_QPS_RTR)
4913 return -EINVAL;
4914
4915 out = kzalloc(outlen, GFP_KERNEL);
4916 if (!out)
4917 return -ENOMEM;
4918
4919 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
4920 if (err)
4921 goto out;
4922
4923 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4924
4925 if (qp_attr_mask & IB_QP_STATE)
4926 qp_attr->qp_state = IB_QPS_RTR;
4927
4928 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4929 if (MLX5_GET(dctc, dctc, rre))
4930 access_flags |= IB_ACCESS_REMOTE_READ;
4931 if (MLX5_GET(dctc, dctc, rwe))
4932 access_flags |= IB_ACCESS_REMOTE_WRITE;
4933 if (MLX5_GET(dctc, dctc, rae))
4934 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4935 qp_attr->qp_access_flags = access_flags;
4936 }
4937
4938 if (qp_attr_mask & IB_QP_PORT)
4939 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4940 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4941 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4942 if (qp_attr_mask & IB_QP_AV) {
4943 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4944 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4945 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4946 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4947 }
4948 if (qp_attr_mask & IB_QP_PATH_MTU)
4949 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4950 if (qp_attr_mask & IB_QP_PKEY_INDEX)
4951 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4952 out:
4953 kfree(out);
4954 return err;
4955 }
4956
4957 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4958 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4959 {
4960 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4961 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4962 int err = 0;
4963 u8 raw_packet_qp_state;
4964
4965 if (ibqp->rwq_ind_tbl)
4966 return -ENOSYS;
4967
4968 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4969 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4970 qp_init_attr);
4971
4972 /* Not all of output fields are applicable, make sure to zero them */
4973 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4974 memset(qp_attr, 0, sizeof(*qp_attr));
4975
4976 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
4977 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4978 qp_attr_mask, qp_init_attr);
4979
4980 mutex_lock(&qp->mutex);
4981
4982 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4983 qp->flags & MLX5_IB_QP_UNDERLAY) {
4984 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4985 if (err)
4986 goto out;
4987 qp->state = raw_packet_qp_state;
4988 qp_attr->port_num = 1;
4989 } else {
4990 err = query_qp_attr(dev, qp, qp_attr);
4991 if (err)
4992 goto out;
4993 }
4994
4995 qp_attr->qp_state = qp->state;
4996 qp_attr->cur_qp_state = qp_attr->qp_state;
4997 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4998 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4999
5000 if (!ibqp->uobject) {
5001 qp_attr->cap.max_send_wr = qp->sq.max_post;
5002 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5003 qp_init_attr->qp_context = ibqp->qp_context;
5004 } else {
5005 qp_attr->cap.max_send_wr = 0;
5006 qp_attr->cap.max_send_sge = 0;
5007 }
5008
5009 qp_init_attr->qp_type = ibqp->qp_type;
5010 qp_init_attr->recv_cq = ibqp->recv_cq;
5011 qp_init_attr->send_cq = ibqp->send_cq;
5012 qp_init_attr->srq = ibqp->srq;
5013 qp_attr->cap.max_inline_data = qp->max_inline_data;
5014
5015 qp_init_attr->cap = qp_attr->cap;
5016
5017 qp_init_attr->create_flags = 0;
5018 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5019 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5020
5021 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5022 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5023 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5024 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5025 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5026 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5027 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5028 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5029
5030 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5031 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5032
5033 out:
5034 mutex_unlock(&qp->mutex);
5035 return err;
5036 }
5037
5038 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5039 struct ib_ucontext *context,
5040 struct ib_udata *udata)
5041 {
5042 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5043 struct mlx5_ib_xrcd *xrcd;
5044 int err;
5045
5046 if (!MLX5_CAP_GEN(dev->mdev, xrc))
5047 return ERR_PTR(-ENOSYS);
5048
5049 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5050 if (!xrcd)
5051 return ERR_PTR(-ENOMEM);
5052
5053 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
5054 if (err) {
5055 kfree(xrcd);
5056 return ERR_PTR(-ENOMEM);
5057 }
5058
5059 return &xrcd->ibxrcd;
5060 }
5061
5062 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5063 {
5064 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5065 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5066 int err;
5067
5068 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
5069 if (err)
5070 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5071
5072 kfree(xrcd);
5073 return 0;
5074 }
5075
5076 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5077 {
5078 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5079 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5080 struct ib_event event;
5081
5082 if (rwq->ibwq.event_handler) {
5083 event.device = rwq->ibwq.device;
5084 event.element.wq = &rwq->ibwq;
5085 switch (type) {
5086 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5087 event.event = IB_EVENT_WQ_FATAL;
5088 break;
5089 default:
5090 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5091 return;
5092 }
5093
5094 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5095 }
5096 }
5097
5098 static int set_delay_drop(struct mlx5_ib_dev *dev)
5099 {
5100 int err = 0;
5101
5102 mutex_lock(&dev->delay_drop.lock);
5103 if (dev->delay_drop.activate)
5104 goto out;
5105
5106 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5107 if (err)
5108 goto out;
5109
5110 dev->delay_drop.activate = true;
5111 out:
5112 mutex_unlock(&dev->delay_drop.lock);
5113
5114 if (!err)
5115 atomic_inc(&dev->delay_drop.rqs_cnt);
5116 return err;
5117 }
5118
5119 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5120 struct ib_wq_init_attr *init_attr)
5121 {
5122 struct mlx5_ib_dev *dev;
5123 int has_net_offloads;
5124 __be64 *rq_pas0;
5125 void *in;
5126 void *rqc;
5127 void *wq;
5128 int inlen;
5129 int err;
5130
5131 dev = to_mdev(pd->device);
5132
5133 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5134 in = kvzalloc(inlen, GFP_KERNEL);
5135 if (!in)
5136 return -ENOMEM;
5137
5138 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5139 MLX5_SET(rqc, rqc, mem_rq_type,
5140 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5141 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5142 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5143 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5144 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5145 wq = MLX5_ADDR_OF(rqc, rqc, wq);
5146 MLX5_SET(wq, wq, wq_type,
5147 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5148 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5149 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5150 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5151 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5152 err = -EOPNOTSUPP;
5153 goto out;
5154 } else {
5155 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5156 }
5157 }
5158 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5159 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5160 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5161 MLX5_SET(wq, wq, log_wqe_stride_size,
5162 rwq->single_stride_log_num_of_bytes -
5163 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5164 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5165 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5166 }
5167 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5168 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5169 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5170 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5171 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5172 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5173 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5174 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5175 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5176 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5177 err = -EOPNOTSUPP;
5178 goto out;
5179 }
5180 } else {
5181 MLX5_SET(rqc, rqc, vsd, 1);
5182 }
5183 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5184 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5185 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5186 err = -EOPNOTSUPP;
5187 goto out;
5188 }
5189 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5190 }
5191 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5192 if (!(dev->ib_dev.attrs.raw_packet_caps &
5193 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5194 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5195 err = -EOPNOTSUPP;
5196 goto out;
5197 }
5198 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5199 }
5200 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5201 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5202 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5203 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5204 err = set_delay_drop(dev);
5205 if (err) {
5206 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5207 err);
5208 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5209 } else {
5210 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5211 }
5212 }
5213 out:
5214 kvfree(in);
5215 return err;
5216 }
5217
5218 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5219 struct ib_wq_init_attr *wq_init_attr,
5220 struct mlx5_ib_create_wq *ucmd,
5221 struct mlx5_ib_rwq *rwq)
5222 {
5223 /* Sanity check RQ size before proceeding */
5224 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5225 return -EINVAL;
5226
5227 if (!ucmd->rq_wqe_count)
5228 return -EINVAL;
5229
5230 rwq->wqe_count = ucmd->rq_wqe_count;
5231 rwq->wqe_shift = ucmd->rq_wqe_shift;
5232 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5233 rwq->log_rq_stride = rwq->wqe_shift;
5234 rwq->log_rq_size = ilog2(rwq->wqe_count);
5235 return 0;
5236 }
5237
5238 static int prepare_user_rq(struct ib_pd *pd,
5239 struct ib_wq_init_attr *init_attr,
5240 struct ib_udata *udata,
5241 struct mlx5_ib_rwq *rwq)
5242 {
5243 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5244 struct mlx5_ib_create_wq ucmd = {};
5245 int err;
5246 size_t required_cmd_sz;
5247
5248 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5249 + sizeof(ucmd.single_stride_log_num_of_bytes);
5250 if (udata->inlen < required_cmd_sz) {
5251 mlx5_ib_dbg(dev, "invalid inlen\n");
5252 return -EINVAL;
5253 }
5254
5255 if (udata->inlen > sizeof(ucmd) &&
5256 !ib_is_udata_cleared(udata, sizeof(ucmd),
5257 udata->inlen - sizeof(ucmd))) {
5258 mlx5_ib_dbg(dev, "inlen is not supported\n");
5259 return -EOPNOTSUPP;
5260 }
5261
5262 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5263 mlx5_ib_dbg(dev, "copy failed\n");
5264 return -EFAULT;
5265 }
5266
5267 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5268 mlx5_ib_dbg(dev, "invalid comp mask\n");
5269 return -EOPNOTSUPP;
5270 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5271 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5272 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5273 return -EOPNOTSUPP;
5274 }
5275 if ((ucmd.single_stride_log_num_of_bytes <
5276 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5277 (ucmd.single_stride_log_num_of_bytes >
5278 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5279 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5280 ucmd.single_stride_log_num_of_bytes,
5281 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5282 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5283 return -EINVAL;
5284 }
5285 if ((ucmd.single_wqe_log_num_of_strides >
5286 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5287 (ucmd.single_wqe_log_num_of_strides <
5288 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5289 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5290 ucmd.single_wqe_log_num_of_strides,
5291 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5292 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5293 return -EINVAL;
5294 }
5295 rwq->single_stride_log_num_of_bytes =
5296 ucmd.single_stride_log_num_of_bytes;
5297 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5298 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5299 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5300 }
5301
5302 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5303 if (err) {
5304 mlx5_ib_dbg(dev, "err %d\n", err);
5305 return err;
5306 }
5307
5308 err = create_user_rq(dev, pd, rwq, &ucmd);
5309 if (err) {
5310 mlx5_ib_dbg(dev, "err %d\n", err);
5311 if (err)
5312 return err;
5313 }
5314
5315 rwq->user_index = ucmd.user_index;
5316 return 0;
5317 }
5318
5319 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5320 struct ib_wq_init_attr *init_attr,
5321 struct ib_udata *udata)
5322 {
5323 struct mlx5_ib_dev *dev;
5324 struct mlx5_ib_rwq *rwq;
5325 struct mlx5_ib_create_wq_resp resp = {};
5326 size_t min_resp_len;
5327 int err;
5328
5329 if (!udata)
5330 return ERR_PTR(-ENOSYS);
5331
5332 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5333 if (udata->outlen && udata->outlen < min_resp_len)
5334 return ERR_PTR(-EINVAL);
5335
5336 dev = to_mdev(pd->device);
5337 switch (init_attr->wq_type) {
5338 case IB_WQT_RQ:
5339 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5340 if (!rwq)
5341 return ERR_PTR(-ENOMEM);
5342 err = prepare_user_rq(pd, init_attr, udata, rwq);
5343 if (err)
5344 goto err;
5345 err = create_rq(rwq, pd, init_attr);
5346 if (err)
5347 goto err_user_rq;
5348 break;
5349 default:
5350 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5351 init_attr->wq_type);
5352 return ERR_PTR(-EINVAL);
5353 }
5354
5355 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5356 rwq->ibwq.state = IB_WQS_RESET;
5357 if (udata->outlen) {
5358 resp.response_length = offsetof(typeof(resp), response_length) +
5359 sizeof(resp.response_length);
5360 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5361 if (err)
5362 goto err_copy;
5363 }
5364
5365 rwq->core_qp.event = mlx5_ib_wq_event;
5366 rwq->ibwq.event_handler = init_attr->event_handler;
5367 return &rwq->ibwq;
5368
5369 err_copy:
5370 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5371 err_user_rq:
5372 destroy_user_rq(dev, pd, rwq);
5373 err:
5374 kfree(rwq);
5375 return ERR_PTR(err);
5376 }
5377
5378 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5379 {
5380 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5381 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5382
5383 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5384 destroy_user_rq(dev, wq->pd, rwq);
5385 kfree(rwq);
5386
5387 return 0;
5388 }
5389
5390 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5391 struct ib_rwq_ind_table_init_attr *init_attr,
5392 struct ib_udata *udata)
5393 {
5394 struct mlx5_ib_dev *dev = to_mdev(device);
5395 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5396 int sz = 1 << init_attr->log_ind_tbl_size;
5397 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5398 size_t min_resp_len;
5399 int inlen;
5400 int err;
5401 int i;
5402 u32 *in;
5403 void *rqtc;
5404
5405 if (udata->inlen > 0 &&
5406 !ib_is_udata_cleared(udata, 0,
5407 udata->inlen))
5408 return ERR_PTR(-EOPNOTSUPP);
5409
5410 if (init_attr->log_ind_tbl_size >
5411 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5412 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5413 init_attr->log_ind_tbl_size,
5414 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5415 return ERR_PTR(-EINVAL);
5416 }
5417
5418 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5419 if (udata->outlen && udata->outlen < min_resp_len)
5420 return ERR_PTR(-EINVAL);
5421
5422 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5423 if (!rwq_ind_tbl)
5424 return ERR_PTR(-ENOMEM);
5425
5426 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5427 in = kvzalloc(inlen, GFP_KERNEL);
5428 if (!in) {
5429 err = -ENOMEM;
5430 goto err;
5431 }
5432
5433 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5434
5435 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5436 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5437
5438 for (i = 0; i < sz; i++)
5439 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5440
5441 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5442 kvfree(in);
5443
5444 if (err)
5445 goto err;
5446
5447 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5448 if (udata->outlen) {
5449 resp.response_length = offsetof(typeof(resp), response_length) +
5450 sizeof(resp.response_length);
5451 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5452 if (err)
5453 goto err_copy;
5454 }
5455
5456 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5457
5458 err_copy:
5459 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5460 err:
5461 kfree(rwq_ind_tbl);
5462 return ERR_PTR(err);
5463 }
5464
5465 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5466 {
5467 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5468 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5469
5470 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5471
5472 kfree(rwq_ind_tbl);
5473 return 0;
5474 }
5475
5476 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5477 u32 wq_attr_mask, struct ib_udata *udata)
5478 {
5479 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5480 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5481 struct mlx5_ib_modify_wq ucmd = {};
5482 size_t required_cmd_sz;
5483 int curr_wq_state;
5484 int wq_state;
5485 int inlen;
5486 int err;
5487 void *rqc;
5488 void *in;
5489
5490 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5491 if (udata->inlen < required_cmd_sz)
5492 return -EINVAL;
5493
5494 if (udata->inlen > sizeof(ucmd) &&
5495 !ib_is_udata_cleared(udata, sizeof(ucmd),
5496 udata->inlen - sizeof(ucmd)))
5497 return -EOPNOTSUPP;
5498
5499 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5500 return -EFAULT;
5501
5502 if (ucmd.comp_mask || ucmd.reserved)
5503 return -EOPNOTSUPP;
5504
5505 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5506 in = kvzalloc(inlen, GFP_KERNEL);
5507 if (!in)
5508 return -ENOMEM;
5509
5510 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5511
5512 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5513 wq_attr->curr_wq_state : wq->state;
5514 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5515 wq_attr->wq_state : curr_wq_state;
5516 if (curr_wq_state == IB_WQS_ERR)
5517 curr_wq_state = MLX5_RQC_STATE_ERR;
5518 if (wq_state == IB_WQS_ERR)
5519 wq_state = MLX5_RQC_STATE_ERR;
5520 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5521 MLX5_SET(rqc, rqc, state, wq_state);
5522
5523 if (wq_attr_mask & IB_WQ_FLAGS) {
5524 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5525 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5526 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5527 mlx5_ib_dbg(dev, "VLAN offloads are not "
5528 "supported\n");
5529 err = -EOPNOTSUPP;
5530 goto out;
5531 }
5532 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5533 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5534 MLX5_SET(rqc, rqc, vsd,
5535 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5536 }
5537
5538 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5539 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5540 err = -EOPNOTSUPP;
5541 goto out;
5542 }
5543 }
5544
5545 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5546 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5547 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5548 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5549 MLX5_SET(rqc, rqc, counter_set_id,
5550 dev->port->cnts.set_id);
5551 } else
5552 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5553 dev->ib_dev.name);
5554 }
5555
5556 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5557 if (!err)
5558 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5559
5560 out:
5561 kvfree(in);
5562 return err;
5563 }
CRIS linux kernel tree