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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / infiniband / hw / mthca / mthca_qp.c
blobd21960cd9a49c1f4ad8c5067bc01ba3709f0d073
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/sched.h>
39
40 #include <asm/io.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
50
51 enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
58 };
59
60 enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69 };
70
71 enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77 };
78
79 enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83 };
84
85 enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100 };
101
102 enum {
103 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
104 };
105
106 struct mthca_qp_path {
107 __be32 port_pkey;
108 u8 rnr_retry;
109 u8 g_mylmc;
110 __be16 rlid;
111 u8 ackto;
112 u8 mgid_index;
113 u8 static_rate;
114 u8 hop_limit;
115 __be32 sl_tclass_flowlabel;
116 u8 rgid[16];
117 } __attribute__((packed));
118
119 struct mthca_qp_context {
120 __be32 flags;
121 __be32 tavor_sched_queue; /* Reserved on Arbel */
122 u8 mtu_msgmax;
123 u8 rq_size_stride; /* Reserved on Tavor */
124 u8 sq_size_stride; /* Reserved on Tavor */
125 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
126 __be32 usr_page;
127 __be32 local_qpn;
128 __be32 remote_qpn;
129 u32 reserved1[2];
130 struct mthca_qp_path pri_path;
131 struct mthca_qp_path alt_path;
132 __be32 rdd;
133 __be32 pd;
134 __be32 wqe_base;
135 __be32 wqe_lkey;
136 __be32 params1;
137 __be32 reserved2;
138 __be32 next_send_psn;
139 __be32 cqn_snd;
140 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
141 __be32 snd_db_index; /* (debugging only entries) */
142 __be32 last_acked_psn;
143 __be32 ssn;
144 __be32 params2;
145 __be32 rnr_nextrecvpsn;
146 __be32 ra_buff_indx;
147 __be32 cqn_rcv;
148 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
149 __be32 rcv_db_index; /* (debugging only entries) */
150 __be32 qkey;
151 __be32 srqn;
152 __be32 rmsn;
153 __be16 rq_wqe_counter; /* reserved on Tavor */
154 __be16 sq_wqe_counter; /* reserved on Tavor */
155 u32 reserved3[18];
156 } __attribute__((packed));
157
158 struct mthca_qp_param {
159 __be32 opt_param_mask;
160 u32 reserved1;
161 struct mthca_qp_context context;
162 u32 reserved2[62];
163 } __attribute__((packed));
164
165 enum {
166 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
167 MTHCA_QP_OPTPAR_RRE = 1 << 1,
168 MTHCA_QP_OPTPAR_RAE = 1 << 2,
169 MTHCA_QP_OPTPAR_RWE = 1 << 3,
170 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
171 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
172 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
173 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
174 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
175 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
176 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
177 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
178 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
179 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
180 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
181 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
182 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
183 };
184
185 static const u8 mthca_opcode[] = {
186 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
187 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
188 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
189 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
190 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
191 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
192 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
193 };
194
195 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
196 {
197 return qp->qpn >= dev->qp_table.sqp_start &&
198 qp->qpn <= dev->qp_table.sqp_start + 3;
199 }
200
201 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
202 {
203 return qp->qpn >= dev->qp_table.sqp_start &&
204 qp->qpn <= dev->qp_table.sqp_start + 1;
205 }
206
207 static void *get_recv_wqe(struct mthca_qp *qp, int n)
208 {
209 if (qp->is_direct)
210 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
211 else
212 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
213 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
214 }
215
216 static void *get_send_wqe(struct mthca_qp *qp, int n)
217 {
218 if (qp->is_direct)
219 return qp->queue.direct.buf + qp->send_wqe_offset +
220 (n << qp->sq.wqe_shift);
221 else
222 return qp->queue.page_list[(qp->send_wqe_offset +
223 (n << qp->sq.wqe_shift)) >>
224 PAGE_SHIFT].buf +
225 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
226 (PAGE_SIZE - 1));
227 }
228
229 static void mthca_wq_reset(struct mthca_wq *wq)
230 {
231 wq->next_ind = 0;
232 wq->last_comp = wq->max - 1;
233 wq->head = 0;
234 wq->tail = 0;
235 }
236
237 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
238 enum ib_event_type event_type)
239 {
240 struct mthca_qp *qp;
241 struct ib_event event;
242
243 spin_lock(&dev->qp_table.lock);
244 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
245 if (qp)
246 ++qp->refcount;
247 spin_unlock(&dev->qp_table.lock);
248
249 if (!qp) {
250 mthca_warn(dev, "Async event %d for bogus QP %08x\n",
251 event_type, qpn);
252 return;
253 }
254
255 if (event_type == IB_EVENT_PATH_MIG)
256 qp->port = qp->alt_port;
257
258 event.device = &dev->ib_dev;
259 event.event = event_type;
260 event.element.qp = &qp->ibqp;
261 if (qp->ibqp.event_handler)
262 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
263
264 spin_lock(&dev->qp_table.lock);
265 if (!--qp->refcount)
266 wake_up(&qp->wait);
267 spin_unlock(&dev->qp_table.lock);
268 }
269
270 static int to_mthca_state(enum ib_qp_state ib_state)
271 {
272 switch (ib_state) {
273 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
274 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
275 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
276 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
277 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
278 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
279 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
280 default: return -1;
281 }
282 }
283
284 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
285
286 static int to_mthca_st(int transport)
287 {
288 switch (transport) {
289 case RC: return MTHCA_QP_ST_RC;
290 case UC: return MTHCA_QP_ST_UC;
291 case UD: return MTHCA_QP_ST_UD;
292 case RD: return MTHCA_QP_ST_RD;
293 case MLX: return MTHCA_QP_ST_MLX;
294 default: return -1;
295 }
296 }
297
298 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
299 int attr_mask)
300 {
301 if (attr_mask & IB_QP_PKEY_INDEX)
302 sqp->pkey_index = attr->pkey_index;
303 if (attr_mask & IB_QP_QKEY)
304 sqp->qkey = attr->qkey;
305 if (attr_mask & IB_QP_SQ_PSN)
306 sqp->send_psn = attr->sq_psn;
307 }
308
309 static void init_port(struct mthca_dev *dev, int port)
310 {
311 int err;
312 struct mthca_init_ib_param param;
313
314 memset(&param, 0, sizeof param);
315
316 param.port_width = dev->limits.port_width_cap;
317 param.vl_cap = dev->limits.vl_cap;
318 param.mtu_cap = dev->limits.mtu_cap;
319 param.gid_cap = dev->limits.gid_table_len;
320 param.pkey_cap = dev->limits.pkey_table_len;
321
322 err = mthca_INIT_IB(dev, &param, port);
323 if (err)
324 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
325 }
326
327 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
328 int attr_mask)
329 {
330 u8 dest_rd_atomic;
331 u32 access_flags;
332 u32 hw_access_flags = 0;
333
334 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
335 dest_rd_atomic = attr->max_dest_rd_atomic;
336 else
337 dest_rd_atomic = qp->resp_depth;
338
339 if (attr_mask & IB_QP_ACCESS_FLAGS)
340 access_flags = attr->qp_access_flags;
341 else
342 access_flags = qp->atomic_rd_en;
343
344 if (!dest_rd_atomic)
345 access_flags &= IB_ACCESS_REMOTE_WRITE;
346
347 if (access_flags & IB_ACCESS_REMOTE_READ)
348 hw_access_flags |= MTHCA_QP_BIT_RRE;
349 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
350 hw_access_flags |= MTHCA_QP_BIT_RAE;
351 if (access_flags & IB_ACCESS_REMOTE_WRITE)
352 hw_access_flags |= MTHCA_QP_BIT_RWE;
353
354 return cpu_to_be32(hw_access_flags);
355 }
356
357 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
358 {
359 switch (mthca_state) {
360 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
361 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
362 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
363 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
364 case MTHCA_QP_STATE_DRAINING:
365 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
366 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
367 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
368 default: return -1;
369 }
370 }
371
372 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
373 {
374 switch (mthca_mig_state) {
375 case 0: return IB_MIG_ARMED;
376 case 1: return IB_MIG_REARM;
377 case 3: return IB_MIG_MIGRATED;
378 default: return -1;
379 }
380 }
381
382 static int to_ib_qp_access_flags(int mthca_flags)
383 {
384 int ib_flags = 0;
385
386 if (mthca_flags & MTHCA_QP_BIT_RRE)
387 ib_flags |= IB_ACCESS_REMOTE_READ;
388 if (mthca_flags & MTHCA_QP_BIT_RWE)
389 ib_flags |= IB_ACCESS_REMOTE_WRITE;
390 if (mthca_flags & MTHCA_QP_BIT_RAE)
391 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
392
393 return ib_flags;
394 }
395
396 static void to_rdma_ah_attr(struct mthca_dev *dev,
397 struct rdma_ah_attr *ah_attr,
398 struct mthca_qp_path *path)
399 {
400 u8 port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
401
402 memset(ah_attr, 0, sizeof(*ah_attr));
403
404 if (port_num == 0 || port_num > dev->limits.num_ports)
405 return;
406 ah_attr->type = rdma_ah_find_type(&dev->ib_dev, port_num);
407 rdma_ah_set_port_num(ah_attr, port_num);
408
409 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
410 rdma_ah_set_sl(ah_attr, be32_to_cpu(path->sl_tclass_flowlabel) >> 28);
411 rdma_ah_set_path_bits(ah_attr, path->g_mylmc & 0x7f);
412 rdma_ah_set_static_rate(ah_attr,
413 mthca_rate_to_ib(dev,
414 path->static_rate & 0xf,
415 port_num));
416 if (path->g_mylmc & (1 << 7)) {
417 u32 tc_fl = be32_to_cpu(path->sl_tclass_flowlabel);
418
419 rdma_ah_set_grh(ah_attr, NULL,
420 tc_fl & 0xfffff,
421 path->mgid_index &
422 (dev->limits.gid_table_len - 1),
423 path->hop_limit,
424 (tc_fl >> 20) & 0xff);
425 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
426 }
427 }
428
429 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
430 struct ib_qp_init_attr *qp_init_attr)
431 {
432 struct mthca_dev *dev = to_mdev(ibqp->device);
433 struct mthca_qp *qp = to_mqp(ibqp);
434 int err = 0;
435 struct mthca_mailbox *mailbox = NULL;
436 struct mthca_qp_param *qp_param;
437 struct mthca_qp_context *context;
438 int mthca_state;
439
440 mutex_lock(&qp->mutex);
441
442 if (qp->state == IB_QPS_RESET) {
443 qp_attr->qp_state = IB_QPS_RESET;
444 goto done;
445 }
446
447 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
448 if (IS_ERR(mailbox)) {
449 err = PTR_ERR(mailbox);
450 goto out;
451 }
452
453 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox);
454 if (err) {
455 mthca_warn(dev, "QUERY_QP failed (%d)\n", err);
456 goto out_mailbox;
457 }
458
459 qp_param = mailbox->buf;
460 context = &qp_param->context;
461 mthca_state = be32_to_cpu(context->flags) >> 28;
462
463 qp->state = to_ib_qp_state(mthca_state);
464 qp_attr->qp_state = qp->state;
465 qp_attr->path_mtu = context->mtu_msgmax >> 5;
466 qp_attr->path_mig_state =
467 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
468 qp_attr->qkey = be32_to_cpu(context->qkey);
469 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
470 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
471 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
472 qp_attr->qp_access_flags =
473 to_ib_qp_access_flags(be32_to_cpu(context->params2));
474
475 if (qp->transport == RC || qp->transport == UC) {
476 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
477 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
478 qp_attr->alt_pkey_index =
479 be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
480 qp_attr->alt_port_num =
481 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
482 }
483
484 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
485 qp_attr->port_num =
486 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
487
488 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
489 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
490
491 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
492
493 qp_attr->max_dest_rd_atomic =
494 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
495 qp_attr->min_rnr_timer =
496 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
497 qp_attr->timeout = context->pri_path.ackto >> 3;
498 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
499 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
500 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
501
502 done:
503 qp_attr->cur_qp_state = qp_attr->qp_state;
504 qp_attr->cap.max_send_wr = qp->sq.max;
505 qp_attr->cap.max_recv_wr = qp->rq.max;
506 qp_attr->cap.max_send_sge = qp->sq.max_gs;
507 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
508 qp_attr->cap.max_inline_data = qp->max_inline_data;
509
510 qp_init_attr->cap = qp_attr->cap;
511 qp_init_attr->sq_sig_type = qp->sq_policy;
512
513 out_mailbox:
514 mthca_free_mailbox(dev, mailbox);
515
516 out:
517 mutex_unlock(&qp->mutex);
518 return err;
519 }
520
521 static int mthca_path_set(struct mthca_dev *dev, const struct rdma_ah_attr *ah,
522 struct mthca_qp_path *path, u8 port)
523 {
524 path->g_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
525 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
526 path->static_rate = mthca_get_rate(dev, rdma_ah_get_static_rate(ah),
527 port);
528
529 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
530 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
531
532 if (grh->sgid_index >= dev->limits.gid_table_len) {
533 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
534 grh->sgid_index,
535 dev->limits.gid_table_len - 1);
536 return -1;
537 }
538
539 path->g_mylmc |= 1 << 7;
540 path->mgid_index = grh->sgid_index;
541 path->hop_limit = grh->hop_limit;
542 path->sl_tclass_flowlabel =
543 cpu_to_be32((rdma_ah_get_sl(ah) << 28) |
544 (grh->traffic_class << 20) |
545 (grh->flow_label));
546 memcpy(path->rgid, grh->dgid.raw, 16);
547 } else {
548 path->sl_tclass_flowlabel = cpu_to_be32(rdma_ah_get_sl(ah) <<
549 28);
550 }
551
552 return 0;
553 }
554
555 static int __mthca_modify_qp(struct ib_qp *ibqp,
556 const struct ib_qp_attr *attr, int attr_mask,
557 enum ib_qp_state cur_state, enum ib_qp_state new_state)
558 {
559 struct mthca_dev *dev = to_mdev(ibqp->device);
560 struct mthca_qp *qp = to_mqp(ibqp);
561 struct mthca_mailbox *mailbox;
562 struct mthca_qp_param *qp_param;
563 struct mthca_qp_context *qp_context;
564 u32 sqd_event = 0;
565 int err = -EINVAL;
566
567 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
568 if (IS_ERR(mailbox)) {
569 err = PTR_ERR(mailbox);
570 goto out;
571 }
572 qp_param = mailbox->buf;
573 qp_context = &qp_param->context;
574 memset(qp_param, 0, sizeof *qp_param);
575
576 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
577 (to_mthca_st(qp->transport) << 16));
578 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
579 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
580 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
581 else {
582 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
583 switch (attr->path_mig_state) {
584 case IB_MIG_MIGRATED:
585 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
586 break;
587 case IB_MIG_REARM:
588 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
589 break;
590 case IB_MIG_ARMED:
591 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
592 break;
593 }
594 }
595
596 /* leave tavor_sched_queue as 0 */
597
598 if (qp->transport == MLX || qp->transport == UD)
599 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
600 else if (attr_mask & IB_QP_PATH_MTU) {
601 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
602 mthca_dbg(dev, "path MTU (%u) is invalid\n",
603 attr->path_mtu);
604 goto out_mailbox;
605 }
606 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
607 }
608
609 if (mthca_is_memfree(dev)) {
610 if (qp->rq.max)
611 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
612 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
613
614 if (qp->sq.max)
615 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
616 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
617 }
618
619 /* leave arbel_sched_queue as 0 */
620
621 if (qp->ibqp.uobject)
622 qp_context->usr_page =
623 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
624 else
625 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
626 qp_context->local_qpn = cpu_to_be32(qp->qpn);
627 if (attr_mask & IB_QP_DEST_QPN) {
628 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
629 }
630
631 if (qp->transport == MLX)
632 qp_context->pri_path.port_pkey |=
633 cpu_to_be32(qp->port << 24);
634 else {
635 if (attr_mask & IB_QP_PORT) {
636 qp_context->pri_path.port_pkey |=
637 cpu_to_be32(attr->port_num << 24);
638 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
639 }
640 }
641
642 if (attr_mask & IB_QP_PKEY_INDEX) {
643 qp_context->pri_path.port_pkey |=
644 cpu_to_be32(attr->pkey_index);
645 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
646 }
647
648 if (attr_mask & IB_QP_RNR_RETRY) {
649 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
650 attr->rnr_retry << 5;
651 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
652 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
653 }
654
655 if (attr_mask & IB_QP_AV) {
656 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
657 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
658 goto out_mailbox;
659
660 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
661 }
662
663 if (ibqp->qp_type == IB_QPT_RC &&
664 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
665 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
666
667 if (mthca_is_memfree(dev))
668 qp_context->rlkey_arbel_sched_queue |= sched_queue;
669 else
670 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
671
672 qp_param->opt_param_mask |=
673 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
674 }
675
676 if (attr_mask & IB_QP_TIMEOUT) {
677 qp_context->pri_path.ackto = attr->timeout << 3;
678 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
679 }
680
681 if (attr_mask & IB_QP_ALT_PATH) {
682 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
683 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
684 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
685 goto out_mailbox;
686 }
687
688 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
689 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
690 attr->alt_port_num);
691 goto out_mailbox;
692 }
693
694 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
695 rdma_ah_get_port_num(&attr->alt_ah_attr)))
696 goto out_mailbox;
697
698 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
699 attr->alt_port_num << 24);
700 qp_context->alt_path.ackto = attr->alt_timeout << 3;
701 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
702 }
703
704 /* leave rdd as 0 */
705 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
706 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
707 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
708 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
709 (MTHCA_FLIGHT_LIMIT << 24) |
710 MTHCA_QP_BIT_SWE);
711 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
712 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
713 if (attr_mask & IB_QP_RETRY_CNT) {
714 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
715 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
716 }
717
718 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
719 if (attr->max_rd_atomic) {
720 qp_context->params1 |=
721 cpu_to_be32(MTHCA_QP_BIT_SRE |
722 MTHCA_QP_BIT_SAE);
723 qp_context->params1 |=
724 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
725 }
726 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
727 }
728
729 if (attr_mask & IB_QP_SQ_PSN)
730 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
731 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
732
733 if (mthca_is_memfree(dev)) {
734 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
735 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
736 }
737
738 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
739 if (attr->max_dest_rd_atomic)
740 qp_context->params2 |=
741 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
742
743 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
744 }
745
746 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
747 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
748 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
749 MTHCA_QP_OPTPAR_RRE |
750 MTHCA_QP_OPTPAR_RAE);
751 }
752
753 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
754
755 if (ibqp->srq)
756 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
757
758 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
759 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
760 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
761 }
762 if (attr_mask & IB_QP_RQ_PSN)
763 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
764
765 qp_context->ra_buff_indx =
766 cpu_to_be32(dev->qp_table.rdb_base +
767 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
768 dev->qp_table.rdb_shift));
769
770 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
771
772 if (mthca_is_memfree(dev))
773 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
774
775 if (attr_mask & IB_QP_QKEY) {
776 qp_context->qkey = cpu_to_be32(attr->qkey);
777 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
778 }
779
780 if (ibqp->srq)
781 qp_context->srqn = cpu_to_be32(1 << 24 |
782 to_msrq(ibqp->srq)->srqn);
783
784 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
785 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
786 attr->en_sqd_async_notify)
787 sqd_event = 1 << 31;
788
789 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
790 mailbox, sqd_event);
791 if (err) {
792 mthca_warn(dev, "modify QP %d->%d returned %d.\n",
793 cur_state, new_state, err);
794 goto out_mailbox;
795 }
796
797 qp->state = new_state;
798 if (attr_mask & IB_QP_ACCESS_FLAGS)
799 qp->atomic_rd_en = attr->qp_access_flags;
800 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
801 qp->resp_depth = attr->max_dest_rd_atomic;
802 if (attr_mask & IB_QP_PORT)
803 qp->port = attr->port_num;
804 if (attr_mask & IB_QP_ALT_PATH)
805 qp->alt_port = attr->alt_port_num;
806
807 if (is_sqp(dev, qp))
808 store_attrs(to_msqp(qp), attr, attr_mask);
809
810 /*
811 * If we moved QP0 to RTR, bring the IB link up; if we moved
812 * QP0 to RESET or ERROR, bring the link back down.
813 */
814 if (is_qp0(dev, qp)) {
815 if (cur_state != IB_QPS_RTR &&
816 new_state == IB_QPS_RTR)
817 init_port(dev, qp->port);
818
819 if (cur_state != IB_QPS_RESET &&
820 cur_state != IB_QPS_ERR &&
821 (new_state == IB_QPS_RESET ||
822 new_state == IB_QPS_ERR))
823 mthca_CLOSE_IB(dev, qp->port);
824 }
825
826 /*
827 * If we moved a kernel QP to RESET, clean up all old CQ
828 * entries and reinitialize the QP.
829 */
830 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
831 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
832 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
833 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
834 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
835
836 mthca_wq_reset(&qp->sq);
837 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
838
839 mthca_wq_reset(&qp->rq);
840 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
841
842 if (mthca_is_memfree(dev)) {
843 *qp->sq.db = 0;
844 *qp->rq.db = 0;
845 }
846 }
847
848 out_mailbox:
849 mthca_free_mailbox(dev, mailbox);
850 out:
851 return err;
852 }
853
854 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
855 struct ib_udata *udata)
856 {
857 struct mthca_dev *dev = to_mdev(ibqp->device);
858 struct mthca_qp *qp = to_mqp(ibqp);
859 enum ib_qp_state cur_state, new_state;
860 int err = -EINVAL;
861
862 mutex_lock(&qp->mutex);
863 if (attr_mask & IB_QP_CUR_STATE) {
864 cur_state = attr->cur_qp_state;
865 } else {
866 spin_lock_irq(&qp->sq.lock);
867 spin_lock(&qp->rq.lock);
868 cur_state = qp->state;
869 spin_unlock(&qp->rq.lock);
870 spin_unlock_irq(&qp->sq.lock);
871 }
872
873 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
874
875 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
876 IB_LINK_LAYER_UNSPECIFIED)) {
877 mthca_dbg(dev, "Bad QP transition (transport %d) "
878 "%d->%d with attr 0x%08x\n",
879 qp->transport, cur_state, new_state,
880 attr_mask);
881 goto out;
882 }
883
884 if ((attr_mask & IB_QP_PKEY_INDEX) &&
885 attr->pkey_index >= dev->limits.pkey_table_len) {
886 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
887 attr->pkey_index, dev->limits.pkey_table_len-1);
888 goto out;
889 }
890
891 if ((attr_mask & IB_QP_PORT) &&
892 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
893 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
894 goto out;
895 }
896
897 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
898 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
899 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
900 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
901 goto out;
902 }
903
904 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
905 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
906 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
907 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
908 goto out;
909 }
910
911 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
912 err = 0;
913 goto out;
914 }
915
916 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
917
918 out:
919 mutex_unlock(&qp->mutex);
920 return err;
921 }
922
923 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
924 {
925 /*
926 * Calculate the maximum size of WQE s/g segments, excluding
927 * the next segment and other non-data segments.
928 */
929 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
930
931 switch (qp->transport) {
932 case MLX:
933 max_data_size -= 2 * sizeof (struct mthca_data_seg);
934 break;
935
936 case UD:
937 if (mthca_is_memfree(dev))
938 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
939 else
940 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
941 break;
942
943 default:
944 max_data_size -= sizeof (struct mthca_raddr_seg);
945 break;
946 }
947
948 return max_data_size;
949 }
950
951 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
952 {
953 /* We don't support inline data for kernel QPs (yet). */
954 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
955 }
956
957 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
958 struct mthca_pd *pd,
959 struct mthca_qp *qp)
960 {
961 int max_data_size = mthca_max_data_size(dev, qp,
962 min(dev->limits.max_desc_sz,
963 1 << qp->sq.wqe_shift));
964
965 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
966
967 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
968 max_data_size / sizeof (struct mthca_data_seg));
969 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
970 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
971 sizeof (struct mthca_next_seg)) /
972 sizeof (struct mthca_data_seg));
973 }
974
975 /*
976 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
977 * rq.max_gs and sq.max_gs must all be assigned.
978 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
979 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
980 * queue)
981 */
982 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
983 struct mthca_pd *pd,
984 struct mthca_qp *qp)
985 {
986 int size;
987 int err = -ENOMEM;
988
989 size = sizeof (struct mthca_next_seg) +
990 qp->rq.max_gs * sizeof (struct mthca_data_seg);
991
992 if (size > dev->limits.max_desc_sz)
993 return -EINVAL;
994
995 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
996 qp->rq.wqe_shift++)
997 ; /* nothing */
998
999 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1000 switch (qp->transport) {
1001 case MLX:
1002 size += 2 * sizeof (struct mthca_data_seg);
1003 break;
1004
1005 case UD:
1006 size += mthca_is_memfree(dev) ?
1007 sizeof (struct mthca_arbel_ud_seg) :
1008 sizeof (struct mthca_tavor_ud_seg);
1009 break;
1010
1011 case UC:
1012 size += sizeof (struct mthca_raddr_seg);
1013 break;
1014
1015 case RC:
1016 size += sizeof (struct mthca_raddr_seg);
1017 /*
1018 * An atomic op will require an atomic segment, a
1019 * remote address segment and one scatter entry.
1020 */
1021 size = max_t(int, size,
1022 sizeof (struct mthca_atomic_seg) +
1023 sizeof (struct mthca_raddr_seg) +
1024 sizeof (struct mthca_data_seg));
1025 break;
1026
1027 default:
1028 break;
1029 }
1030
1031 /* Make sure that we have enough space for a bind request */
1032 size = max_t(int, size, sizeof (struct mthca_bind_seg));
1033
1034 size += sizeof (struct mthca_next_seg);
1035
1036 if (size > dev->limits.max_desc_sz)
1037 return -EINVAL;
1038
1039 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1040 qp->sq.wqe_shift++)
1041 ; /* nothing */
1042
1043 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1044 1 << qp->sq.wqe_shift);
1045
1046 /*
1047 * If this is a userspace QP, we don't actually have to
1048 * allocate anything. All we need is to calculate the WQE
1049 * sizes and the send_wqe_offset, so we're done now.
1050 */
1051 if (pd->ibpd.uobject)
1052 return 0;
1053
1054 size = PAGE_ALIGN(qp->send_wqe_offset +
1055 (qp->sq.max << qp->sq.wqe_shift));
1056
1057 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1058 GFP_KERNEL);
1059 if (!qp->wrid)
1060 goto err_out;
1061
1062 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1063 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1064 if (err)
1065 goto err_out;
1066
1067 return 0;
1068
1069 err_out:
1070 kfree(qp->wrid);
1071 return err;
1072 }
1073
1074 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1075 struct mthca_qp *qp)
1076 {
1077 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1078 (qp->sq.max << qp->sq.wqe_shift)),
1079 &qp->queue, qp->is_direct, &qp->mr);
1080 kfree(qp->wrid);
1081 }
1082
1083 static int mthca_map_memfree(struct mthca_dev *dev,
1084 struct mthca_qp *qp)
1085 {
1086 int ret;
1087
1088 if (mthca_is_memfree(dev)) {
1089 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1090 if (ret)
1091 return ret;
1092
1093 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1094 if (ret)
1095 goto err_qpc;
1096
1097 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1098 qp->qpn << dev->qp_table.rdb_shift);
1099 if (ret)
1100 goto err_eqpc;
1101
1102 }
1103
1104 return 0;
1105
1106 err_eqpc:
1107 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1108
1109 err_qpc:
1110 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1111
1112 return ret;
1113 }
1114
1115 static void mthca_unmap_memfree(struct mthca_dev *dev,
1116 struct mthca_qp *qp)
1117 {
1118 mthca_table_put(dev, dev->qp_table.rdb_table,
1119 qp->qpn << dev->qp_table.rdb_shift);
1120 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1121 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1122 }
1123
1124 static int mthca_alloc_memfree(struct mthca_dev *dev,
1125 struct mthca_qp *qp)
1126 {
1127 if (mthca_is_memfree(dev)) {
1128 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1129 qp->qpn, &qp->rq.db);
1130 if (qp->rq.db_index < 0)
1131 return -ENOMEM;
1132
1133 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1134 qp->qpn, &qp->sq.db);
1135 if (qp->sq.db_index < 0) {
1136 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1137 return -ENOMEM;
1138 }
1139 }
1140
1141 return 0;
1142 }
1143
1144 static void mthca_free_memfree(struct mthca_dev *dev,
1145 struct mthca_qp *qp)
1146 {
1147 if (mthca_is_memfree(dev)) {
1148 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1149 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1150 }
1151 }
1152
1153 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1154 struct mthca_pd *pd,
1155 struct mthca_cq *send_cq,
1156 struct mthca_cq *recv_cq,
1157 enum ib_sig_type send_policy,
1158 struct mthca_qp *qp)
1159 {
1160 int ret;
1161 int i;
1162 struct mthca_next_seg *next;
1163
1164 qp->refcount = 1;
1165 init_waitqueue_head(&qp->wait);
1166 mutex_init(&qp->mutex);
1167 qp->state = IB_QPS_RESET;
1168 qp->atomic_rd_en = 0;
1169 qp->resp_depth = 0;
1170 qp->sq_policy = send_policy;
1171 mthca_wq_reset(&qp->sq);
1172 mthca_wq_reset(&qp->rq);
1173
1174 spin_lock_init(&qp->sq.lock);
1175 spin_lock_init(&qp->rq.lock);
1176
1177 ret = mthca_map_memfree(dev, qp);
1178 if (ret)
1179 return ret;
1180
1181 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1182 if (ret) {
1183 mthca_unmap_memfree(dev, qp);
1184 return ret;
1185 }
1186
1187 mthca_adjust_qp_caps(dev, pd, qp);
1188
1189 /*
1190 * If this is a userspace QP, we're done now. The doorbells
1191 * will be allocated and buffers will be initialized in
1192 * userspace.
1193 */
1194 if (pd->ibpd.uobject)
1195 return 0;
1196
1197 ret = mthca_alloc_memfree(dev, qp);
1198 if (ret) {
1199 mthca_free_wqe_buf(dev, qp);
1200 mthca_unmap_memfree(dev, qp);
1201 return ret;
1202 }
1203
1204 if (mthca_is_memfree(dev)) {
1205 struct mthca_data_seg *scatter;
1206 int size = (sizeof (struct mthca_next_seg) +
1207 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1208
1209 for (i = 0; i < qp->rq.max; ++i) {
1210 next = get_recv_wqe(qp, i);
1211 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1212 qp->rq.wqe_shift);
1213 next->ee_nds = cpu_to_be32(size);
1214
1215 for (scatter = (void *) (next + 1);
1216 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1217 ++scatter)
1218 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1219 }
1220
1221 for (i = 0; i < qp->sq.max; ++i) {
1222 next = get_send_wqe(qp, i);
1223 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1224 qp->sq.wqe_shift) +
1225 qp->send_wqe_offset);
1226 }
1227 } else {
1228 for (i = 0; i < qp->rq.max; ++i) {
1229 next = get_recv_wqe(qp, i);
1230 next->nda_op = htonl((((i + 1) % qp->rq.max) <<
1231 qp->rq.wqe_shift) | 1);
1232 }
1233
1234 }
1235
1236 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1237 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1238
1239 return 0;
1240 }
1241
1242 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1243 struct mthca_pd *pd, struct mthca_qp *qp)
1244 {
1245 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1246
1247 /* Sanity check QP size before proceeding */
1248 if (cap->max_send_wr > dev->limits.max_wqes ||
1249 cap->max_recv_wr > dev->limits.max_wqes ||
1250 cap->max_send_sge > dev->limits.max_sg ||
1251 cap->max_recv_sge > dev->limits.max_sg ||
1252 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1253 return -EINVAL;
1254
1255 /*
1256 * For MLX transport we need 2 extra send gather entries:
1257 * one for the header and one for the checksum at the end
1258 */
1259 if (qp->transport == MLX && cap->max_send_sge + 2 > dev->limits.max_sg)
1260 return -EINVAL;
1261
1262 if (mthca_is_memfree(dev)) {
1263 qp->rq.max = cap->max_recv_wr ?
1264 roundup_pow_of_two(cap->max_recv_wr) : 0;
1265 qp->sq.max = cap->max_send_wr ?
1266 roundup_pow_of_two(cap->max_send_wr) : 0;
1267 } else {
1268 qp->rq.max = cap->max_recv_wr;
1269 qp->sq.max = cap->max_send_wr;
1270 }
1271
1272 qp->rq.max_gs = cap->max_recv_sge;
1273 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1274 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1275 MTHCA_INLINE_CHUNK_SIZE) /
1276 sizeof (struct mthca_data_seg));
1277
1278 return 0;
1279 }
1280
1281 int mthca_alloc_qp(struct mthca_dev *dev,
1282 struct mthca_pd *pd,
1283 struct mthca_cq *send_cq,
1284 struct mthca_cq *recv_cq,
1285 enum ib_qp_type type,
1286 enum ib_sig_type send_policy,
1287 struct ib_qp_cap *cap,
1288 struct mthca_qp *qp)
1289 {
1290 int err;
1291
1292 switch (type) {
1293 case IB_QPT_RC: qp->transport = RC; break;
1294 case IB_QPT_UC: qp->transport = UC; break;
1295 case IB_QPT_UD: qp->transport = UD; break;
1296 default: return -EINVAL;
1297 }
1298
1299 err = mthca_set_qp_size(dev, cap, pd, qp);
1300 if (err)
1301 return err;
1302
1303 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1304 if (qp->qpn == -1)
1305 return -ENOMEM;
1306
1307 /* initialize port to zero for error-catching. */
1308 qp->port = 0;
1309
1310 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1311 send_policy, qp);
1312 if (err) {
1313 mthca_free(&dev->qp_table.alloc, qp->qpn);
1314 return err;
1315 }
1316
1317 spin_lock_irq(&dev->qp_table.lock);
1318 mthca_array_set(&dev->qp_table.qp,
1319 qp->qpn & (dev->limits.num_qps - 1), qp);
1320 spin_unlock_irq(&dev->qp_table.lock);
1321
1322 return 0;
1323 }
1324
1325 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1326 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1327 {
1328 if (send_cq == recv_cq) {
1329 spin_lock_irq(&send_cq->lock);
1330 __acquire(&recv_cq->lock);
1331 } else if (send_cq->cqn < recv_cq->cqn) {
1332 spin_lock_irq(&send_cq->lock);
1333 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1334 } else {
1335 spin_lock_irq(&recv_cq->lock);
1336 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1337 }
1338 }
1339
1340 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1341 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1342 {
1343 if (send_cq == recv_cq) {
1344 __release(&recv_cq->lock);
1345 spin_unlock_irq(&send_cq->lock);
1346 } else if (send_cq->cqn < recv_cq->cqn) {
1347 spin_unlock(&recv_cq->lock);
1348 spin_unlock_irq(&send_cq->lock);
1349 } else {
1350 spin_unlock(&send_cq->lock);
1351 spin_unlock_irq(&recv_cq->lock);
1352 }
1353 }
1354
1355 int mthca_alloc_sqp(struct mthca_dev *dev,
1356 struct mthca_pd *pd,
1357 struct mthca_cq *send_cq,
1358 struct mthca_cq *recv_cq,
1359 enum ib_sig_type send_policy,
1360 struct ib_qp_cap *cap,
1361 int qpn,
1362 int port,
1363 struct mthca_sqp *sqp)
1364 {
1365 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1366 int err;
1367
1368 sqp->qp.transport = MLX;
1369 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1370 if (err)
1371 return err;
1372
1373 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1374 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1375 &sqp->header_dma, GFP_KERNEL);
1376 if (!sqp->header_buf)
1377 return -ENOMEM;
1378
1379 spin_lock_irq(&dev->qp_table.lock);
1380 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1381 err = -EBUSY;
1382 else
1383 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1384 spin_unlock_irq(&dev->qp_table.lock);
1385
1386 if (err)
1387 goto err_out;
1388
1389 sqp->qp.port = port;
1390 sqp->qp.qpn = mqpn;
1391 sqp->qp.transport = MLX;
1392
1393 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1394 send_policy, &sqp->qp);
1395 if (err)
1396 goto err_out_free;
1397
1398 atomic_inc(&pd->sqp_count);
1399
1400 return 0;
1401
1402 err_out_free:
1403 /*
1404 * Lock CQs here, so that CQ polling code can do QP lookup
1405 * without taking a lock.
1406 */
1407 mthca_lock_cqs(send_cq, recv_cq);
1408
1409 spin_lock(&dev->qp_table.lock);
1410 mthca_array_clear(&dev->qp_table.qp, mqpn);
1411 spin_unlock(&dev->qp_table.lock);
1412
1413 mthca_unlock_cqs(send_cq, recv_cq);
1414
1415 err_out:
1416 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1417 sqp->header_buf, sqp->header_dma);
1418
1419 return err;
1420 }
1421
1422 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1423 {
1424 int c;
1425
1426 spin_lock_irq(&dev->qp_table.lock);
1427 c = qp->refcount;
1428 spin_unlock_irq(&dev->qp_table.lock);
1429
1430 return c;
1431 }
1432
1433 void mthca_free_qp(struct mthca_dev *dev,
1434 struct mthca_qp *qp)
1435 {
1436 struct mthca_cq *send_cq;
1437 struct mthca_cq *recv_cq;
1438
1439 send_cq = to_mcq(qp->ibqp.send_cq);
1440 recv_cq = to_mcq(qp->ibqp.recv_cq);
1441
1442 /*
1443 * Lock CQs here, so that CQ polling code can do QP lookup
1444 * without taking a lock.
1445 */
1446 mthca_lock_cqs(send_cq, recv_cq);
1447
1448 spin_lock(&dev->qp_table.lock);
1449 mthca_array_clear(&dev->qp_table.qp,
1450 qp->qpn & (dev->limits.num_qps - 1));
1451 --qp->refcount;
1452 spin_unlock(&dev->qp_table.lock);
1453
1454 mthca_unlock_cqs(send_cq, recv_cq);
1455
1456 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1457
1458 if (qp->state != IB_QPS_RESET)
1459 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1460 NULL, 0);
1461
1462 /*
1463 * If this is a userspace QP, the buffers, MR, CQs and so on
1464 * will be cleaned up in userspace, so all we have to do is
1465 * unref the mem-free tables and free the QPN in our table.
1466 */
1467 if (!qp->ibqp.uobject) {
1468 mthca_cq_clean(dev, recv_cq, qp->qpn,
1469 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1470 if (send_cq != recv_cq)
1471 mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1472
1473 mthca_free_memfree(dev, qp);
1474 mthca_free_wqe_buf(dev, qp);
1475 }
1476
1477 mthca_unmap_memfree(dev, qp);
1478
1479 if (is_sqp(dev, qp)) {
1480 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1481 dma_free_coherent(&dev->pdev->dev,
1482 to_msqp(qp)->header_buf_size,
1483 to_msqp(qp)->header_buf,
1484 to_msqp(qp)->header_dma);
1485 } else
1486 mthca_free(&dev->qp_table.alloc, qp->qpn);
1487 }
1488
1489 /* Create UD header for an MLX send and build a data segment for it */
1490 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1491 int ind, struct ib_ud_wr *wr,
1492 struct mthca_mlx_seg *mlx,
1493 struct mthca_data_seg *data)
1494 {
1495 int header_size;
1496 int err;
1497 u16 pkey;
1498
1499 ib_ud_header_init(256, /* assume a MAD */ 1, 0, 0,
1500 mthca_ah_grh_present(to_mah(wr->ah)), 0, 0, 0,
1501 &sqp->ud_header);
1502
1503 err = mthca_read_ah(dev, to_mah(wr->ah), &sqp->ud_header);
1504 if (err)
1505 return err;
1506 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1507 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1508 (sqp->ud_header.lrh.destination_lid ==
1509 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1510 (sqp->ud_header.lrh.service_level << 8));
1511 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1512 mlx->vcrc = 0;
1513
1514 switch (wr->wr.opcode) {
1515 case IB_WR_SEND:
1516 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1517 sqp->ud_header.immediate_present = 0;
1518 break;
1519 case IB_WR_SEND_WITH_IMM:
1520 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1521 sqp->ud_header.immediate_present = 1;
1522 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
1523 break;
1524 default:
1525 return -EINVAL;
1526 }
1527
1528 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1529 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1530 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1531 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1532 if (!sqp->qp.ibqp.qp_num)
1533 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1534 sqp->pkey_index, &pkey);
1535 else
1536 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1537 wr->pkey_index, &pkey);
1538 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1539 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1540 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1541 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
1542 sqp->qkey : wr->remote_qkey);
1543 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1544
1545 header_size = ib_ud_header_pack(&sqp->ud_header,
1546 sqp->header_buf +
1547 ind * MTHCA_UD_HEADER_SIZE);
1548
1549 data->byte_count = cpu_to_be32(header_size);
1550 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1551 data->addr = cpu_to_be64(sqp->header_dma +
1552 ind * MTHCA_UD_HEADER_SIZE);
1553
1554 return 0;
1555 }
1556
1557 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1558 struct ib_cq *ib_cq)
1559 {
1560 unsigned cur;
1561 struct mthca_cq *cq;
1562
1563 cur = wq->head - wq->tail;
1564 if (likely(cur + nreq < wq->max))
1565 return 0;
1566
1567 cq = to_mcq(ib_cq);
1568 spin_lock(&cq->lock);
1569 cur = wq->head - wq->tail;
1570 spin_unlock(&cq->lock);
1571
1572 return cur + nreq >= wq->max;
1573 }
1574
1575 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg,
1576 u64 remote_addr, u32 rkey)
1577 {
1578 rseg->raddr = cpu_to_be64(remote_addr);
1579 rseg->rkey = cpu_to_be32(rkey);
1580 rseg->reserved = 0;
1581 }
1582
1583 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg,
1584 struct ib_atomic_wr *wr)
1585 {
1586 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1587 aseg->swap_add = cpu_to_be64(wr->swap);
1588 aseg->compare = cpu_to_be64(wr->compare_add);
1589 } else {
1590 aseg->swap_add = cpu_to_be64(wr->compare_add);
1591 aseg->compare = 0;
1592 }
1593
1594 }
1595
1596 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg,
1597 struct ib_ud_wr *wr)
1598 {
1599 useg->lkey = cpu_to_be32(to_mah(wr->ah)->key);
1600 useg->av_addr = cpu_to_be64(to_mah(wr->ah)->avdma);
1601 useg->dqpn = cpu_to_be32(wr->remote_qpn);
1602 useg->qkey = cpu_to_be32(wr->remote_qkey);
1603
1604 }
1605
1606 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg,
1607 struct ib_ud_wr *wr)
1608 {
1609 memcpy(useg->av, to_mah(wr->ah)->av, MTHCA_AV_SIZE);
1610 useg->dqpn = cpu_to_be32(wr->remote_qpn);
1611 useg->qkey = cpu_to_be32(wr->remote_qkey);
1612 }
1613
1614 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1615 struct ib_send_wr **bad_wr)
1616 {
1617 struct mthca_dev *dev = to_mdev(ibqp->device);
1618 struct mthca_qp *qp = to_mqp(ibqp);
1619 void *wqe;
1620 void *prev_wqe;
1621 unsigned long flags;
1622 int err = 0;
1623 int nreq;
1624 int i;
1625 int size;
1626 /*
1627 * f0 and size0 are only used if nreq != 0, and they will
1628 * always be initialized the first time through the main loop
1629 * before nreq is incremented. So nreq cannot become non-zero
1630 * without initializing f0 and size0, and they are in fact
1631 * never used uninitialized.
1632 */
1633 int uninitialized_var(size0);
1634 u32 uninitialized_var(f0);
1635 int ind;
1636 u8 op0 = 0;
1637
1638 spin_lock_irqsave(&qp->sq.lock, flags);
1639
1640 /* XXX check that state is OK to post send */
1641
1642 ind = qp->sq.next_ind;
1643
1644 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1645 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1646 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1647 " %d max, %d nreq)\n", qp->qpn,
1648 qp->sq.head, qp->sq.tail,
1649 qp->sq.max, nreq);
1650 err = -ENOMEM;
1651 *bad_wr = wr;
1652 goto out;
1653 }
1654
1655 wqe = get_send_wqe(qp, ind);
1656 prev_wqe = qp->sq.last;
1657 qp->sq.last = wqe;
1658
1659 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1660 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1661 ((struct mthca_next_seg *) wqe)->flags =
1662 ((wr->send_flags & IB_SEND_SIGNALED) ?
1663 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1664 ((wr->send_flags & IB_SEND_SOLICITED) ?
1665 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1666 cpu_to_be32(1);
1667 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1668 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1669 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
1670
1671 wqe += sizeof (struct mthca_next_seg);
1672 size = sizeof (struct mthca_next_seg) / 16;
1673
1674 switch (qp->transport) {
1675 case RC:
1676 switch (wr->opcode) {
1677 case IB_WR_ATOMIC_CMP_AND_SWP:
1678 case IB_WR_ATOMIC_FETCH_AND_ADD:
1679 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
1680 atomic_wr(wr)->rkey);
1681 wqe += sizeof (struct mthca_raddr_seg);
1682
1683 set_atomic_seg(wqe, atomic_wr(wr));
1684 wqe += sizeof (struct mthca_atomic_seg);
1685 size += (sizeof (struct mthca_raddr_seg) +
1686 sizeof (struct mthca_atomic_seg)) / 16;
1687 break;
1688
1689 case IB_WR_RDMA_WRITE:
1690 case IB_WR_RDMA_WRITE_WITH_IMM:
1691 case IB_WR_RDMA_READ:
1692 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1693 rdma_wr(wr)->rkey);
1694 wqe += sizeof (struct mthca_raddr_seg);
1695 size += sizeof (struct mthca_raddr_seg) / 16;
1696 break;
1697
1698 default:
1699 /* No extra segments required for sends */
1700 break;
1701 }
1702
1703 break;
1704
1705 case UC:
1706 switch (wr->opcode) {
1707 case IB_WR_RDMA_WRITE:
1708 case IB_WR_RDMA_WRITE_WITH_IMM:
1709 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1710 rdma_wr(wr)->rkey);
1711 wqe += sizeof (struct mthca_raddr_seg);
1712 size += sizeof (struct mthca_raddr_seg) / 16;
1713 break;
1714
1715 default:
1716 /* No extra segments required for sends */
1717 break;
1718 }
1719
1720 break;
1721
1722 case UD:
1723 set_tavor_ud_seg(wqe, ud_wr(wr));
1724 wqe += sizeof (struct mthca_tavor_ud_seg);
1725 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1726 break;
1727
1728 case MLX:
1729 err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
1730 wqe - sizeof (struct mthca_next_seg),
1731 wqe);
1732 if (err) {
1733 *bad_wr = wr;
1734 goto out;
1735 }
1736 wqe += sizeof (struct mthca_data_seg);
1737 size += sizeof (struct mthca_data_seg) / 16;
1738 break;
1739 }
1740
1741 if (wr->num_sge > qp->sq.max_gs) {
1742 mthca_err(dev, "too many gathers\n");
1743 err = -EINVAL;
1744 *bad_wr = wr;
1745 goto out;
1746 }
1747
1748 for (i = 0; i < wr->num_sge; ++i) {
1749 mthca_set_data_seg(wqe, wr->sg_list + i);
1750 wqe += sizeof (struct mthca_data_seg);
1751 size += sizeof (struct mthca_data_seg) / 16;
1752 }
1753
1754 /* Add one more inline data segment for ICRC */
1755 if (qp->transport == MLX) {
1756 ((struct mthca_data_seg *) wqe)->byte_count =
1757 cpu_to_be32((1 << 31) | 4);
1758 ((u32 *) wqe)[1] = 0;
1759 wqe += sizeof (struct mthca_data_seg);
1760 size += sizeof (struct mthca_data_seg) / 16;
1761 }
1762
1763 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1764
1765 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1766 mthca_err(dev, "opcode invalid\n");
1767 err = -EINVAL;
1768 *bad_wr = wr;
1769 goto out;
1770 }
1771
1772 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1773 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1774 qp->send_wqe_offset) |
1775 mthca_opcode[wr->opcode]);
1776 wmb();
1777 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1778 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size |
1779 ((wr->send_flags & IB_SEND_FENCE) ?
1780 MTHCA_NEXT_FENCE : 0));
1781
1782 if (!nreq) {
1783 size0 = size;
1784 op0 = mthca_opcode[wr->opcode];
1785 f0 = wr->send_flags & IB_SEND_FENCE ?
1786 MTHCA_SEND_DOORBELL_FENCE : 0;
1787 }
1788
1789 ++ind;
1790 if (unlikely(ind >= qp->sq.max))
1791 ind -= qp->sq.max;
1792 }
1793
1794 out:
1795 if (likely(nreq)) {
1796 wmb();
1797
1798 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) +
1799 qp->send_wqe_offset) | f0 | op0,
1800 (qp->qpn << 8) | size0,
1801 dev->kar + MTHCA_SEND_DOORBELL,
1802 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1803 /*
1804 * Make sure doorbells don't leak out of SQ spinlock
1805 * and reach the HCA out of order:
1806 */
1807 mmiowb();
1808 }
1809
1810 qp->sq.next_ind = ind;
1811 qp->sq.head += nreq;
1812
1813 spin_unlock_irqrestore(&qp->sq.lock, flags);
1814 return err;
1815 }
1816
1817 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1818 struct ib_recv_wr **bad_wr)
1819 {
1820 struct mthca_dev *dev = to_mdev(ibqp->device);
1821 struct mthca_qp *qp = to_mqp(ibqp);
1822 unsigned long flags;
1823 int err = 0;
1824 int nreq;
1825 int i;
1826 int size;
1827 /*
1828 * size0 is only used if nreq != 0, and it will always be
1829 * initialized the first time through the main loop before
1830 * nreq is incremented. So nreq cannot become non-zero
1831 * without initializing size0, and it is in fact never used
1832 * uninitialized.
1833 */
1834 int uninitialized_var(size0);
1835 int ind;
1836 void *wqe;
1837 void *prev_wqe;
1838
1839 spin_lock_irqsave(&qp->rq.lock, flags);
1840
1841 /* XXX check that state is OK to post receive */
1842
1843 ind = qp->rq.next_ind;
1844
1845 for (nreq = 0; wr; wr = wr->next) {
1846 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1847 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1848 " %d max, %d nreq)\n", qp->qpn,
1849 qp->rq.head, qp->rq.tail,
1850 qp->rq.max, nreq);
1851 err = -ENOMEM;
1852 *bad_wr = wr;
1853 goto out;
1854 }
1855
1856 wqe = get_recv_wqe(qp, ind);
1857 prev_wqe = qp->rq.last;
1858 qp->rq.last = wqe;
1859
1860 ((struct mthca_next_seg *) wqe)->ee_nds =
1861 cpu_to_be32(MTHCA_NEXT_DBD);
1862 ((struct mthca_next_seg *) wqe)->flags = 0;
1863
1864 wqe += sizeof (struct mthca_next_seg);
1865 size = sizeof (struct mthca_next_seg) / 16;
1866
1867 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1868 err = -EINVAL;
1869 *bad_wr = wr;
1870 goto out;
1871 }
1872
1873 for (i = 0; i < wr->num_sge; ++i) {
1874 mthca_set_data_seg(wqe, wr->sg_list + i);
1875 wqe += sizeof (struct mthca_data_seg);
1876 size += sizeof (struct mthca_data_seg) / 16;
1877 }
1878
1879 qp->wrid[ind] = wr->wr_id;
1880
1881 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1882 cpu_to_be32(MTHCA_NEXT_DBD | size);
1883
1884 if (!nreq)
1885 size0 = size;
1886
1887 ++ind;
1888 if (unlikely(ind >= qp->rq.max))
1889 ind -= qp->rq.max;
1890
1891 ++nreq;
1892 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1893 nreq = 0;
1894
1895 wmb();
1896
1897 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1898 qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL,
1899 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1900
1901 qp->rq.next_ind = ind;
1902 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1903 }
1904 }
1905
1906 out:
1907 if (likely(nreq)) {
1908 wmb();
1909
1910 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1911 qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL,
1912 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1913 }
1914
1915 qp->rq.next_ind = ind;
1916 qp->rq.head += nreq;
1917
1918 /*
1919 * Make sure doorbells don't leak out of RQ spinlock and reach
1920 * the HCA out of order:
1921 */
1922 mmiowb();
1923
1924 spin_unlock_irqrestore(&qp->rq.lock, flags);
1925 return err;
1926 }
1927
1928 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1929 struct ib_send_wr **bad_wr)
1930 {
1931 struct mthca_dev *dev = to_mdev(ibqp->device);
1932 struct mthca_qp *qp = to_mqp(ibqp);
1933 u32 dbhi;
1934 void *wqe;
1935 void *prev_wqe;
1936 unsigned long flags;
1937 int err = 0;
1938 int nreq;
1939 int i;
1940 int size;
1941 /*
1942 * f0 and size0 are only used if nreq != 0, and they will
1943 * always be initialized the first time through the main loop
1944 * before nreq is incremented. So nreq cannot become non-zero
1945 * without initializing f0 and size0, and they are in fact
1946 * never used uninitialized.
1947 */
1948 int uninitialized_var(size0);
1949 u32 uninitialized_var(f0);
1950 int ind;
1951 u8 op0 = 0;
1952
1953 spin_lock_irqsave(&qp->sq.lock, flags);
1954
1955 /* XXX check that state is OK to post send */
1956
1957 ind = qp->sq.head & (qp->sq.max - 1);
1958
1959 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1960 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1961 nreq = 0;
1962
1963 dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1964 ((qp->sq.head & 0xffff) << 8) | f0 | op0;
1965
1966 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1967
1968 /*
1969 * Make sure that descriptors are written before
1970 * doorbell record.
1971 */
1972 wmb();
1973 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1974
1975 /*
1976 * Make sure doorbell record is written before we
1977 * write MMIO send doorbell.
1978 */
1979 wmb();
1980
1981 mthca_write64(dbhi, (qp->qpn << 8) | size0,
1982 dev->kar + MTHCA_SEND_DOORBELL,
1983 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1984 }
1985
1986 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1987 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1988 " %d max, %d nreq)\n", qp->qpn,
1989 qp->sq.head, qp->sq.tail,
1990 qp->sq.max, nreq);
1991 err = -ENOMEM;
1992 *bad_wr = wr;
1993 goto out;
1994 }
1995
1996 wqe = get_send_wqe(qp, ind);
1997 prev_wqe = qp->sq.last;
1998 qp->sq.last = wqe;
1999
2000 ((struct mthca_next_seg *) wqe)->flags =
2001 ((wr->send_flags & IB_SEND_SIGNALED) ?
2002 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
2003 ((wr->send_flags & IB_SEND_SOLICITED) ?
2004 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
2005 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2006 cpu_to_be32(MTHCA_NEXT_IP_CSUM | MTHCA_NEXT_TCP_UDP_CSUM) : 0) |
2007 cpu_to_be32(1);
2008 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2009 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2010 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
2011
2012 wqe += sizeof (struct mthca_next_seg);
2013 size = sizeof (struct mthca_next_seg) / 16;
2014
2015 switch (qp->transport) {
2016 case RC:
2017 switch (wr->opcode) {
2018 case IB_WR_ATOMIC_CMP_AND_SWP:
2019 case IB_WR_ATOMIC_FETCH_AND_ADD:
2020 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2021 atomic_wr(wr)->rkey);
2022 wqe += sizeof (struct mthca_raddr_seg);
2023
2024 set_atomic_seg(wqe, atomic_wr(wr));
2025 wqe += sizeof (struct mthca_atomic_seg);
2026 size += (sizeof (struct mthca_raddr_seg) +
2027 sizeof (struct mthca_atomic_seg)) / 16;
2028 break;
2029
2030 case IB_WR_RDMA_READ:
2031 case IB_WR_RDMA_WRITE:
2032 case IB_WR_RDMA_WRITE_WITH_IMM:
2033 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2034 rdma_wr(wr)->rkey);
2035 wqe += sizeof (struct mthca_raddr_seg);
2036 size += sizeof (struct mthca_raddr_seg) / 16;
2037 break;
2038
2039 default:
2040 /* No extra segments required for sends */
2041 break;
2042 }
2043
2044 break;
2045
2046 case UC:
2047 switch (wr->opcode) {
2048 case IB_WR_RDMA_WRITE:
2049 case IB_WR_RDMA_WRITE_WITH_IMM:
2050 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2051 rdma_wr(wr)->rkey);
2052 wqe += sizeof (struct mthca_raddr_seg);
2053 size += sizeof (struct mthca_raddr_seg) / 16;
2054 break;
2055
2056 default:
2057 /* No extra segments required for sends */
2058 break;
2059 }
2060
2061 break;
2062
2063 case UD:
2064 set_arbel_ud_seg(wqe, ud_wr(wr));
2065 wqe += sizeof (struct mthca_arbel_ud_seg);
2066 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2067 break;
2068
2069 case MLX:
2070 err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
2071 wqe - sizeof (struct mthca_next_seg),
2072 wqe);
2073 if (err) {
2074 *bad_wr = wr;
2075 goto out;
2076 }
2077 wqe += sizeof (struct mthca_data_seg);
2078 size += sizeof (struct mthca_data_seg) / 16;
2079 break;
2080 }
2081
2082 if (wr->num_sge > qp->sq.max_gs) {
2083 mthca_err(dev, "too many gathers\n");
2084 err = -EINVAL;
2085 *bad_wr = wr;
2086 goto out;
2087 }
2088
2089 for (i = 0; i < wr->num_sge; ++i) {
2090 mthca_set_data_seg(wqe, wr->sg_list + i);
2091 wqe += sizeof (struct mthca_data_seg);
2092 size += sizeof (struct mthca_data_seg) / 16;
2093 }
2094
2095 /* Add one more inline data segment for ICRC */
2096 if (qp->transport == MLX) {
2097 ((struct mthca_data_seg *) wqe)->byte_count =
2098 cpu_to_be32((1 << 31) | 4);
2099 ((u32 *) wqe)[1] = 0;
2100 wqe += sizeof (struct mthca_data_seg);
2101 size += sizeof (struct mthca_data_seg) / 16;
2102 }
2103
2104 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2105
2106 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2107 mthca_err(dev, "opcode invalid\n");
2108 err = -EINVAL;
2109 *bad_wr = wr;
2110 goto out;
2111 }
2112
2113 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2114 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2115 qp->send_wqe_offset) |
2116 mthca_opcode[wr->opcode]);
2117 wmb();
2118 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2119 cpu_to_be32(MTHCA_NEXT_DBD | size |
2120 ((wr->send_flags & IB_SEND_FENCE) ?
2121 MTHCA_NEXT_FENCE : 0));
2122
2123 if (!nreq) {
2124 size0 = size;
2125 op0 = mthca_opcode[wr->opcode];
2126 f0 = wr->send_flags & IB_SEND_FENCE ?
2127 MTHCA_SEND_DOORBELL_FENCE : 0;
2128 }
2129
2130 ++ind;
2131 if (unlikely(ind >= qp->sq.max))
2132 ind -= qp->sq.max;
2133 }
2134
2135 out:
2136 if (likely(nreq)) {
2137 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
2138
2139 qp->sq.head += nreq;
2140
2141 /*
2142 * Make sure that descriptors are written before
2143 * doorbell record.
2144 */
2145 wmb();
2146 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2147
2148 /*
2149 * Make sure doorbell record is written before we
2150 * write MMIO send doorbell.
2151 */
2152 wmb();
2153
2154 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL,
2155 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2156 }
2157
2158 /*
2159 * Make sure doorbells don't leak out of SQ spinlock and reach
2160 * the HCA out of order:
2161 */
2162 mmiowb();
2163
2164 spin_unlock_irqrestore(&qp->sq.lock, flags);
2165 return err;
2166 }
2167
2168 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2169 struct ib_recv_wr **bad_wr)
2170 {
2171 struct mthca_dev *dev = to_mdev(ibqp->device);
2172 struct mthca_qp *qp = to_mqp(ibqp);
2173 unsigned long flags;
2174 int err = 0;
2175 int nreq;
2176 int ind;
2177 int i;
2178 void *wqe;
2179
2180 spin_lock_irqsave(&qp->rq.lock, flags);
2181
2182 /* XXX check that state is OK to post receive */
2183
2184 ind = qp->rq.head & (qp->rq.max - 1);
2185
2186 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2187 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2188 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2189 " %d max, %d nreq)\n", qp->qpn,
2190 qp->rq.head, qp->rq.tail,
2191 qp->rq.max, nreq);
2192 err = -ENOMEM;
2193 *bad_wr = wr;
2194 goto out;
2195 }
2196
2197 wqe = get_recv_wqe(qp, ind);
2198
2199 ((struct mthca_next_seg *) wqe)->flags = 0;
2200
2201 wqe += sizeof (struct mthca_next_seg);
2202
2203 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2204 err = -EINVAL;
2205 *bad_wr = wr;
2206 goto out;
2207 }
2208
2209 for (i = 0; i < wr->num_sge; ++i) {
2210 mthca_set_data_seg(wqe, wr->sg_list + i);
2211 wqe += sizeof (struct mthca_data_seg);
2212 }
2213
2214 if (i < qp->rq.max_gs)
2215 mthca_set_data_seg_inval(wqe);
2216
2217 qp->wrid[ind] = wr->wr_id;
2218
2219 ++ind;
2220 if (unlikely(ind >= qp->rq.max))
2221 ind -= qp->rq.max;
2222 }
2223 out:
2224 if (likely(nreq)) {
2225 qp->rq.head += nreq;
2226
2227 /*
2228 * Make sure that descriptors are written before
2229 * doorbell record.
2230 */
2231 wmb();
2232 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2233 }
2234
2235 spin_unlock_irqrestore(&qp->rq.lock, flags);
2236 return err;
2237 }
2238
2239 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2240 int index, int *dbd, __be32 *new_wqe)
2241 {
2242 struct mthca_next_seg *next;
2243
2244 /*
2245 * For SRQs, all receive WQEs generate a CQE, so we're always
2246 * at the end of the doorbell chain.
2247 */
2248 if (qp->ibqp.srq && !is_send) {
2249 *new_wqe = 0;
2250 return;
2251 }
2252
2253 if (is_send)
2254 next = get_send_wqe(qp, index);
2255 else
2256 next = get_recv_wqe(qp, index);
2257
2258 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2259 if (next->ee_nds & cpu_to_be32(0x3f))
2260 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2261 (next->ee_nds & cpu_to_be32(0x3f));
2262 else
2263 *new_wqe = 0;
2264 }
2265
2266 int mthca_init_qp_table(struct mthca_dev *dev)
2267 {
2268 int err;
2269 int i;
2270
2271 spin_lock_init(&dev->qp_table.lock);
2272
2273 /*
2274 * We reserve 2 extra QPs per port for the special QPs. The
2275 * special QP for port 1 has to be even, so round up.
2276 */
2277 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2278 err = mthca_alloc_init(&dev->qp_table.alloc,
2279 dev->limits.num_qps,
2280 (1 << 24) - 1,
2281 dev->qp_table.sqp_start +
2282 MTHCA_MAX_PORTS * 2);
2283 if (err)
2284 return err;
2285
2286 err = mthca_array_init(&dev->qp_table.qp,
2287 dev->limits.num_qps);
2288 if (err) {
2289 mthca_alloc_cleanup(&dev->qp_table.alloc);
2290 return err;
2291 }
2292
2293 for (i = 0; i < 2; ++i) {
2294 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2295 dev->qp_table.sqp_start + i * 2);
2296 if (err) {
2297 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2298 "%d, aborting.\n", err);
2299 goto err_out;
2300 }
2301 }
2302 return 0;
2303
2304 err_out:
2305 for (i = 0; i < 2; ++i)
2306 mthca_CONF_SPECIAL_QP(dev, i, 0);
2307
2308 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2309 mthca_alloc_cleanup(&dev->qp_table.alloc);
2310
2311 return err;
2312 }
2313
2314 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2315 {
2316 int i;
2317
2318 for (i = 0; i < 2; ++i)
2319 mthca_CONF_SPECIAL_QP(dev, i, 0);
2320
2321 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2322 mthca_alloc_cleanup(&dev->qp_table.alloc);
2323 }
CRIS linux kernel tree