Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / media / cec / cec-pin-priv.h
blob7d0def19976247afb991fd7ad7e573f250e81a93
1 /*
2 * cec-pin-priv.h - internal cec-pin header
4 * Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
20 #ifndef LINUX_CEC_PIN_PRIV_H
21 #define LINUX_CEC_PIN_PRIV_H
23 #include <linux/types.h>
24 #include <linux/atomic.h>
25 #include <media/cec-pin.h>
27 enum cec_pin_state {
28 /* CEC is off */
29 CEC_ST_OFF,
30 /* CEC is idle, waiting for Rx or Tx */
31 CEC_ST_IDLE,
33 /* Tx states */
35 /* Pending Tx, waiting for Signal Free Time to expire */
36 CEC_ST_TX_WAIT,
37 /* Low-drive was detected, wait for bus to go high */
38 CEC_ST_TX_WAIT_FOR_HIGH,
39 /* Drive CEC low for the start bit */
40 CEC_ST_TX_START_BIT_LOW,
41 /* Drive CEC high for the start bit */
42 CEC_ST_TX_START_BIT_HIGH,
43 /* Drive CEC low for the 0 bit */
44 CEC_ST_TX_DATA_BIT_0_LOW,
45 /* Drive CEC high for the 0 bit */
46 CEC_ST_TX_DATA_BIT_0_HIGH,
47 /* Drive CEC low for the 1 bit */
48 CEC_ST_TX_DATA_BIT_1_LOW,
49 /* Drive CEC high for the 1 bit */
50 CEC_ST_TX_DATA_BIT_1_HIGH,
52 * Wait for start of sample time to check for Ack bit or first
53 * four initiator bits to check for Arbitration Lost.
55 CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE,
56 /* Wait for end of bit period after sampling */
57 CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE,
59 /* Rx states */
61 /* Start bit low detected */
62 CEC_ST_RX_START_BIT_LOW,
63 /* Start bit high detected */
64 CEC_ST_RX_START_BIT_HIGH,
65 /* Wait for bit sample time */
66 CEC_ST_RX_DATA_SAMPLE,
67 /* Wait for earliest end of bit period after sampling */
68 CEC_ST_RX_DATA_POST_SAMPLE,
69 /* Wait for CEC to go high (i.e. end of bit period */
70 CEC_ST_RX_DATA_HIGH,
71 /* Drive CEC low to send 0 Ack bit */
72 CEC_ST_RX_ACK_LOW,
73 /* End of 0 Ack time, wait for earliest end of bit period */
74 CEC_ST_RX_ACK_LOW_POST,
75 /* Wait for CEC to go high (i.e. end of bit period */
76 CEC_ST_RX_ACK_HIGH_POST,
77 /* Wait for earliest end of bit period and end of message */
78 CEC_ST_RX_ACK_FINISH,
80 /* Start low drive */
81 CEC_ST_LOW_DRIVE,
82 /* Monitor pin using interrupts */
83 CEC_ST_RX_IRQ,
85 /* Total number of pin states */
86 CEC_PIN_STATES
89 #define CEC_NUM_PIN_EVENTS 128
91 #define CEC_PIN_IRQ_UNCHANGED 0
92 #define CEC_PIN_IRQ_DISABLE 1
93 #define CEC_PIN_IRQ_ENABLE 2
95 struct cec_pin {
96 struct cec_adapter *adap;
97 const struct cec_pin_ops *ops;
98 struct task_struct *kthread;
99 wait_queue_head_t kthread_waitq;
100 struct hrtimer timer;
101 ktime_t ts;
102 unsigned int wait_usecs;
103 u16 la_mask;
104 bool enabled;
105 bool monitor_all;
106 bool rx_eom;
107 bool enable_irq_failed;
108 enum cec_pin_state state;
109 struct cec_msg tx_msg;
110 u32 tx_bit;
111 bool tx_nacked;
112 u32 tx_signal_free_time;
113 struct cec_msg rx_msg;
114 u32 rx_bit;
116 struct cec_msg work_rx_msg;
117 u8 work_tx_status;
118 ktime_t work_tx_ts;
119 atomic_t work_irq_change;
120 atomic_t work_pin_events;
121 unsigned int work_pin_events_wr;
122 unsigned int work_pin_events_rd;
123 ktime_t work_pin_ts[CEC_NUM_PIN_EVENTS];
124 bool work_pin_is_high[CEC_NUM_PIN_EVENTS];
125 ktime_t timer_ts;
126 u32 timer_cnt;
127 u32 timer_100ms_overruns;
128 u32 timer_300ms_overruns;
129 u32 timer_max_overrun;
130 u32 timer_sum_overrun;
133 #endif