2 Driver for M88RS2000 demodulator and tuner
4 Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
7 Include various calculation code from DS3000 driver.
8 Copyright (C) 2009 Konstantin Dimitrov.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/jiffies.h>
29 #include <linux/string.h>
30 #include <linux/slab.h>
31 #include <linux/types.h>
34 #include <media/dvb_frontend.h>
35 #include "m88rs2000.h"
37 struct m88rs2000_state
{
38 struct i2c_adapter
*i2c
;
39 const struct m88rs2000_config
*config
;
40 struct dvb_frontend frontend
;
44 enum fe_code_rate fec_inner
;
49 static int m88rs2000_debug
;
51 module_param_named(debug
, m88rs2000_debug
, int, 0644);
52 MODULE_PARM_DESC(debug
, "set debugging level (1=info (or-able)).");
54 #define dprintk(level, args...) do { \
55 if (level & m88rs2000_debug) \
56 printk(KERN_DEBUG "m88rs2000-fe: " args); \
59 #define deb_info(args...) dprintk(0x01, args)
60 #define info(format, arg...) \
61 printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
63 static int m88rs2000_writereg(struct m88rs2000_state
*state
,
67 u8 buf
[] = { reg
, data
};
68 struct i2c_msg msg
= {
69 .addr
= state
->config
->demod_addr
,
75 ret
= i2c_transfer(state
->i2c
, &msg
, 1);
78 deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
79 __func__
, reg
, data
, ret
);
81 return (ret
!= 1) ? -EREMOTEIO
: 0;
84 static u8
m88rs2000_readreg(struct m88rs2000_state
*state
, u8 reg
)
90 struct i2c_msg msg
[] = {
92 .addr
= state
->config
->demod_addr
,
97 .addr
= state
->config
->demod_addr
,
104 ret
= i2c_transfer(state
->i2c
, msg
, 2);
107 deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
113 static u32
m88rs2000_get_mclk(struct dvb_frontend
*fe
)
115 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
118 /* Must not be 0x00 or 0xff */
119 reg
= m88rs2000_readreg(state
, 0x86);
120 if (!reg
|| reg
== 0xff)
126 mclk
= (u32
)(reg
* RS2000_FE_CRYSTAL_KHZ
+ 28 / 2) / 28;
131 static int m88rs2000_set_carrieroffset(struct dvb_frontend
*fe
, s16 offset
)
133 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
139 mclk
= m88rs2000_get_mclk(fe
);
143 tmp
= (offset
* 4096 + (s32
)mclk
/ 2) / (s32
)mclk
;
148 ret
= m88rs2000_writereg(state
, 0x9c, (u8
)(tmp
>> 4));
150 reg
= m88rs2000_readreg(state
, 0x9d);
152 reg
|= (u8
)(tmp
& 0xf) << 4;
154 ret
|= m88rs2000_writereg(state
, 0x9d, reg
);
159 static int m88rs2000_set_symbolrate(struct dvb_frontend
*fe
, u32 srate
)
161 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
167 if ((srate
< 1000000) || (srate
> 45000000))
170 mclk
= m88rs2000_get_mclk(fe
);
179 b
[0] = (u8
) (temp
>> 16) & 0xff;
180 b
[1] = (u8
) (temp
>> 8) & 0xff;
181 b
[2] = (u8
) temp
& 0xff;
183 ret
= m88rs2000_writereg(state
, 0x93, b
[2]);
184 ret
|= m88rs2000_writereg(state
, 0x94, b
[1]);
185 ret
|= m88rs2000_writereg(state
, 0x95, b
[0]);
187 if (srate
> 10000000)
188 ret
|= m88rs2000_writereg(state
, 0xa0, 0x20);
190 ret
|= m88rs2000_writereg(state
, 0xa0, 0x60);
192 ret
|= m88rs2000_writereg(state
, 0xa1, 0xe0);
194 if (srate
> 12000000)
195 ret
|= m88rs2000_writereg(state
, 0xa3, 0x20);
196 else if (srate
> 2800000)
197 ret
|= m88rs2000_writereg(state
, 0xa3, 0x98);
199 ret
|= m88rs2000_writereg(state
, 0xa3, 0x90);
201 deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
205 static int m88rs2000_send_diseqc_msg(struct dvb_frontend
*fe
,
206 struct dvb_diseqc_master_cmd
*m
)
208 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
212 deb_info("%s\n", __func__
);
213 m88rs2000_writereg(state
, 0x9a, 0x30);
214 reg
= m88rs2000_readreg(state
, 0xb2);
216 m88rs2000_writereg(state
, 0xb2, reg
);
217 for (i
= 0; i
< m
->msg_len
; i
++)
218 m88rs2000_writereg(state
, 0xb3 + i
, m
->msg
[i
]);
220 reg
= m88rs2000_readreg(state
, 0xb1);
222 reg
|= ((m
->msg_len
- 1) << 3) | 0x07;
224 m88rs2000_writereg(state
, 0xb1, reg
);
226 for (i
= 0; i
< 15; i
++) {
227 if ((m88rs2000_readreg(state
, 0xb1) & 0x40) == 0x0)
232 reg
= m88rs2000_readreg(state
, 0xb1);
233 if ((reg
& 0x40) > 0x0) {
236 m88rs2000_writereg(state
, 0xb1, reg
);
239 reg
= m88rs2000_readreg(state
, 0xb2);
242 m88rs2000_writereg(state
, 0xb2, reg
);
243 m88rs2000_writereg(state
, 0x9a, 0xb0);
249 static int m88rs2000_send_diseqc_burst(struct dvb_frontend
*fe
,
250 enum fe_sec_mini_cmd burst
)
252 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
254 deb_info("%s\n", __func__
);
255 m88rs2000_writereg(state
, 0x9a, 0x30);
257 reg0
= m88rs2000_readreg(state
, 0xb1);
258 reg1
= m88rs2000_readreg(state
, 0xb2);
259 /* TODO complete this section */
260 m88rs2000_writereg(state
, 0xb2, reg1
);
261 m88rs2000_writereg(state
, 0xb1, reg0
);
262 m88rs2000_writereg(state
, 0x9a, 0xb0);
267 static int m88rs2000_set_tone(struct dvb_frontend
*fe
,
268 enum fe_sec_tone_mode tone
)
270 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
272 m88rs2000_writereg(state
, 0x9a, 0x30);
273 reg0
= m88rs2000_readreg(state
, 0xb1);
274 reg1
= m88rs2000_readreg(state
, 0xb2);
289 m88rs2000_writereg(state
, 0xb2, reg1
);
290 m88rs2000_writereg(state
, 0xb1, reg0
);
291 m88rs2000_writereg(state
, 0x9a, 0xb0);
301 static struct inittab m88rs2000_setup
[] = {
302 {DEMOD_WRITE
, 0x9a, 0x30},
303 {DEMOD_WRITE
, 0x00, 0x01},
304 {WRITE_DELAY
, 0x19, 0x00},
305 {DEMOD_WRITE
, 0x00, 0x00},
306 {DEMOD_WRITE
, 0x9a, 0xb0},
307 {DEMOD_WRITE
, 0x81, 0xc1},
308 {DEMOD_WRITE
, 0x81, 0x81},
309 {DEMOD_WRITE
, 0x86, 0xc6},
310 {DEMOD_WRITE
, 0x9a, 0x30},
311 {DEMOD_WRITE
, 0xf0, 0x22},
312 {DEMOD_WRITE
, 0xf1, 0xbf},
313 {DEMOD_WRITE
, 0xb0, 0x45},
314 {DEMOD_WRITE
, 0xb2, 0x01}, /* set voltage pin always set 1*/
315 {DEMOD_WRITE
, 0x9a, 0xb0},
319 static struct inittab m88rs2000_shutdown
[] = {
320 {DEMOD_WRITE
, 0x9a, 0x30},
321 {DEMOD_WRITE
, 0xb0, 0x00},
322 {DEMOD_WRITE
, 0xf1, 0x89},
323 {DEMOD_WRITE
, 0x00, 0x01},
324 {DEMOD_WRITE
, 0x9a, 0xb0},
325 {DEMOD_WRITE
, 0x81, 0x81},
329 static struct inittab fe_reset
[] = {
330 {DEMOD_WRITE
, 0x00, 0x01},
331 {DEMOD_WRITE
, 0x20, 0x81},
332 {DEMOD_WRITE
, 0x21, 0x80},
333 {DEMOD_WRITE
, 0x10, 0x33},
334 {DEMOD_WRITE
, 0x11, 0x44},
335 {DEMOD_WRITE
, 0x12, 0x07},
336 {DEMOD_WRITE
, 0x18, 0x20},
337 {DEMOD_WRITE
, 0x28, 0x04},
338 {DEMOD_WRITE
, 0x29, 0x8e},
339 {DEMOD_WRITE
, 0x3b, 0xff},
340 {DEMOD_WRITE
, 0x32, 0x10},
341 {DEMOD_WRITE
, 0x33, 0x02},
342 {DEMOD_WRITE
, 0x34, 0x30},
343 {DEMOD_WRITE
, 0x35, 0xff},
344 {DEMOD_WRITE
, 0x38, 0x50},
345 {DEMOD_WRITE
, 0x39, 0x68},
346 {DEMOD_WRITE
, 0x3c, 0x7f},
347 {DEMOD_WRITE
, 0x3d, 0x0f},
348 {DEMOD_WRITE
, 0x45, 0x20},
349 {DEMOD_WRITE
, 0x46, 0x24},
350 {DEMOD_WRITE
, 0x47, 0x7c},
351 {DEMOD_WRITE
, 0x48, 0x16},
352 {DEMOD_WRITE
, 0x49, 0x04},
353 {DEMOD_WRITE
, 0x4a, 0x01},
354 {DEMOD_WRITE
, 0x4b, 0x78},
355 {DEMOD_WRITE
, 0X4d, 0xd2},
356 {DEMOD_WRITE
, 0x4e, 0x6d},
357 {DEMOD_WRITE
, 0x50, 0x30},
358 {DEMOD_WRITE
, 0x51, 0x30},
359 {DEMOD_WRITE
, 0x54, 0x7b},
360 {DEMOD_WRITE
, 0x56, 0x09},
361 {DEMOD_WRITE
, 0x58, 0x59},
362 {DEMOD_WRITE
, 0x59, 0x37},
363 {DEMOD_WRITE
, 0x63, 0xfa},
367 static struct inittab fe_trigger
[] = {
368 {DEMOD_WRITE
, 0x97, 0x04},
369 {DEMOD_WRITE
, 0x99, 0x77},
370 {DEMOD_WRITE
, 0x9b, 0x64},
371 {DEMOD_WRITE
, 0x9e, 0x00},
372 {DEMOD_WRITE
, 0x9f, 0xf8},
373 {DEMOD_WRITE
, 0x98, 0xff},
374 {DEMOD_WRITE
, 0xc0, 0x0f},
375 {DEMOD_WRITE
, 0x89, 0x01},
376 {DEMOD_WRITE
, 0x00, 0x00},
377 {WRITE_DELAY
, 0x0a, 0x00},
378 {DEMOD_WRITE
, 0x00, 0x01},
379 {DEMOD_WRITE
, 0x00, 0x00},
380 {DEMOD_WRITE
, 0x9a, 0xb0},
384 static int m88rs2000_tab_set(struct m88rs2000_state
*state
,
392 for (i
= 0; i
< 255; i
++) {
393 switch (tab
[i
].cmd
) {
395 ret
= m88rs2000_writereg(state
, tab
[i
].reg
,
403 if (tab
[i
].reg
== 0xaa && tab
[i
].val
== 0xff)
416 static int m88rs2000_set_voltage(struct dvb_frontend
*fe
,
417 enum fe_sec_voltage volt
)
419 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
422 data
= m88rs2000_readreg(state
, 0xb2);
423 data
|= 0x03; /* bit0 V/H, bit1 off/on */
433 case SEC_VOLTAGE_OFF
:
437 m88rs2000_writereg(state
, 0xb2, data
);
442 static int m88rs2000_init(struct dvb_frontend
*fe
)
444 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
447 deb_info("m88rs2000: init chip\n");
448 /* Setup frontend from shutdown/cold */
449 if (state
->config
->inittab
)
450 ret
= m88rs2000_tab_set(state
,
451 (struct inittab
*)state
->config
->inittab
);
453 ret
= m88rs2000_tab_set(state
, m88rs2000_setup
);
458 static int m88rs2000_sleep(struct dvb_frontend
*fe
)
460 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
462 /* Shutdown the frondend */
463 ret
= m88rs2000_tab_set(state
, m88rs2000_shutdown
);
467 static int m88rs2000_read_status(struct dvb_frontend
*fe
,
468 enum fe_status
*status
)
470 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
471 u8 reg
= m88rs2000_readreg(state
, 0x8c);
475 if ((reg
& 0xee) == 0xee) {
476 *status
= FE_HAS_CARRIER
| FE_HAS_SIGNAL
| FE_HAS_VITERBI
477 | FE_HAS_SYNC
| FE_HAS_LOCK
;
478 if (state
->config
->set_ts_params
)
479 state
->config
->set_ts_params(fe
, CALL_IS_READ
);
484 static int m88rs2000_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
486 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
489 m88rs2000_writereg(state
, 0x9a, 0x30);
490 tmp0
= m88rs2000_readreg(state
, 0xd8);
491 if ((tmp0
& 0x10) != 0) {
492 m88rs2000_writereg(state
, 0x9a, 0xb0);
497 *ber
= (m88rs2000_readreg(state
, 0xd7) << 8) |
498 m88rs2000_readreg(state
, 0xd6);
500 tmp1
= m88rs2000_readreg(state
, 0xd9);
501 m88rs2000_writereg(state
, 0xd9, (tmp1
& ~7) | 4);
503 m88rs2000_writereg(state
, 0xd8, (tmp0
& ~8) | 0x30);
504 m88rs2000_writereg(state
, 0xd8, (tmp0
& ~8) | 0x30);
505 m88rs2000_writereg(state
, 0x9a, 0xb0);
510 static int m88rs2000_read_signal_strength(struct dvb_frontend
*fe
,
513 if (fe
->ops
.tuner_ops
.get_rf_strength
)
514 fe
->ops
.tuner_ops
.get_rf_strength(fe
, strength
);
519 static int m88rs2000_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
521 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
523 *snr
= 512 * m88rs2000_readreg(state
, 0x65);
528 static int m88rs2000_read_ucblocks(struct dvb_frontend
*fe
, u32
*ucblocks
)
530 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
533 *ucblocks
= (m88rs2000_readreg(state
, 0xd5) << 8) |
534 m88rs2000_readreg(state
, 0xd4);
535 tmp
= m88rs2000_readreg(state
, 0xd8);
536 m88rs2000_writereg(state
, 0xd8, tmp
& ~0x20);
537 /* needs two times */
538 m88rs2000_writereg(state
, 0xd8, tmp
| 0x20);
539 m88rs2000_writereg(state
, 0xd8, tmp
| 0x20);
544 static int m88rs2000_set_fec(struct m88rs2000_state
*state
,
545 enum fe_code_rate fec
)
571 reg
= m88rs2000_readreg(state
, 0x70);
573 ret
= m88rs2000_writereg(state
, 0x70, reg
| fec_set
);
575 ret
|= m88rs2000_writereg(state
, 0x76, 0x8);
580 static enum fe_code_rate
m88rs2000_get_fec(struct m88rs2000_state
*state
)
583 m88rs2000_writereg(state
, 0x9a, 0x30);
584 reg
= m88rs2000_readreg(state
, 0x76);
585 m88rs2000_writereg(state
, 0x9a, 0xb0);
608 static int m88rs2000_set_frontend(struct dvb_frontend
*fe
)
610 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
611 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
612 enum fe_status status
= 0;
618 state
->no_lock_count
= 0;
620 if (c
->delivery_system
!= SYS_DVBS
) {
621 deb_info("%s: unsupported delivery system selected (%d)\n",
622 __func__
, c
->delivery_system
);
627 if (fe
->ops
.tuner_ops
.set_params
)
628 ret
= fe
->ops
.tuner_ops
.set_params(fe
);
633 if (fe
->ops
.tuner_ops
.get_frequency
) {
634 ret
= fe
->ops
.tuner_ops
.get_frequency(fe
, &tuner_freq
);
639 offset
= (s16
)((s32
)tuner_freq
- c
->frequency
);
644 /* default mclk value 96.4285 * 2 * 1000 = 192857 */
645 if (((c
->frequency
% 192857) >= (192857 - 3000)) ||
646 (c
->frequency
% 192857) <= 3000)
647 ret
= m88rs2000_writereg(state
, 0x86, 0xc2);
649 ret
= m88rs2000_writereg(state
, 0x86, 0xc6);
651 ret
|= m88rs2000_set_carrieroffset(fe
, offset
);
655 /* Reset demod by symbol rate */
656 if (c
->symbol_rate
> 27500000)
657 ret
= m88rs2000_writereg(state
, 0xf1, 0xa4);
659 ret
= m88rs2000_writereg(state
, 0xf1, 0xbf);
661 ret
|= m88rs2000_tab_set(state
, fe_reset
);
666 ret
= m88rs2000_set_fec(state
, c
->fec_inner
);
667 ret
|= m88rs2000_writereg(state
, 0x85, 0x1);
668 ret
|= m88rs2000_writereg(state
, 0x8a, 0xbf);
669 ret
|= m88rs2000_writereg(state
, 0x8d, 0x1e);
670 ret
|= m88rs2000_writereg(state
, 0x90, 0xf1);
671 ret
|= m88rs2000_writereg(state
, 0x91, 0x08);
676 /* Set Symbol Rate */
677 ret
= m88rs2000_set_symbolrate(fe
, c
->symbol_rate
);
682 ret
= m88rs2000_tab_set(state
, fe_trigger
);
686 for (i
= 0; i
< 25; i
++) {
687 reg
= m88rs2000_readreg(state
, 0x8c);
688 if ((reg
& 0xee) == 0xee) {
689 status
= FE_HAS_LOCK
;
692 state
->no_lock_count
++;
693 if (state
->no_lock_count
== 15) {
694 reg
= m88rs2000_readreg(state
, 0x70);
696 m88rs2000_writereg(state
, 0x70, reg
);
697 state
->no_lock_count
= 0;
702 if (status
& FE_HAS_LOCK
) {
703 state
->fec_inner
= m88rs2000_get_fec(state
);
704 /* Uknown suspect SNR level */
705 reg
= m88rs2000_readreg(state
, 0x65);
708 state
->tuner_frequency
= c
->frequency
;
709 state
->symbol_rate
= c
->symbol_rate
;
713 static int m88rs2000_get_frontend(struct dvb_frontend
*fe
,
714 struct dtv_frontend_properties
*c
)
716 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
718 c
->fec_inner
= state
->fec_inner
;
719 c
->frequency
= state
->tuner_frequency
;
720 c
->symbol_rate
= state
->symbol_rate
;
724 static int m88rs2000_get_tune_settings(struct dvb_frontend
*fe
,
725 struct dvb_frontend_tune_settings
*tune
)
727 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
729 if (c
->symbol_rate
> 3000000)
730 tune
->min_delay_ms
= 2000;
732 tune
->min_delay_ms
= 3000;
734 tune
->step_size
= c
->symbol_rate
/ 16000;
735 tune
->max_drift
= c
->symbol_rate
/ 2000;
740 static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
742 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
745 m88rs2000_writereg(state
, 0x81, 0x84);
747 m88rs2000_writereg(state
, 0x81, 0x81);
752 static void m88rs2000_release(struct dvb_frontend
*fe
)
754 struct m88rs2000_state
*state
= fe
->demodulator_priv
;
758 static const struct dvb_frontend_ops m88rs2000_ops
= {
759 .delsys
= { SYS_DVBS
},
761 .name
= "M88RS2000 DVB-S",
762 .frequency_min
= 950000,
763 .frequency_max
= 2150000,
764 .frequency_stepsize
= 1000, /* kHz for QPSK frontends */
765 .frequency_tolerance
= 5000,
766 .symbol_rate_min
= 1000000,
767 .symbol_rate_max
= 45000000,
768 .symbol_rate_tolerance
= 500, /* ppm */
769 .caps
= FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
| FE_CAN_FEC_3_4
|
770 FE_CAN_FEC_5_6
| FE_CAN_FEC_7_8
|
771 FE_CAN_QPSK
| FE_CAN_INVERSION_AUTO
|
775 .release
= m88rs2000_release
,
776 .init
= m88rs2000_init
,
777 .sleep
= m88rs2000_sleep
,
778 .i2c_gate_ctrl
= m88rs2000_i2c_gate_ctrl
,
779 .read_status
= m88rs2000_read_status
,
780 .read_ber
= m88rs2000_read_ber
,
781 .read_signal_strength
= m88rs2000_read_signal_strength
,
782 .read_snr
= m88rs2000_read_snr
,
783 .read_ucblocks
= m88rs2000_read_ucblocks
,
784 .diseqc_send_master_cmd
= m88rs2000_send_diseqc_msg
,
785 .diseqc_send_burst
= m88rs2000_send_diseqc_burst
,
786 .set_tone
= m88rs2000_set_tone
,
787 .set_voltage
= m88rs2000_set_voltage
,
789 .set_frontend
= m88rs2000_set_frontend
,
790 .get_frontend
= m88rs2000_get_frontend
,
791 .get_tune_settings
= m88rs2000_get_tune_settings
,
794 struct dvb_frontend
*m88rs2000_attach(const struct m88rs2000_config
*config
,
795 struct i2c_adapter
*i2c
)
797 struct m88rs2000_state
*state
= NULL
;
799 /* allocate memory for the internal state */
800 state
= kzalloc(sizeof(struct m88rs2000_state
), GFP_KERNEL
);
804 /* setup the state */
805 state
->config
= config
;
807 state
->tuner_frequency
= 0;
808 state
->symbol_rate
= 0;
809 state
->fec_inner
= 0;
811 /* create dvb_frontend */
812 memcpy(&state
->frontend
.ops
, &m88rs2000_ops
,
813 sizeof(struct dvb_frontend_ops
));
814 state
->frontend
.demodulator_priv
= state
;
815 return &state
->frontend
;
822 EXPORT_SYMBOL(m88rs2000_attach
);
824 MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
825 MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
826 MODULE_LICENSE("GPL");
827 MODULE_VERSION("1.13");