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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / media / platform / pxa_camera.c
blobc71a00736541110ca150abb4ba725bf44026b0f5
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/moduleparam.h>
27 #include <linux/of.h>
28 #include <linux/of_graph.h>
29 #include <linux/time.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma/pxa-dma.h>
36
37 #include <media/v4l2-async.h>
38 #include <media/v4l2-clk.h>
39 #include <media/v4l2-common.h>
40 #include <media/v4l2-ctrls.h>
41 #include <media/v4l2-device.h>
42 #include <media/v4l2-event.h>
43 #include <media/v4l2-ioctl.h>
44 #include <media/v4l2-fwnode.h>
45
46 #include <media/videobuf2-dma-sg.h>
47
48 #include <linux/videodev2.h>
49
50 #include <linux/platform_data/media/camera-pxa.h>
51
52 #define PXA_CAM_VERSION "0.0.6"
53 #define PXA_CAM_DRV_NAME "pxa27x-camera"
54
55 #define DEFAULT_WIDTH 640
56 #define DEFAULT_HEIGHT 480
57
58 /* Camera Interface */
59 #define CICR0 0x0000
60 #define CICR1 0x0004
61 #define CICR2 0x0008
62 #define CICR3 0x000C
63 #define CICR4 0x0010
64 #define CISR 0x0014
65 #define CIFR 0x0018
66 #define CITOR 0x001C
67 #define CIBR0 0x0028
68 #define CIBR1 0x0030
69 #define CIBR2 0x0038
70
71 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
72 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
73 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
74 #define CICR0_ENB (1 << 28) /* Camera interface enable */
75 #define CICR0_DIS (1 << 27) /* Camera interface disable */
76 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
77 #define CICR0_TOM (1 << 9) /* Time-out mask */
78 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
79 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
80 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
81 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
82 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
83 #define CICR0_CDM (1 << 3) /* Disable-done mask */
84 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
85 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
86 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
87
88 #define CICR1_TBIT (1 << 31) /* Transparency bit */
89 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
90 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
91 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
92 #define CICR1_RGB_F (1 << 11) /* RGB format */
93 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
94 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
95 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
96 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
97 #define CICR1_DW (0x7 << 0) /* Data width mask */
98
99 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
100 wait count mask */
101 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
102 wait count mask */
103 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
104 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
105 wait count mask */
106 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
107 wait count mask */
108
109 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
110 wait count mask */
111 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
112 wait count mask */
113 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
114 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
115 wait count mask */
116 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
117
118 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
119 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
120 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
121 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
122 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
123 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
124 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
125 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
126
127 #define CISR_FTO (1 << 15) /* FIFO time-out */
128 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
129 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
130 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
131 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
132 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
133 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
134 #define CISR_EOL (1 << 8) /* End of line */
135 #define CISR_PAR_ERR (1 << 7) /* Parity error */
136 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
137 #define CISR_CDD (1 << 5) /* Camera interface disable done */
138 #define CISR_SOF (1 << 4) /* Start of frame */
139 #define CISR_EOF (1 << 3) /* End of frame */
140 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
141 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
142 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
143
144 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
145 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
146 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
147 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
148 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
149 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
150 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
151 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
152
153 #define CICR0_SIM_MP (0 << 24)
154 #define CICR0_SIM_SP (1 << 24)
155 #define CICR0_SIM_MS (2 << 24)
156 #define CICR0_SIM_EP (3 << 24)
157 #define CICR0_SIM_ES (4 << 24)
158
159 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
160 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
161 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
162 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
163 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
164
165 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
166 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
167 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
168 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
169 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
170
171 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
172 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
173 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
174 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
175
176 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
177 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
178 CICR0_EOFM | CICR0_FOM)
179
180 #define sensor_call(cam, o, f, args...) \
181 v4l2_subdev_call(cam->sensor, o, f, ##args)
182
183 /*
184 * Format handling
185 */
186
187 /**
188 * enum pxa_mbus_packing - data packing types on the media-bus
189 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
190 * sample represents one pixel
191 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
192 * possibly incomplete byte high bits are padding
193 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
194 * to 16 bits
195 */
196 enum pxa_mbus_packing {
197 PXA_MBUS_PACKING_NONE,
198 PXA_MBUS_PACKING_2X8_PADHI,
199 PXA_MBUS_PACKING_EXTEND16,
200 };
201
202 /**
203 * enum pxa_mbus_order - sample order on the media bus
204 * @PXA_MBUS_ORDER_LE: least significant sample first
205 * @PXA_MBUS_ORDER_BE: most significant sample first
206 */
207 enum pxa_mbus_order {
208 PXA_MBUS_ORDER_LE,
209 PXA_MBUS_ORDER_BE,
210 };
211
212 /**
213 * enum pxa_mbus_layout - planes layout in memory
214 * @PXA_MBUS_LAYOUT_PACKED: color components packed
215 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
216 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
217 * chroma plane (C plane is half the size
218 * of Y plane)
219 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
220 * chroma plane (C plane is the same size
221 * as Y plane)
222 */
223 enum pxa_mbus_layout {
224 PXA_MBUS_LAYOUT_PACKED = 0,
225 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
226 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
227 PXA_MBUS_LAYOUT_PLANAR_Y_C,
228 };
229
230 /**
231 * struct pxa_mbus_pixelfmt - Data format on the media bus
232 * @name: Name of the format
233 * @fourcc: Fourcc code, that will be obtained if the data is
234 * stored in memory in the following way:
235 * @packing: Type of sample-packing, that has to be used
236 * @order: Sample order when storing in memory
237 * @layout: Planes layout in memory
238 * @bits_per_sample: How many bits the bridge has to sample
239 */
240 struct pxa_mbus_pixelfmt {
241 const char *name;
242 u32 fourcc;
243 enum pxa_mbus_packing packing;
244 enum pxa_mbus_order order;
245 enum pxa_mbus_layout layout;
246 u8 bits_per_sample;
247 };
248
249 /**
250 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
251 * @code: mediabus pixel-code
252 * @fmt: pixel format description
253 */
254 struct pxa_mbus_lookup {
255 u32 code;
256 struct pxa_mbus_pixelfmt fmt;
257 };
258
259 static const struct pxa_mbus_lookup mbus_fmt[] = {
260 {
261 .code = MEDIA_BUS_FMT_YUYV8_2X8,
262 .fmt = {
263 .fourcc = V4L2_PIX_FMT_YUYV,
264 .name = "YUYV",
265 .bits_per_sample = 8,
266 .packing = PXA_MBUS_PACKING_2X8_PADHI,
267 .order = PXA_MBUS_ORDER_LE,
268 .layout = PXA_MBUS_LAYOUT_PACKED,
269 },
270 }, {
271 .code = MEDIA_BUS_FMT_YVYU8_2X8,
272 .fmt = {
273 .fourcc = V4L2_PIX_FMT_YVYU,
274 .name = "YVYU",
275 .bits_per_sample = 8,
276 .packing = PXA_MBUS_PACKING_2X8_PADHI,
277 .order = PXA_MBUS_ORDER_LE,
278 .layout = PXA_MBUS_LAYOUT_PACKED,
279 },
280 }, {
281 .code = MEDIA_BUS_FMT_UYVY8_2X8,
282 .fmt = {
283 .fourcc = V4L2_PIX_FMT_UYVY,
284 .name = "UYVY",
285 .bits_per_sample = 8,
286 .packing = PXA_MBUS_PACKING_2X8_PADHI,
287 .order = PXA_MBUS_ORDER_LE,
288 .layout = PXA_MBUS_LAYOUT_PACKED,
289 },
290 }, {
291 .code = MEDIA_BUS_FMT_VYUY8_2X8,
292 .fmt = {
293 .fourcc = V4L2_PIX_FMT_VYUY,
294 .name = "VYUY",
295 .bits_per_sample = 8,
296 .packing = PXA_MBUS_PACKING_2X8_PADHI,
297 .order = PXA_MBUS_ORDER_LE,
298 .layout = PXA_MBUS_LAYOUT_PACKED,
299 },
300 }, {
301 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
302 .fmt = {
303 .fourcc = V4L2_PIX_FMT_RGB555,
304 .name = "RGB555",
305 .bits_per_sample = 8,
306 .packing = PXA_MBUS_PACKING_2X8_PADHI,
307 .order = PXA_MBUS_ORDER_LE,
308 .layout = PXA_MBUS_LAYOUT_PACKED,
309 },
310 }, {
311 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
312 .fmt = {
313 .fourcc = V4L2_PIX_FMT_RGB555X,
314 .name = "RGB555X",
315 .bits_per_sample = 8,
316 .packing = PXA_MBUS_PACKING_2X8_PADHI,
317 .order = PXA_MBUS_ORDER_BE,
318 .layout = PXA_MBUS_LAYOUT_PACKED,
319 },
320 }, {
321 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
322 .fmt = {
323 .fourcc = V4L2_PIX_FMT_RGB565,
324 .name = "RGB565",
325 .bits_per_sample = 8,
326 .packing = PXA_MBUS_PACKING_2X8_PADHI,
327 .order = PXA_MBUS_ORDER_LE,
328 .layout = PXA_MBUS_LAYOUT_PACKED,
329 },
330 }, {
331 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
332 .fmt = {
333 .fourcc = V4L2_PIX_FMT_RGB565X,
334 .name = "RGB565X",
335 .bits_per_sample = 8,
336 .packing = PXA_MBUS_PACKING_2X8_PADHI,
337 .order = PXA_MBUS_ORDER_BE,
338 .layout = PXA_MBUS_LAYOUT_PACKED,
339 },
340 }, {
341 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
342 .fmt = {
343 .fourcc = V4L2_PIX_FMT_SBGGR8,
344 .name = "Bayer 8 BGGR",
345 .bits_per_sample = 8,
346 .packing = PXA_MBUS_PACKING_NONE,
347 .order = PXA_MBUS_ORDER_LE,
348 .layout = PXA_MBUS_LAYOUT_PACKED,
349 },
350 }, {
351 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
352 .fmt = {
353 .fourcc = V4L2_PIX_FMT_SGBRG8,
354 .name = "Bayer 8 GBRG",
355 .bits_per_sample = 8,
356 .packing = PXA_MBUS_PACKING_NONE,
357 .order = PXA_MBUS_ORDER_LE,
358 .layout = PXA_MBUS_LAYOUT_PACKED,
359 },
360 }, {
361 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
362 .fmt = {
363 .fourcc = V4L2_PIX_FMT_SGRBG8,
364 .name = "Bayer 8 GRBG",
365 .bits_per_sample = 8,
366 .packing = PXA_MBUS_PACKING_NONE,
367 .order = PXA_MBUS_ORDER_LE,
368 .layout = PXA_MBUS_LAYOUT_PACKED,
369 },
370 }, {
371 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
372 .fmt = {
373 .fourcc = V4L2_PIX_FMT_SRGGB8,
374 .name = "Bayer 8 RGGB",
375 .bits_per_sample = 8,
376 .packing = PXA_MBUS_PACKING_NONE,
377 .order = PXA_MBUS_ORDER_LE,
378 .layout = PXA_MBUS_LAYOUT_PACKED,
379 },
380 }, {
381 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
382 .fmt = {
383 .fourcc = V4L2_PIX_FMT_SBGGR10,
384 .name = "Bayer 10 BGGR",
385 .bits_per_sample = 10,
386 .packing = PXA_MBUS_PACKING_EXTEND16,
387 .order = PXA_MBUS_ORDER_LE,
388 .layout = PXA_MBUS_LAYOUT_PACKED,
389 },
390 }, {
391 .code = MEDIA_BUS_FMT_Y8_1X8,
392 .fmt = {
393 .fourcc = V4L2_PIX_FMT_GREY,
394 .name = "Grey",
395 .bits_per_sample = 8,
396 .packing = PXA_MBUS_PACKING_NONE,
397 .order = PXA_MBUS_ORDER_LE,
398 .layout = PXA_MBUS_LAYOUT_PACKED,
399 },
400 }, {
401 .code = MEDIA_BUS_FMT_Y10_1X10,
402 .fmt = {
403 .fourcc = V4L2_PIX_FMT_Y10,
404 .name = "Grey 10bit",
405 .bits_per_sample = 10,
406 .packing = PXA_MBUS_PACKING_EXTEND16,
407 .order = PXA_MBUS_ORDER_LE,
408 .layout = PXA_MBUS_LAYOUT_PACKED,
409 },
410 }, {
411 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
412 .fmt = {
413 .fourcc = V4L2_PIX_FMT_SBGGR10,
414 .name = "Bayer 10 BGGR",
415 .bits_per_sample = 8,
416 .packing = PXA_MBUS_PACKING_2X8_PADHI,
417 .order = PXA_MBUS_ORDER_LE,
418 .layout = PXA_MBUS_LAYOUT_PACKED,
419 },
420 }, {
421 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
422 .fmt = {
423 .fourcc = V4L2_PIX_FMT_SBGGR10,
424 .name = "Bayer 10 BGGR",
425 .bits_per_sample = 8,
426 .packing = PXA_MBUS_PACKING_2X8_PADHI,
427 .order = PXA_MBUS_ORDER_BE,
428 .layout = PXA_MBUS_LAYOUT_PACKED,
429 },
430 }, {
431 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
432 .fmt = {
433 .fourcc = V4L2_PIX_FMT_RGB444,
434 .name = "RGB444",
435 .bits_per_sample = 8,
436 .packing = PXA_MBUS_PACKING_2X8_PADHI,
437 .order = PXA_MBUS_ORDER_BE,
438 .layout = PXA_MBUS_LAYOUT_PACKED,
439 },
440 }, {
441 .code = MEDIA_BUS_FMT_UYVY8_1X16,
442 .fmt = {
443 .fourcc = V4L2_PIX_FMT_UYVY,
444 .name = "UYVY 16bit",
445 .bits_per_sample = 16,
446 .packing = PXA_MBUS_PACKING_EXTEND16,
447 .order = PXA_MBUS_ORDER_LE,
448 .layout = PXA_MBUS_LAYOUT_PACKED,
449 },
450 }, {
451 .code = MEDIA_BUS_FMT_VYUY8_1X16,
452 .fmt = {
453 .fourcc = V4L2_PIX_FMT_VYUY,
454 .name = "VYUY 16bit",
455 .bits_per_sample = 16,
456 .packing = PXA_MBUS_PACKING_EXTEND16,
457 .order = PXA_MBUS_ORDER_LE,
458 .layout = PXA_MBUS_LAYOUT_PACKED,
459 },
460 }, {
461 .code = MEDIA_BUS_FMT_YUYV8_1X16,
462 .fmt = {
463 .fourcc = V4L2_PIX_FMT_YUYV,
464 .name = "YUYV 16bit",
465 .bits_per_sample = 16,
466 .packing = PXA_MBUS_PACKING_EXTEND16,
467 .order = PXA_MBUS_ORDER_LE,
468 .layout = PXA_MBUS_LAYOUT_PACKED,
469 },
470 }, {
471 .code = MEDIA_BUS_FMT_YVYU8_1X16,
472 .fmt = {
473 .fourcc = V4L2_PIX_FMT_YVYU,
474 .name = "YVYU 16bit",
475 .bits_per_sample = 16,
476 .packing = PXA_MBUS_PACKING_EXTEND16,
477 .order = PXA_MBUS_ORDER_LE,
478 .layout = PXA_MBUS_LAYOUT_PACKED,
479 },
480 }, {
481 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
482 .fmt = {
483 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
484 .name = "Bayer 10 BGGR DPCM 8",
485 .bits_per_sample = 8,
486 .packing = PXA_MBUS_PACKING_NONE,
487 .order = PXA_MBUS_ORDER_LE,
488 .layout = PXA_MBUS_LAYOUT_PACKED,
489 },
490 }, {
491 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
492 .fmt = {
493 .fourcc = V4L2_PIX_FMT_SGBRG10,
494 .name = "Bayer 10 GBRG",
495 .bits_per_sample = 10,
496 .packing = PXA_MBUS_PACKING_EXTEND16,
497 .order = PXA_MBUS_ORDER_LE,
498 .layout = PXA_MBUS_LAYOUT_PACKED,
499 },
500 }, {
501 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
502 .fmt = {
503 .fourcc = V4L2_PIX_FMT_SGRBG10,
504 .name = "Bayer 10 GRBG",
505 .bits_per_sample = 10,
506 .packing = PXA_MBUS_PACKING_EXTEND16,
507 .order = PXA_MBUS_ORDER_LE,
508 .layout = PXA_MBUS_LAYOUT_PACKED,
509 },
510 }, {
511 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
512 .fmt = {
513 .fourcc = V4L2_PIX_FMT_SRGGB10,
514 .name = "Bayer 10 RGGB",
515 .bits_per_sample = 10,
516 .packing = PXA_MBUS_PACKING_EXTEND16,
517 .order = PXA_MBUS_ORDER_LE,
518 .layout = PXA_MBUS_LAYOUT_PACKED,
519 },
520 }, {
521 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
522 .fmt = {
523 .fourcc = V4L2_PIX_FMT_SBGGR12,
524 .name = "Bayer 12 BGGR",
525 .bits_per_sample = 12,
526 .packing = PXA_MBUS_PACKING_EXTEND16,
527 .order = PXA_MBUS_ORDER_LE,
528 .layout = PXA_MBUS_LAYOUT_PACKED,
529 },
530 }, {
531 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
532 .fmt = {
533 .fourcc = V4L2_PIX_FMT_SGBRG12,
534 .name = "Bayer 12 GBRG",
535 .bits_per_sample = 12,
536 .packing = PXA_MBUS_PACKING_EXTEND16,
537 .order = PXA_MBUS_ORDER_LE,
538 .layout = PXA_MBUS_LAYOUT_PACKED,
539 },
540 }, {
541 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
542 .fmt = {
543 .fourcc = V4L2_PIX_FMT_SGRBG12,
544 .name = "Bayer 12 GRBG",
545 .bits_per_sample = 12,
546 .packing = PXA_MBUS_PACKING_EXTEND16,
547 .order = PXA_MBUS_ORDER_LE,
548 .layout = PXA_MBUS_LAYOUT_PACKED,
549 },
550 }, {
551 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
552 .fmt = {
553 .fourcc = V4L2_PIX_FMT_SRGGB12,
554 .name = "Bayer 12 RGGB",
555 .bits_per_sample = 12,
556 .packing = PXA_MBUS_PACKING_EXTEND16,
557 .order = PXA_MBUS_ORDER_LE,
558 .layout = PXA_MBUS_LAYOUT_PACKED,
559 },
560 },
561 };
562
563 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
564 {
565 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
566 return width * mf->bits_per_sample / 8;
567
568 switch (mf->packing) {
569 case PXA_MBUS_PACKING_NONE:
570 return width * mf->bits_per_sample / 8;
571 case PXA_MBUS_PACKING_2X8_PADHI:
572 case PXA_MBUS_PACKING_EXTEND16:
573 return width * 2;
574 }
575 return -EINVAL;
576 }
577
578 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
579 u32 bytes_per_line, u32 height)
580 {
581 if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
582 return bytes_per_line * height;
583
584 switch (mf->packing) {
585 case PXA_MBUS_PACKING_2X8_PADHI:
586 return bytes_per_line * height * 2;
587 default:
588 return -EINVAL;
589 }
590 }
591
592 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
593 u32 code,
594 const struct pxa_mbus_lookup *lookup,
595 int n)
596 {
597 int i;
598
599 for (i = 0; i < n; i++)
600 if (lookup[i].code == code)
601 return &lookup[i].fmt;
602
603 return NULL;
604 }
605
606 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
607 u32 code)
608 {
609 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
610 }
611
612 static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
613 unsigned int flags)
614 {
615 unsigned long common_flags;
616 bool hsync = true, vsync = true, pclk, data, mode;
617 bool mipi_lanes, mipi_clock;
618
619 common_flags = cfg->flags & flags;
620
621 switch (cfg->type) {
622 case V4L2_MBUS_PARALLEL:
623 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
624 V4L2_MBUS_HSYNC_ACTIVE_LOW);
625 vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
626 V4L2_MBUS_VSYNC_ACTIVE_LOW);
627 /* fall through */
628 case V4L2_MBUS_BT656:
629 pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
630 V4L2_MBUS_PCLK_SAMPLE_FALLING);
631 data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
632 V4L2_MBUS_DATA_ACTIVE_LOW);
633 mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
634 return (!hsync || !vsync || !pclk || !data || !mode) ?
635 0 : common_flags;
636 case V4L2_MBUS_CSI2:
637 mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
638 mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
639 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
640 return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
641 default:
642 WARN_ON(1);
643 return -EINVAL;
644 }
645 return 0;
646 }
647
648 /**
649 * struct pxa_camera_format_xlate - match between host and sensor formats
650 * @code: code of a sensor provided format
651 * @host_fmt: host format after host translation from code
652 *
653 * Host and sensor translation structure. Used in table of host and sensor
654 * formats matchings in pxa_camera_device. A host can override the generic list
655 * generation by implementing get_formats(), and use it for format checks and
656 * format setup.
657 */
658 struct pxa_camera_format_xlate {
659 u32 code;
660 const struct pxa_mbus_pixelfmt *host_fmt;
661 };
662
663 /*
664 * Structures
665 */
666 enum pxa_camera_active_dma {
667 DMA_Y = 0x1,
668 DMA_U = 0x2,
669 DMA_V = 0x4,
670 };
671
672 /* buffer for one video frame */
673 struct pxa_buffer {
674 /* common v4l buffer stuff -- must be first */
675 struct vb2_v4l2_buffer vbuf;
676 struct list_head queue;
677 u32 code;
678 int nb_planes;
679 /* our descriptor lists for Y, U and V channels */
680 struct dma_async_tx_descriptor *descs[3];
681 dma_cookie_t cookie[3];
682 struct scatterlist *sg[3];
683 int sg_len[3];
684 size_t plane_sizes[3];
685 int inwork;
686 enum pxa_camera_active_dma active_dma;
687 };
688
689 struct pxa_camera_dev {
690 struct v4l2_device v4l2_dev;
691 struct video_device vdev;
692 struct v4l2_async_notifier notifier;
693 struct vb2_queue vb2_vq;
694 struct v4l2_subdev *sensor;
695 struct pxa_camera_format_xlate *user_formats;
696 const struct pxa_camera_format_xlate *current_fmt;
697 struct v4l2_pix_format current_pix;
698
699 struct v4l2_async_subdev asd;
700 struct v4l2_async_subdev *asds[1];
701
702 /*
703 * PXA27x is only supposed to handle one camera on its Quick Capture
704 * interface. If anyone ever builds hardware to enable more than
705 * one camera, they will have to modify this driver too
706 */
707 struct clk *clk;
708
709 unsigned int irq;
710 void __iomem *base;
711
712 int channels;
713 struct dma_chan *dma_chans[3];
714
715 struct pxacamera_platform_data *pdata;
716 struct resource *res;
717 unsigned long platform_flags;
718 unsigned long ciclk;
719 unsigned long mclk;
720 u32 mclk_divisor;
721 struct v4l2_clk *mclk_clk;
722 u16 width_flags; /* max 10 bits */
723
724 struct list_head capture;
725
726 spinlock_t lock;
727 struct mutex mlock;
728 unsigned int buf_sequence;
729
730 struct pxa_buffer *active;
731 struct tasklet_struct task_eof;
732
733 u32 save_cicr[5];
734 };
735
736 struct pxa_cam {
737 unsigned long flags;
738 };
739
740 static const char *pxa_cam_driver_description = "PXA_Camera";
741
742 /*
743 * Format translation functions
744 */
745 static const struct pxa_camera_format_xlate
746 *pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats,
747 unsigned int fourcc)
748 {
749 unsigned int i;
750
751 for (i = 0; user_formats[i].code; i++)
752 if (user_formats[i].host_fmt->fourcc == fourcc)
753 return user_formats + i;
754 return NULL;
755 }
756
757 static struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate(
758 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
759 int (*get_formats)(struct v4l2_device *, unsigned int,
760 struct pxa_camera_format_xlate *xlate))
761 {
762 unsigned int i, fmts = 0, raw_fmts = 0;
763 int ret;
764 struct v4l2_subdev_mbus_code_enum code = {
765 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
766 };
767 struct pxa_camera_format_xlate *user_formats;
768
769 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
770 raw_fmts++;
771 code.index++;
772 }
773
774 /*
775 * First pass - only count formats this host-sensor
776 * configuration can provide
777 */
778 for (i = 0; i < raw_fmts; i++) {
779 ret = get_formats(v4l2_dev, i, NULL);
780 if (ret < 0)
781 return ERR_PTR(ret);
782 fmts += ret;
783 }
784
785 if (!fmts)
786 return ERR_PTR(-ENXIO);
787
788 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
789 if (!user_formats)
790 return ERR_PTR(-ENOMEM);
791
792 /* Second pass - actually fill data formats */
793 fmts = 0;
794 for (i = 0; i < raw_fmts; i++) {
795 ret = get_formats(v4l2_dev, i, user_formats + fmts);
796 if (ret < 0)
797 goto egfmt;
798 fmts += ret;
799 }
800 user_formats[fmts].code = 0;
801
802 return user_formats;
803 egfmt:
804 kfree(user_formats);
805 return ERR_PTR(ret);
806 }
807
808 /*
809 * Videobuf operations
810 */
811 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
812 {
813 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
814
815 return container_of(vbuf, struct pxa_buffer, vbuf);
816 }
817
818 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
819 {
820 return pcdev->v4l2_dev.dev;
821 }
822
823 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
824 {
825 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
826 }
827
828 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
829 enum pxa_camera_active_dma act_dma);
830
831 static void pxa_camera_dma_irq_y(void *data)
832 {
833 struct pxa_camera_dev *pcdev = data;
834
835 pxa_camera_dma_irq(pcdev, DMA_Y);
836 }
837
838 static void pxa_camera_dma_irq_u(void *data)
839 {
840 struct pxa_camera_dev *pcdev = data;
841
842 pxa_camera_dma_irq(pcdev, DMA_U);
843 }
844
845 static void pxa_camera_dma_irq_v(void *data)
846 {
847 struct pxa_camera_dev *pcdev = data;
848
849 pxa_camera_dma_irq(pcdev, DMA_V);
850 }
851
852 /**
853 * pxa_init_dma_channel - init dma descriptors
854 * @pcdev: pxa camera device
855 * @buf: pxa camera buffer
856 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
857 * @sg: dma scatter list
858 * @sglen: dma scatter list length
859 *
860 * Prepares the pxa dma descriptors to transfer one camera channel.
861 *
862 * Returns 0 if success or -ENOMEM if no memory is available
863 */
864 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
865 struct pxa_buffer *buf, int channel,
866 struct scatterlist *sg, int sglen)
867 {
868 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
869 struct dma_async_tx_descriptor *tx;
870
871 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
872 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
873 if (!tx) {
874 dev_err(pcdev_to_dev(pcdev),
875 "dmaengine_prep_slave_sg failed\n");
876 goto fail;
877 }
878
879 tx->callback_param = pcdev;
880 switch (channel) {
881 case 0:
882 tx->callback = pxa_camera_dma_irq_y;
883 break;
884 case 1:
885 tx->callback = pxa_camera_dma_irq_u;
886 break;
887 case 2:
888 tx->callback = pxa_camera_dma_irq_v;
889 break;
890 }
891
892 buf->descs[channel] = tx;
893 return 0;
894 fail:
895 dev_dbg(pcdev_to_dev(pcdev),
896 "%s (vb=%p) dma_tx=%p\n",
897 __func__, buf, tx);
898
899 return -ENOMEM;
900 }
901
902 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
903 struct pxa_buffer *buf)
904 {
905 buf->active_dma = DMA_Y;
906 if (buf->nb_planes == 3)
907 buf->active_dma |= DMA_U | DMA_V;
908 }
909
910 /**
911 * pxa_dma_start_channels - start DMA channel for active buffer
912 * @pcdev: pxa camera device
913 *
914 * Initialize DMA channels to the beginning of the active video buffer, and
915 * start these channels.
916 */
917 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
918 {
919 int i;
920
921 for (i = 0; i < pcdev->channels; i++) {
922 dev_dbg(pcdev_to_dev(pcdev),
923 "%s (channel=%d)\n", __func__, i);
924 dma_async_issue_pending(pcdev->dma_chans[i]);
925 }
926 }
927
928 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
929 {
930 int i;
931
932 for (i = 0; i < pcdev->channels; i++) {
933 dev_dbg(pcdev_to_dev(pcdev),
934 "%s (channel=%d)\n", __func__, i);
935 dmaengine_terminate_all(pcdev->dma_chans[i]);
936 }
937 }
938
939 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
940 struct pxa_buffer *buf)
941 {
942 int i;
943
944 for (i = 0; i < pcdev->channels; i++) {
945 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
946 dev_dbg(pcdev_to_dev(pcdev),
947 "%s (channel=%d) : submit vb=%p cookie=%d\n",
948 __func__, i, buf, buf->descs[i]->cookie);
949 }
950 }
951
952 /**
953 * pxa_camera_start_capture - start video capturing
954 * @pcdev: camera device
955 *
956 * Launch capturing. DMA channels should not be active yet. They should get
957 * activated at the end of frame interrupt, to capture only whole frames, and
958 * never begin the capture of a partial frame.
959 */
960 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
961 {
962 unsigned long cicr0;
963
964 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
965 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
966 /* Enable End-Of-Frame Interrupt */
967 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
968 cicr0 &= ~CICR0_EOFM;
969 __raw_writel(cicr0, pcdev->base + CICR0);
970 }
971
972 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
973 {
974 unsigned long cicr0;
975
976 pxa_dma_stop_channels(pcdev);
977
978 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
979 __raw_writel(cicr0, pcdev->base + CICR0);
980
981 pcdev->active = NULL;
982 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
983 }
984
985 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
986 struct pxa_buffer *buf,
987 enum vb2_buffer_state state)
988 {
989 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
990 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
991
992 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
993 list_del_init(&buf->queue);
994 vb->timestamp = ktime_get_ns();
995 vbuf->sequence = pcdev->buf_sequence++;
996 vbuf->field = V4L2_FIELD_NONE;
997 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
998 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
999 __func__, buf);
1000
1001 if (list_empty(&pcdev->capture)) {
1002 pxa_camera_stop_capture(pcdev);
1003 return;
1004 }
1005
1006 pcdev->active = list_entry(pcdev->capture.next,
1007 struct pxa_buffer, queue);
1008 }
1009
1010 /**
1011 * pxa_camera_check_link_miss - check missed DMA linking
1012 * @pcdev: camera device
1013 * @last_submitted: an opaque DMA cookie for last submitted
1014 * @last_issued: an opaque DMA cookie for last issued
1015 *
1016 * The DMA chaining is done with DMA running. This means a tiny temporal window
1017 * remains, where a buffer is queued on the chain, while the chain is already
1018 * stopped. This means the tailed buffer would never be transferred by DMA.
1019 * This function restarts the capture for this corner case, where :
1020 * - DADR() == DADDR_STOP
1021 * - a videobuffer is queued on the pcdev->capture list
1022 *
1023 * Please check the "DMA hot chaining timeslice issue" in
1024 * Documentation/video4linux/pxa_camera.txt
1025 *
1026 * Context: should only be called within the dma irq handler
1027 */
1028 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
1029 dma_cookie_t last_submitted,
1030 dma_cookie_t last_issued)
1031 {
1032 bool is_dma_stopped = last_submitted != last_issued;
1033
1034 dev_dbg(pcdev_to_dev(pcdev),
1035 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
1036 __func__, pcdev->active, is_dma_stopped);
1037
1038 if (pcdev->active && is_dma_stopped)
1039 pxa_camera_start_capture(pcdev);
1040 }
1041
1042 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1043 enum pxa_camera_active_dma act_dma)
1044 {
1045 struct pxa_buffer *buf, *last_buf;
1046 unsigned long flags;
1047 u32 camera_status, overrun;
1048 int chan;
1049 enum dma_status last_status;
1050 dma_cookie_t last_issued;
1051
1052 spin_lock_irqsave(&pcdev->lock, flags);
1053
1054 camera_status = __raw_readl(pcdev->base + CISR);
1055 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1056 camera_status, act_dma);
1057 overrun = CISR_IFO_0;
1058 if (pcdev->channels == 3)
1059 overrun |= CISR_IFO_1 | CISR_IFO_2;
1060
1061 /*
1062 * pcdev->active should not be NULL in DMA irq handler.
1063 *
1064 * But there is one corner case : if capture was stopped due to an
1065 * overrun of channel 1, and at that same channel 2 was completed.
1066 *
1067 * When handling the overrun in DMA irq for channel 1, we'll stop the
1068 * capture and restart it (and thus set pcdev->active to NULL). But the
1069 * DMA irq handler will already be pending for channel 2. So on entering
1070 * the DMA irq handler for channel 2 there will be no active buffer, yet
1071 * that is normal.
1072 */
1073 if (!pcdev->active)
1074 goto out;
1075
1076 buf = pcdev->active;
1077 WARN_ON(buf->inwork || list_empty(&buf->queue));
1078
1079 /*
1080 * It's normal if the last frame creates an overrun, as there
1081 * are no more DMA descriptors to fetch from QCI fifos
1082 */
1083 switch (act_dma) {
1084 case DMA_U:
1085 chan = 1;
1086 break;
1087 case DMA_V:
1088 chan = 2;
1089 break;
1090 default:
1091 chan = 0;
1092 break;
1093 }
1094 last_buf = list_entry(pcdev->capture.prev,
1095 struct pxa_buffer, queue);
1096 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1097 last_buf->cookie[chan],
1098 NULL, &last_issued);
1099 if (camera_status & overrun &&
1100 last_status != DMA_COMPLETE) {
1101 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1102 camera_status);
1103 pxa_camera_stop_capture(pcdev);
1104 list_for_each_entry(buf, &pcdev->capture, queue)
1105 pxa_dma_add_tail_buf(pcdev, buf);
1106 pxa_camera_start_capture(pcdev);
1107 goto out;
1108 }
1109 buf->active_dma &= ~act_dma;
1110 if (!buf->active_dma) {
1111 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1112 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1113 last_issued);
1114 }
1115
1116 out:
1117 spin_unlock_irqrestore(&pcdev->lock, flags);
1118 }
1119
1120 static u32 mclk_get_divisor(struct platform_device *pdev,
1121 struct pxa_camera_dev *pcdev)
1122 {
1123 unsigned long mclk = pcdev->mclk;
1124 u32 div;
1125 unsigned long lcdclk;
1126
1127 lcdclk = clk_get_rate(pcdev->clk);
1128 pcdev->ciclk = lcdclk;
1129
1130 /* mclk <= ciclk / 4 (27.4.2) */
1131 if (mclk > lcdclk / 4) {
1132 mclk = lcdclk / 4;
1133 dev_warn(&pdev->dev,
1134 "Limiting master clock to %lu\n", mclk);
1135 }
1136
1137 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1138 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1139
1140 /* If we're not supplying MCLK, leave it at 0 */
1141 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1142 pcdev->mclk = lcdclk / (2 * (div + 1));
1143
1144 dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1145 lcdclk, mclk, div);
1146
1147 return div;
1148 }
1149
1150 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1151 unsigned long pclk)
1152 {
1153 /* We want a timeout > 1 pixel time, not ">=" */
1154 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1155
1156 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1157 }
1158
1159 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1160 {
1161 u32 cicr4 = 0;
1162
1163 /* disable all interrupts */
1164 __raw_writel(0x3ff, pcdev->base + CICR0);
1165
1166 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1167 cicr4 |= CICR4_PCLK_EN;
1168 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1169 cicr4 |= CICR4_MCLK_EN;
1170 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1171 cicr4 |= CICR4_PCP;
1172 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1173 cicr4 |= CICR4_HSP;
1174 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1175 cicr4 |= CICR4_VSP;
1176
1177 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1178
1179 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1180 /* Initialise the timeout under the assumption pclk = mclk */
1181 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1182 else
1183 /* "Safe default" - 13MHz */
1184 recalculate_fifo_timeout(pcdev, 13000000);
1185
1186 clk_prepare_enable(pcdev->clk);
1187 }
1188
1189 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1190 {
1191 clk_disable_unprepare(pcdev->clk);
1192 }
1193
1194 static void pxa_camera_eof(unsigned long arg)
1195 {
1196 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
1197 unsigned long cifr;
1198 struct pxa_buffer *buf;
1199
1200 dev_dbg(pcdev_to_dev(pcdev),
1201 "Camera interrupt status 0x%x\n",
1202 __raw_readl(pcdev->base + CISR));
1203
1204 /* Reset the FIFOs */
1205 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1206 __raw_writel(cifr, pcdev->base + CIFR);
1207
1208 pcdev->active = list_first_entry(&pcdev->capture,
1209 struct pxa_buffer, queue);
1210 buf = pcdev->active;
1211 pxa_videobuf_set_actdma(pcdev, buf);
1212
1213 pxa_dma_start_channels(pcdev);
1214 }
1215
1216 static irqreturn_t pxa_camera_irq(int irq, void *data)
1217 {
1218 struct pxa_camera_dev *pcdev = data;
1219 unsigned long status, cicr0;
1220
1221 status = __raw_readl(pcdev->base + CISR);
1222 dev_dbg(pcdev_to_dev(pcdev),
1223 "Camera interrupt status 0x%lx\n", status);
1224
1225 if (!status)
1226 return IRQ_NONE;
1227
1228 __raw_writel(status, pcdev->base + CISR);
1229
1230 if (status & CISR_EOF) {
1231 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1232 __raw_writel(cicr0, pcdev->base + CICR0);
1233 tasklet_schedule(&pcdev->task_eof);
1234 }
1235
1236 return IRQ_HANDLED;
1237 }
1238
1239 static int test_platform_param(struct pxa_camera_dev *pcdev,
1240 unsigned char buswidth, unsigned long *flags)
1241 {
1242 /*
1243 * Platform specified synchronization and pixel clock polarities are
1244 * only a recommendation and are only used during probing. The PXA270
1245 * quick capture interface supports both.
1246 */
1247 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1248 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1249 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1250 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1251 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1252 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1253 V4L2_MBUS_DATA_ACTIVE_HIGH |
1254 V4L2_MBUS_PCLK_SAMPLE_RISING |
1255 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1256
1257 /* If requested data width is supported by the platform, use it */
1258 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1259 return 0;
1260
1261 return -EINVAL;
1262 }
1263
1264 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1265 unsigned long flags, __u32 pixfmt)
1266 {
1267 unsigned long dw, bpp;
1268 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1269 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1270
1271 if (ret < 0)
1272 y_skip_top = 0;
1273
1274 /*
1275 * Datawidth is now guaranteed to be equal to one of the three values.
1276 * We fix bit-per-pixel equal to data-width...
1277 */
1278 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1279 case 10:
1280 dw = 4;
1281 bpp = 0x40;
1282 break;
1283 case 9:
1284 dw = 3;
1285 bpp = 0x20;
1286 break;
1287 default:
1288 /*
1289 * Actually it can only be 8 now,
1290 * default is just to silence compiler warnings
1291 */
1292 case 8:
1293 dw = 2;
1294 bpp = 0;
1295 }
1296
1297 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1298 cicr4 |= CICR4_PCLK_EN;
1299 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1300 cicr4 |= CICR4_MCLK_EN;
1301 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1302 cicr4 |= CICR4_PCP;
1303 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1304 cicr4 |= CICR4_HSP;
1305 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1306 cicr4 |= CICR4_VSP;
1307
1308 cicr0 = __raw_readl(pcdev->base + CICR0);
1309 if (cicr0 & CICR0_ENB)
1310 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1311
1312 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1313
1314 switch (pixfmt) {
1315 case V4L2_PIX_FMT_YUV422P:
1316 pcdev->channels = 3;
1317 cicr1 |= CICR1_YCBCR_F;
1318 /*
1319 * Normally, pxa bus wants as input UYVY format. We allow all
1320 * reorderings of the YUV422 format, as no processing is done,
1321 * and the YUV stream is just passed through without any
1322 * transformation. Note that UYVY is the only format that
1323 * should be used if pxa framebuffer Overlay2 is used.
1324 */
1325 /* fall through */
1326 case V4L2_PIX_FMT_UYVY:
1327 case V4L2_PIX_FMT_VYUY:
1328 case V4L2_PIX_FMT_YUYV:
1329 case V4L2_PIX_FMT_YVYU:
1330 cicr1 |= CICR1_COLOR_SP_VAL(2);
1331 break;
1332 case V4L2_PIX_FMT_RGB555:
1333 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1334 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1335 break;
1336 case V4L2_PIX_FMT_RGB565:
1337 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1338 break;
1339 }
1340
1341 cicr2 = 0;
1342 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1343 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1344 cicr4 |= pcdev->mclk_divisor;
1345
1346 __raw_writel(cicr1, pcdev->base + CICR1);
1347 __raw_writel(cicr2, pcdev->base + CICR2);
1348 __raw_writel(cicr3, pcdev->base + CICR3);
1349 __raw_writel(cicr4, pcdev->base + CICR4);
1350
1351 /* CIF interrupts are not used, only DMA */
1352 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1353 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1354 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1355 __raw_writel(cicr0, pcdev->base + CICR0);
1356 }
1357
1358 /*
1359 * Videobuf2 section
1360 */
1361 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1362 {
1363 int i;
1364
1365 for (i = 0; i < 3 && buf->descs[i]; i++) {
1366 dmaengine_desc_free(buf->descs[i]);
1367 kfree(buf->sg[i]);
1368 buf->descs[i] = NULL;
1369 buf->sg[i] = NULL;
1370 buf->sg_len[i] = 0;
1371 buf->plane_sizes[i] = 0;
1372 }
1373 buf->nb_planes = 0;
1374 }
1375
1376 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1377 struct pxa_buffer *buf)
1378 {
1379 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1380 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1381 int nb_channels = pcdev->channels;
1382 int i, ret = 0;
1383 unsigned long size = vb2_plane_size(vb, 0);
1384
1385 switch (nb_channels) {
1386 case 1:
1387 buf->plane_sizes[0] = size;
1388 break;
1389 case 3:
1390 buf->plane_sizes[0] = size / 2;
1391 buf->plane_sizes[1] = size / 4;
1392 buf->plane_sizes[2] = size / 4;
1393 break;
1394 default:
1395 return -EINVAL;
1396 };
1397 buf->nb_planes = nb_channels;
1398
1399 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1400 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1401 if (ret < 0) {
1402 dev_err(pcdev_to_dev(pcdev),
1403 "sg_split failed: %d\n", ret);
1404 return ret;
1405 }
1406 for (i = 0; i < nb_channels; i++) {
1407 ret = pxa_init_dma_channel(pcdev, buf, i,
1408 buf->sg[i], buf->sg_len[i]);
1409 if (ret) {
1410 pxa_buffer_cleanup(buf);
1411 return ret;
1412 }
1413 }
1414 INIT_LIST_HEAD(&buf->queue);
1415
1416 return ret;
1417 }
1418
1419 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1420 {
1421 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1422 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1423
1424 dev_dbg(pcdev_to_dev(pcdev),
1425 "%s(vb=%p)\n", __func__, vb);
1426 pxa_buffer_cleanup(buf);
1427 }
1428
1429 static void pxac_vb2_queue(struct vb2_buffer *vb)
1430 {
1431 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1432 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1433
1434 dev_dbg(pcdev_to_dev(pcdev),
1435 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1436 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1437 pcdev->active);
1438
1439 list_add_tail(&buf->queue, &pcdev->capture);
1440
1441 pxa_dma_add_tail_buf(pcdev, buf);
1442 }
1443
1444 /*
1445 * Please check the DMA prepared buffer structure in :
1446 * Documentation/video4linux/pxa_camera.txt
1447 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1448 * modification while DMA chain is running will work anyway.
1449 */
1450 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1451 {
1452 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1453 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1454 int ret = 0;
1455
1456 switch (pcdev->channels) {
1457 case 1:
1458 case 3:
1459 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1460 break;
1461 default:
1462 return -EINVAL;
1463 }
1464
1465 dev_dbg(pcdev_to_dev(pcdev),
1466 "%s (vb=%p) nb_channels=%d size=%lu\n",
1467 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1468
1469 WARN_ON(!pcdev->current_fmt);
1470
1471 #ifdef DEBUG
1472 /*
1473 * This can be useful if you want to see if we actually fill
1474 * the buffer with something
1475 */
1476 for (i = 0; i < vb->num_planes; i++)
1477 memset((void *)vb2_plane_vaddr(vb, i),
1478 0xaa, vb2_get_plane_payload(vb, i));
1479 #endif
1480
1481 /*
1482 * I think, in buf_prepare you only have to protect global data,
1483 * the actual buffer is yours
1484 */
1485 buf->inwork = 0;
1486 pxa_videobuf_set_actdma(pcdev, buf);
1487
1488 return ret;
1489 }
1490
1491 static int pxac_vb2_init(struct vb2_buffer *vb)
1492 {
1493 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1494 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1495
1496 dev_dbg(pcdev_to_dev(pcdev),
1497 "%s(nb_channels=%d)\n",
1498 __func__, pcdev->channels);
1499
1500 return pxa_buffer_init(pcdev, buf);
1501 }
1502
1503 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1504 unsigned int *nbufs,
1505 unsigned int *num_planes, unsigned int sizes[],
1506 struct device *alloc_devs[])
1507 {
1508 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1509 int size = pcdev->current_pix.sizeimage;
1510
1511 dev_dbg(pcdev_to_dev(pcdev),
1512 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1513 __func__, vq, *nbufs, *num_planes, size);
1514 /*
1515 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1516 * format, even if there are 3 planes Y, U and V, we reply there is only
1517 * one plane, containing Y, U and V data, one after the other.
1518 */
1519 if (*num_planes)
1520 return sizes[0] < size ? -EINVAL : 0;
1521
1522 *num_planes = 1;
1523 switch (pcdev->channels) {
1524 case 1:
1525 case 3:
1526 sizes[0] = size;
1527 break;
1528 default:
1529 return -EINVAL;
1530 }
1531
1532 if (!*nbufs)
1533 *nbufs = 1;
1534
1535 return 0;
1536 }
1537
1538 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1539 {
1540 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1541
1542 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1543 __func__, count, pcdev->active);
1544
1545 pcdev->buf_sequence = 0;
1546 if (!pcdev->active)
1547 pxa_camera_start_capture(pcdev);
1548
1549 return 0;
1550 }
1551
1552 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1553 {
1554 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1555 struct pxa_buffer *buf, *tmp;
1556
1557 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1558 __func__, pcdev->active);
1559 pxa_camera_stop_capture(pcdev);
1560
1561 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1562 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1563 }
1564
1565 static const struct vb2_ops pxac_vb2_ops = {
1566 .queue_setup = pxac_vb2_queue_setup,
1567 .buf_init = pxac_vb2_init,
1568 .buf_prepare = pxac_vb2_prepare,
1569 .buf_queue = pxac_vb2_queue,
1570 .buf_cleanup = pxac_vb2_cleanup,
1571 .start_streaming = pxac_vb2_start_streaming,
1572 .stop_streaming = pxac_vb2_stop_streaming,
1573 .wait_prepare = vb2_ops_wait_prepare,
1574 .wait_finish = vb2_ops_wait_finish,
1575 };
1576
1577 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1578 {
1579 int ret;
1580 struct vb2_queue *vq = &pcdev->vb2_vq;
1581
1582 memset(vq, 0, sizeof(*vq));
1583 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1584 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1585 vq->drv_priv = pcdev;
1586 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1587 vq->buf_struct_size = sizeof(struct pxa_buffer);
1588 vq->dev = pcdev->v4l2_dev.dev;
1589
1590 vq->ops = &pxac_vb2_ops;
1591 vq->mem_ops = &vb2_dma_sg_memops;
1592 vq->lock = &pcdev->mlock;
1593
1594 ret = vb2_queue_init(vq);
1595 dev_dbg(pcdev_to_dev(pcdev),
1596 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1597
1598 return ret;
1599 }
1600
1601 /*
1602 * Video ioctls section
1603 */
1604 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1605 {
1606 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1607 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1608 unsigned long bus_flags, common_flags;
1609 int ret;
1610
1611 ret = test_platform_param(pcdev,
1612 pcdev->current_fmt->host_fmt->bits_per_sample,
1613 &bus_flags);
1614 if (ret < 0)
1615 return ret;
1616
1617 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1618 if (!ret) {
1619 common_flags = pxa_mbus_config_compatible(&cfg,
1620 bus_flags);
1621 if (!common_flags) {
1622 dev_warn(pcdev_to_dev(pcdev),
1623 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1624 cfg.flags, bus_flags);
1625 return -EINVAL;
1626 }
1627 } else if (ret != -ENOIOCTLCMD) {
1628 return ret;
1629 } else {
1630 common_flags = bus_flags;
1631 }
1632
1633 pcdev->channels = 1;
1634
1635 /* Make choises, based on platform preferences */
1636 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1637 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1638 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1639 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1640 else
1641 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1642 }
1643
1644 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1645 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1646 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1647 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1648 else
1649 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1650 }
1651
1652 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1653 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1654 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1655 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1656 else
1657 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1658 }
1659
1660 cfg.flags = common_flags;
1661 ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1662 if (ret < 0 && ret != -ENOIOCTLCMD) {
1663 dev_dbg(pcdev_to_dev(pcdev),
1664 "camera s_mbus_config(0x%lx) returned %d\n",
1665 common_flags, ret);
1666 return ret;
1667 }
1668
1669 pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1670
1671 return 0;
1672 }
1673
1674 static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1675 unsigned char buswidth)
1676 {
1677 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1678 unsigned long bus_flags, common_flags;
1679 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1680
1681 if (ret < 0)
1682 return ret;
1683
1684 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1685 if (!ret) {
1686 common_flags = pxa_mbus_config_compatible(&cfg,
1687 bus_flags);
1688 if (!common_flags) {
1689 dev_warn(pcdev_to_dev(pcdev),
1690 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1691 cfg.flags, bus_flags);
1692 return -EINVAL;
1693 }
1694 } else if (ret == -ENOIOCTLCMD) {
1695 ret = 0;
1696 }
1697
1698 return ret;
1699 }
1700
1701 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1702 {
1703 .fourcc = V4L2_PIX_FMT_YUV422P,
1704 .name = "Planar YUV422 16 bit",
1705 .bits_per_sample = 8,
1706 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1707 .order = PXA_MBUS_ORDER_LE,
1708 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1709 },
1710 };
1711
1712 /* This will be corrected as we get more formats */
1713 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1714 {
1715 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1716 (fmt->bits_per_sample == 8 &&
1717 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1718 (fmt->bits_per_sample > 8 &&
1719 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1720 }
1721
1722 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1723 unsigned int idx,
1724 struct pxa_camera_format_xlate *xlate)
1725 {
1726 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1727 int formats = 0, ret;
1728 struct v4l2_subdev_mbus_code_enum code = {
1729 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1730 .index = idx,
1731 };
1732 const struct pxa_mbus_pixelfmt *fmt;
1733
1734 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1735 if (ret < 0)
1736 /* No more formats */
1737 return 0;
1738
1739 fmt = pxa_mbus_get_fmtdesc(code.code);
1740 if (!fmt) {
1741 dev_err(pcdev_to_dev(pcdev),
1742 "Invalid format code #%u: %d\n", idx, code.code);
1743 return 0;
1744 }
1745
1746 /* This also checks support for the requested bits-per-sample */
1747 ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1748 if (ret < 0)
1749 return 0;
1750
1751 switch (code.code) {
1752 case MEDIA_BUS_FMT_UYVY8_2X8:
1753 formats++;
1754 if (xlate) {
1755 xlate->host_fmt = &pxa_camera_formats[0];
1756 xlate->code = code.code;
1757 xlate++;
1758 dev_dbg(pcdev_to_dev(pcdev),
1759 "Providing format %s using code %d\n",
1760 pxa_camera_formats[0].name, code.code);
1761 }
1762 /* fall through */
1763 case MEDIA_BUS_FMT_VYUY8_2X8:
1764 case MEDIA_BUS_FMT_YUYV8_2X8:
1765 case MEDIA_BUS_FMT_YVYU8_2X8:
1766 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1767 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1768 if (xlate)
1769 dev_dbg(pcdev_to_dev(pcdev),
1770 "Providing format %s packed\n",
1771 fmt->name);
1772 break;
1773 default:
1774 if (!pxa_camera_packing_supported(fmt))
1775 return 0;
1776 if (xlate)
1777 dev_dbg(pcdev_to_dev(pcdev),
1778 "Providing format %s in pass-through mode\n",
1779 fmt->name);
1780 break;
1781 }
1782
1783 /* Generic pass-through */
1784 formats++;
1785 if (xlate) {
1786 xlate->host_fmt = fmt;
1787 xlate->code = code.code;
1788 xlate++;
1789 }
1790
1791 return formats;
1792 }
1793
1794 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1795 {
1796 struct pxa_camera_format_xlate *xlate;
1797
1798 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1799 pxa_camera_get_formats);
1800 if (IS_ERR(xlate))
1801 return PTR_ERR(xlate);
1802
1803 pcdev->user_formats = xlate;
1804 return 0;
1805 }
1806
1807 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1808 {
1809 kfree(pcdev->user_formats);
1810 }
1811
1812 static int pxa_camera_check_frame(u32 width, u32 height)
1813 {
1814 /* limit to pxa hardware capabilities */
1815 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1816 (width & 0x01);
1817 }
1818
1819 #ifdef CONFIG_VIDEO_ADV_DEBUG
1820 static int pxac_vidioc_g_register(struct file *file, void *priv,
1821 struct v4l2_dbg_register *reg)
1822 {
1823 struct pxa_camera_dev *pcdev = video_drvdata(file);
1824
1825 if (reg->reg > CIBR2)
1826 return -ERANGE;
1827
1828 reg->val = __raw_readl(pcdev->base + reg->reg);
1829 reg->size = sizeof(__u32);
1830 return 0;
1831 }
1832
1833 static int pxac_vidioc_s_register(struct file *file, void *priv,
1834 const struct v4l2_dbg_register *reg)
1835 {
1836 struct pxa_camera_dev *pcdev = video_drvdata(file);
1837
1838 if (reg->reg > CIBR2)
1839 return -ERANGE;
1840 if (reg->size != sizeof(__u32))
1841 return -EINVAL;
1842 __raw_writel(reg->val, pcdev->base + reg->reg);
1843 return 0;
1844 }
1845 #endif
1846
1847 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1848 struct v4l2_fmtdesc *f)
1849 {
1850 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1851 const struct pxa_mbus_pixelfmt *format;
1852 unsigned int idx;
1853
1854 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1855 if (f->index >= idx)
1856 return -EINVAL;
1857
1858 format = pcdev->user_formats[f->index].host_fmt;
1859 f->pixelformat = format->fourcc;
1860 return 0;
1861 }
1862
1863 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1864 struct v4l2_format *f)
1865 {
1866 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1867 struct v4l2_pix_format *pix = &f->fmt.pix;
1868
1869 pix->width = pcdev->current_pix.width;
1870 pix->height = pcdev->current_pix.height;
1871 pix->bytesperline = pcdev->current_pix.bytesperline;
1872 pix->sizeimage = pcdev->current_pix.sizeimage;
1873 pix->field = pcdev->current_pix.field;
1874 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1875 pix->colorspace = pcdev->current_pix.colorspace;
1876 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1877 pcdev->current_fmt->host_fmt->fourcc);
1878 return 0;
1879 }
1880
1881 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1882 struct v4l2_format *f)
1883 {
1884 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1885 const struct pxa_camera_format_xlate *xlate;
1886 struct v4l2_pix_format *pix = &f->fmt.pix;
1887 struct v4l2_subdev_pad_config pad_cfg;
1888 struct v4l2_subdev_format format = {
1889 .which = V4L2_SUBDEV_FORMAT_TRY,
1890 };
1891 struct v4l2_mbus_framefmt *mf = &format.format;
1892 __u32 pixfmt = pix->pixelformat;
1893 int ret;
1894
1895 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1896 if (!xlate) {
1897 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1898 return -EINVAL;
1899 }
1900
1901 /*
1902 * Limit to pxa hardware capabilities. YUV422P planar format requires
1903 * images size to be a multiple of 16 bytes. If not, zeros will be
1904 * inserted between Y and U planes, and U and V planes, which violates
1905 * the YUV422P standard.
1906 */
1907 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1908 &pix->height, 32, 2048, 0,
1909 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1910
1911 v4l2_fill_mbus_format(mf, pix, xlate->code);
1912 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1913 if (ret < 0)
1914 return ret;
1915
1916 v4l2_fill_pix_format(pix, mf);
1917
1918 /* Only progressive video supported so far */
1919 switch (mf->field) {
1920 case V4L2_FIELD_ANY:
1921 case V4L2_FIELD_NONE:
1922 pix->field = V4L2_FIELD_NONE;
1923 break;
1924 default:
1925 /* TODO: support interlaced at least in pass-through mode */
1926 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1927 mf->field);
1928 return -EINVAL;
1929 }
1930
1931 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1932 if (ret < 0)
1933 return ret;
1934
1935 pix->bytesperline = ret;
1936 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1937 pix->height);
1938 if (ret < 0)
1939 return ret;
1940
1941 pix->sizeimage = ret;
1942 return 0;
1943 }
1944
1945 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1946 struct v4l2_format *f)
1947 {
1948 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1949 const struct pxa_camera_format_xlate *xlate;
1950 struct v4l2_pix_format *pix = &f->fmt.pix;
1951 struct v4l2_subdev_format format = {
1952 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1953 };
1954 unsigned long flags;
1955 int ret, is_busy;
1956
1957 dev_dbg(pcdev_to_dev(pcdev),
1958 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1959 pix->width, pix->height, pix->pixelformat);
1960
1961 spin_lock_irqsave(&pcdev->lock, flags);
1962 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1963 spin_unlock_irqrestore(&pcdev->lock, flags);
1964
1965 if (is_busy)
1966 return -EBUSY;
1967
1968 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1969 if (ret)
1970 return ret;
1971
1972 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1973 pix->pixelformat);
1974 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1975 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1976 if (ret < 0) {
1977 dev_warn(pcdev_to_dev(pcdev),
1978 "Failed to configure for format %x\n",
1979 pix->pixelformat);
1980 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1981 dev_warn(pcdev_to_dev(pcdev),
1982 "Camera driver produced an unsupported frame %dx%d\n",
1983 pix->width, pix->height);
1984 return -EINVAL;
1985 }
1986
1987 pcdev->current_fmt = xlate;
1988 pcdev->current_pix = *pix;
1989
1990 ret = pxa_camera_set_bus_param(pcdev);
1991 return ret;
1992 }
1993
1994 static int pxac_vidioc_querycap(struct file *file, void *priv,
1995 struct v4l2_capability *cap)
1996 {
1997 strlcpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1998 strlcpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1999 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
2000 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
2001 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
2002
2003 return 0;
2004 }
2005
2006 static int pxac_vidioc_enum_input(struct file *file, void *priv,
2007 struct v4l2_input *i)
2008 {
2009 if (i->index > 0)
2010 return -EINVAL;
2011
2012 i->type = V4L2_INPUT_TYPE_CAMERA;
2013 strlcpy(i->name, "Camera", sizeof(i->name));
2014
2015 return 0;
2016 }
2017
2018 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
2019 {
2020 *i = 0;
2021
2022 return 0;
2023 }
2024
2025 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
2026 {
2027 if (i > 0)
2028 return -EINVAL;
2029
2030 return 0;
2031 }
2032
2033 static int pxac_fops_camera_open(struct file *filp)
2034 {
2035 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2036 int ret;
2037
2038 mutex_lock(&pcdev->mlock);
2039 ret = v4l2_fh_open(filp);
2040 if (ret < 0)
2041 goto out;
2042
2043 ret = sensor_call(pcdev, core, s_power, 1);
2044 if (ret)
2045 v4l2_fh_release(filp);
2046 out:
2047 mutex_unlock(&pcdev->mlock);
2048 return ret;
2049 }
2050
2051 static int pxac_fops_camera_release(struct file *filp)
2052 {
2053 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2054 int ret;
2055
2056 ret = vb2_fop_release(filp);
2057 if (ret < 0)
2058 return ret;
2059
2060 mutex_lock(&pcdev->mlock);
2061 ret = sensor_call(pcdev, core, s_power, 0);
2062 mutex_unlock(&pcdev->mlock);
2063
2064 return ret;
2065 }
2066
2067 static const struct v4l2_file_operations pxa_camera_fops = {
2068 .owner = THIS_MODULE,
2069 .open = pxac_fops_camera_open,
2070 .release = pxac_fops_camera_release,
2071 .read = vb2_fop_read,
2072 .poll = vb2_fop_poll,
2073 .mmap = vb2_fop_mmap,
2074 .unlocked_ioctl = video_ioctl2,
2075 };
2076
2077 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2078 .vidioc_querycap = pxac_vidioc_querycap,
2079
2080 .vidioc_enum_input = pxac_vidioc_enum_input,
2081 .vidioc_g_input = pxac_vidioc_g_input,
2082 .vidioc_s_input = pxac_vidioc_s_input,
2083
2084 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2085 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2086 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2087 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2088
2089 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2090 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2091 .vidioc_querybuf = vb2_ioctl_querybuf,
2092 .vidioc_qbuf = vb2_ioctl_qbuf,
2093 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2094 .vidioc_expbuf = vb2_ioctl_expbuf,
2095 .vidioc_streamon = vb2_ioctl_streamon,
2096 .vidioc_streamoff = vb2_ioctl_streamoff,
2097 #ifdef CONFIG_VIDEO_ADV_DEBUG
2098 .vidioc_g_register = pxac_vidioc_g_register,
2099 .vidioc_s_register = pxac_vidioc_s_register,
2100 #endif
2101 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2102 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2103 };
2104
2105 static const struct v4l2_clk_ops pxa_camera_mclk_ops = {
2106 };
2107
2108 static const struct video_device pxa_camera_videodev_template = {
2109 .name = "pxa-camera",
2110 .minor = -1,
2111 .fops = &pxa_camera_fops,
2112 .ioctl_ops = &pxa_camera_ioctl_ops,
2113 .release = video_device_release_empty,
2114 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2115 };
2116
2117 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2118 struct v4l2_subdev *subdev,
2119 struct v4l2_async_subdev *asd)
2120 {
2121 int err;
2122 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2123 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2124 struct video_device *vdev = &pcdev->vdev;
2125 struct v4l2_pix_format *pix = &pcdev->current_pix;
2126 struct v4l2_subdev_format format = {
2127 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2128 };
2129 struct v4l2_mbus_framefmt *mf = &format.format;
2130
2131 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2132 __func__);
2133 mutex_lock(&pcdev->mlock);
2134 *vdev = pxa_camera_videodev_template;
2135 vdev->v4l2_dev = v4l2_dev;
2136 vdev->lock = &pcdev->mlock;
2137 pcdev->sensor = subdev;
2138 pcdev->vdev.queue = &pcdev->vb2_vq;
2139 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2140 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2141 video_set_drvdata(&pcdev->vdev, pcdev);
2142
2143 err = pxa_camera_build_formats(pcdev);
2144 if (err) {
2145 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2146 err);
2147 goto out;
2148 }
2149
2150 pcdev->current_fmt = pcdev->user_formats;
2151 pix->field = V4L2_FIELD_NONE;
2152 pix->width = DEFAULT_WIDTH;
2153 pix->height = DEFAULT_HEIGHT;
2154 pix->bytesperline =
2155 pxa_mbus_bytes_per_line(pix->width,
2156 pcdev->current_fmt->host_fmt);
2157 pix->sizeimage =
2158 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2159 pix->bytesperline, pix->height);
2160 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2161 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2162
2163 err = sensor_call(pcdev, core, s_power, 1);
2164 if (err)
2165 goto out;
2166
2167 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2168 if (err)
2169 goto out_sensor_poweroff;
2170
2171 v4l2_fill_pix_format(pix, mf);
2172 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2173 __func__, pix->colorspace, pix->pixelformat);
2174
2175 err = pxa_camera_init_videobuf2(pcdev);
2176 if (err)
2177 goto out_sensor_poweroff;
2178
2179 err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
2180 if (err) {
2181 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2182 pcdev->sensor = NULL;
2183 } else {
2184 dev_info(pcdev_to_dev(pcdev),
2185 "PXA Camera driver attached to camera %s\n",
2186 subdev->name);
2187 }
2188
2189 out_sensor_poweroff:
2190 err = sensor_call(pcdev, core, s_power, 0);
2191 out:
2192 mutex_unlock(&pcdev->mlock);
2193 return err;
2194 }
2195
2196 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2197 struct v4l2_subdev *subdev,
2198 struct v4l2_async_subdev *asd)
2199 {
2200 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2201
2202 mutex_lock(&pcdev->mlock);
2203 dev_info(pcdev_to_dev(pcdev),
2204 "PXA Camera driver detached from camera %s\n",
2205 subdev->name);
2206
2207 /* disable capture, disable interrupts */
2208 __raw_writel(0x3ff, pcdev->base + CICR0);
2209
2210 /* Stop DMA engine */
2211 pxa_dma_stop_channels(pcdev);
2212
2213 pxa_camera_destroy_formats(pcdev);
2214
2215 if (pcdev->mclk_clk) {
2216 v4l2_clk_unregister(pcdev->mclk_clk);
2217 pcdev->mclk_clk = NULL;
2218 }
2219
2220 video_unregister_device(&pcdev->vdev);
2221 pcdev->sensor = NULL;
2222
2223 mutex_unlock(&pcdev->mlock);
2224 }
2225
2226 static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2227 .bound = pxa_camera_sensor_bound,
2228 .unbind = pxa_camera_sensor_unbind,
2229 };
2230
2231 /*
2232 * Driver probe, remove, suspend and resume operations
2233 */
2234 static int pxa_camera_suspend(struct device *dev)
2235 {
2236 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2237 int i = 0, ret = 0;
2238
2239 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2240 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2241 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2242 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2243 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2244
2245 if (pcdev->sensor) {
2246 ret = sensor_call(pcdev, core, s_power, 0);
2247 if (ret == -ENOIOCTLCMD)
2248 ret = 0;
2249 }
2250
2251 return ret;
2252 }
2253
2254 static int pxa_camera_resume(struct device *dev)
2255 {
2256 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2257 int i = 0, ret = 0;
2258
2259 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2260 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2261 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2262 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2263 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2264
2265 if (pcdev->sensor) {
2266 ret = sensor_call(pcdev, core, s_power, 1);
2267 if (ret == -ENOIOCTLCMD)
2268 ret = 0;
2269 }
2270
2271 /* Restart frame capture if active buffer exists */
2272 if (!ret && pcdev->active)
2273 pxa_camera_start_capture(pcdev);
2274
2275 return ret;
2276 }
2277
2278 static int pxa_camera_pdata_from_dt(struct device *dev,
2279 struct pxa_camera_dev *pcdev,
2280 struct v4l2_async_subdev *asd)
2281 {
2282 u32 mclk_rate;
2283 struct device_node *remote, *np = dev->of_node;
2284 struct v4l2_fwnode_endpoint ep;
2285 int err = of_property_read_u32(np, "clock-frequency",
2286 &mclk_rate);
2287 if (!err) {
2288 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2289 pcdev->mclk = mclk_rate;
2290 }
2291
2292 np = of_graph_get_next_endpoint(np, NULL);
2293 if (!np) {
2294 dev_err(dev, "could not find endpoint\n");
2295 return -EINVAL;
2296 }
2297
2298 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2299 if (err) {
2300 dev_err(dev, "could not parse endpoint\n");
2301 goto out;
2302 }
2303
2304 switch (ep.bus.parallel.bus_width) {
2305 case 4:
2306 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2307 break;
2308 case 5:
2309 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2310 break;
2311 case 8:
2312 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2313 break;
2314 case 9:
2315 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2316 break;
2317 case 10:
2318 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2319 break;
2320 default:
2321 break;
2322 }
2323
2324 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2325 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2326 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2327 pcdev->platform_flags |= PXA_CAMERA_HSP;
2328 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2329 pcdev->platform_flags |= PXA_CAMERA_VSP;
2330 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2331 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2332 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2333 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2334
2335 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2336 remote = of_graph_get_remote_port(np);
2337 if (remote) {
2338 asd->match.fwnode = of_fwnode_handle(remote);
2339 of_node_put(remote);
2340 } else {
2341 dev_notice(dev, "no remote for %pOF\n", np);
2342 }
2343
2344 out:
2345 of_node_put(np);
2346
2347 return err;
2348 }
2349
2350 static int pxa_camera_probe(struct platform_device *pdev)
2351 {
2352 struct pxa_camera_dev *pcdev;
2353 struct resource *res;
2354 void __iomem *base;
2355 struct dma_slave_config config = {
2356 .src_addr_width = 0,
2357 .src_maxburst = 8,
2358 .direction = DMA_DEV_TO_MEM,
2359 };
2360 dma_cap_mask_t mask;
2361 struct pxad_param params;
2362 char clk_name[V4L2_CLK_NAME_SIZE];
2363 int irq;
2364 int err = 0, i;
2365
2366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2367 irq = platform_get_irq(pdev, 0);
2368 if (!res || irq < 0)
2369 return -ENODEV;
2370
2371 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2372 if (!pcdev) {
2373 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2374 return -ENOMEM;
2375 }
2376
2377 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2378 if (IS_ERR(pcdev->clk))
2379 return PTR_ERR(pcdev->clk);
2380
2381 pcdev->res = res;
2382
2383 pcdev->pdata = pdev->dev.platform_data;
2384 if (&pdev->dev.of_node && !pcdev->pdata) {
2385 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2386 } else {
2387 pcdev->platform_flags = pcdev->pdata->flags;
2388 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2389 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2390 pcdev->asd.match.i2c.adapter_id =
2391 pcdev->pdata->sensor_i2c_adapter_id;
2392 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2393 }
2394 if (err < 0)
2395 return err;
2396
2397 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2398 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2399 /*
2400 * Platform hasn't set available data widths. This is bad.
2401 * Warn and use a default.
2402 */
2403 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2404 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2405 }
2406 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2407 pcdev->width_flags = 1 << 7;
2408 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2409 pcdev->width_flags |= 1 << 8;
2410 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2411 pcdev->width_flags |= 1 << 9;
2412 if (!pcdev->mclk) {
2413 dev_warn(&pdev->dev,
2414 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2415 pcdev->mclk = 20000000;
2416 }
2417
2418 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2419
2420 INIT_LIST_HEAD(&pcdev->capture);
2421 spin_lock_init(&pcdev->lock);
2422 mutex_init(&pcdev->mlock);
2423
2424 /*
2425 * Request the regions.
2426 */
2427 base = devm_ioremap_resource(&pdev->dev, res);
2428 if (IS_ERR(base))
2429 return PTR_ERR(base);
2430
2431 pcdev->irq = irq;
2432 pcdev->base = base;
2433
2434 /* request dma */
2435 dma_cap_zero(mask);
2436 dma_cap_set(DMA_SLAVE, mask);
2437 dma_cap_set(DMA_PRIVATE, mask);
2438
2439 params.prio = 0;
2440 params.drcmr = 68;
2441 pcdev->dma_chans[0] =
2442 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2443 &params, &pdev->dev, "CI_Y");
2444 if (!pcdev->dma_chans[0]) {
2445 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2446 return -ENODEV;
2447 }
2448
2449 params.drcmr = 69;
2450 pcdev->dma_chans[1] =
2451 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2452 &params, &pdev->dev, "CI_U");
2453 if (!pcdev->dma_chans[1]) {
2454 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2455 err = -ENODEV;
2456 goto exit_free_dma_y;
2457 }
2458
2459 params.drcmr = 70;
2460 pcdev->dma_chans[2] =
2461 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2462 &params, &pdev->dev, "CI_V");
2463 if (!pcdev->dma_chans[2]) {
2464 dev_err(&pdev->dev, "Can't request DMA for V\n");
2465 err = -ENODEV;
2466 goto exit_free_dma_u;
2467 }
2468
2469 for (i = 0; i < 3; i++) {
2470 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2471 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2472 if (err < 0) {
2473 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2474 err);
2475 goto exit_free_dma;
2476 }
2477 }
2478
2479 /* request irq */
2480 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2481 PXA_CAM_DRV_NAME, pcdev);
2482 if (err) {
2483 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2484 goto exit_free_dma;
2485 }
2486
2487 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2488
2489 pxa_camera_activate(pcdev);
2490
2491 dev_set_drvdata(&pdev->dev, pcdev);
2492 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2493 if (err)
2494 goto exit_deactivate;
2495
2496 pcdev->asds[0] = &pcdev->asd;
2497 pcdev->notifier.subdevs = pcdev->asds;
2498 pcdev->notifier.num_subdevs = 1;
2499 pcdev->notifier.ops = &pxa_camera_sensor_ops;
2500
2501 if (!of_have_populated_dt())
2502 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2503
2504 err = pxa_camera_init_videobuf2(pcdev);
2505 if (err)
2506 goto exit_free_v4l2dev;
2507
2508 if (pcdev->mclk) {
2509 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2510 pcdev->asd.match.i2c.adapter_id,
2511 pcdev->asd.match.i2c.address);
2512
2513 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
2514 clk_name, NULL);
2515 if (IS_ERR(pcdev->mclk_clk)) {
2516 err = PTR_ERR(pcdev->mclk_clk);
2517 goto exit_free_v4l2dev;
2518 }
2519 }
2520
2521 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2522 if (err)
2523 goto exit_free_clk;
2524
2525 return 0;
2526 exit_free_clk:
2527 v4l2_clk_unregister(pcdev->mclk_clk);
2528 exit_free_v4l2dev:
2529 v4l2_device_unregister(&pcdev->v4l2_dev);
2530 exit_deactivate:
2531 pxa_camera_deactivate(pcdev);
2532 exit_free_dma:
2533 dma_release_channel(pcdev->dma_chans[2]);
2534 exit_free_dma_u:
2535 dma_release_channel(pcdev->dma_chans[1]);
2536 exit_free_dma_y:
2537 dma_release_channel(pcdev->dma_chans[0]);
2538 return err;
2539 }
2540
2541 static int pxa_camera_remove(struct platform_device *pdev)
2542 {
2543 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2544
2545 pxa_camera_deactivate(pcdev);
2546 dma_release_channel(pcdev->dma_chans[0]);
2547 dma_release_channel(pcdev->dma_chans[1]);
2548 dma_release_channel(pcdev->dma_chans[2]);
2549
2550 v4l2_async_notifier_unregister(&pcdev->notifier);
2551
2552 if (pcdev->mclk_clk) {
2553 v4l2_clk_unregister(pcdev->mclk_clk);
2554 pcdev->mclk_clk = NULL;
2555 }
2556
2557 v4l2_device_unregister(&pcdev->v4l2_dev);
2558
2559 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2560
2561 return 0;
2562 }
2563
2564 static const struct dev_pm_ops pxa_camera_pm = {
2565 .suspend = pxa_camera_suspend,
2566 .resume = pxa_camera_resume,
2567 };
2568
2569 static const struct of_device_id pxa_camera_of_match[] = {
2570 { .compatible = "marvell,pxa270-qci", },
2571 {},
2572 };
2573 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2574
2575 static struct platform_driver pxa_camera_driver = {
2576 .driver = {
2577 .name = PXA_CAM_DRV_NAME,
2578 .pm = &pxa_camera_pm,
2579 .of_match_table = of_match_ptr(pxa_camera_of_match),
2580 },
2581 .probe = pxa_camera_probe,
2582 .remove = pxa_camera_remove,
2583 };
2584
2585 module_platform_driver(pxa_camera_driver);
2586
2587 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
2588 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2589 MODULE_LICENSE("GPL");
2590 MODULE_VERSION(PXA_CAM_VERSION);
2591 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
CRIS linux kernel tree