drivers/media/platform/rockchip/rga/rga-hw.h

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author: Jacob Chen <jacob-chen@iotwrt.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #ifndef __RGA_HW_H__
  15 #define __RGA_HW_H__
  16
  17 #define RGA_CMDBUF_SIZE 0x20
  18
  19 /* Hardware limits */
  20 #define MAX_WIDTH 8192
  21 #define MAX_HEIGHT 8192
  22
  23 #define MIN_WIDTH 34
  24 #define MIN_HEIGHT 34
  25
  26 #define DEFAULT_WIDTH 100
  27 #define DEFAULT_HEIGHT 100
  28
  29 #define RGA_TIMEOUT 500
  30
  31 /* Registers address */
  32 #define RGA_SYS_CTRL 0x0000
  33 #define RGA_CMD_CTRL 0x0004
  34 #define RGA_CMD_BASE 0x0008
  35 #define RGA_INT 0x0010
  36 #define RGA_MMU_CTRL0 0x0014
  37 #define RGA_VERSION_INFO 0x0028
  38
  39 #define RGA_MODE_BASE_REG 0x0100
  40 #define RGA_MODE_MAX_REG 0x017C
  41
  42 #define RGA_MODE_CTRL 0x0100
  43 #define RGA_SRC_INFO 0x0104
  44 #define RGA_SRC_Y_RGB_BASE_ADDR 0x0108
  45 #define RGA_SRC_CB_BASE_ADDR 0x010c
  46 #define RGA_SRC_CR_BASE_ADDR 0x0110
  47 #define RGA_SRC1_RGB_BASE_ADDR 0x0114
  48 #define RGA_SRC_VIR_INFO 0x0118
  49 #define RGA_SRC_ACT_INFO 0x011c
  50 #define RGA_SRC_X_FACTOR 0x0120
  51 #define RGA_SRC_Y_FACTOR 0x0124
  52 #define RGA_SRC_BG_COLOR 0x0128
  53 #define RGA_SRC_FG_COLOR 0x012c
  54 #define RGA_SRC_TR_COLOR0 0x0130
  55 #define RGA_SRC_TR_COLOR1 0x0134
  56
  57 #define RGA_DST_INFO 0x0138
  58 #define RGA_DST_Y_RGB_BASE_ADDR 0x013c
  59 #define RGA_DST_CB_BASE_ADDR 0x0140
  60 #define RGA_DST_CR_BASE_ADDR 0x0144
  61 #define RGA_DST_VIR_INFO 0x0148
  62 #define RGA_DST_ACT_INFO 0x014c
  63
  64 #define RGA_ALPHA_CTRL0 0x0150
  65 #define RGA_ALPHA_CTRL1 0x0154
  66 #define RGA_FADING_CTRL 0x0158
  67 #define RGA_PAT_CON 0x015c
  68 #define RGA_ROP_CON0 0x0160
  69 #define RGA_ROP_CON1 0x0164
  70 #define RGA_MASK_BASE 0x0168
  71
  72 #define RGA_MMU_CTRL1 0x016C
  73 #define RGA_MMU_SRC_BASE 0x0170
  74 #define RGA_MMU_SRC1_BASE 0x0174
  75 #define RGA_MMU_DST_BASE 0x0178
  76
  77 /* Registers value */
  78 #define RGA_MODE_RENDER_BITBLT 0
  79 #define RGA_MODE_RENDER_COLOR_PALETTE 1
  80 #define RGA_MODE_RENDER_RECTANGLE_FILL 2
  81 #define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3
  82
  83 #define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0
  84 #define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1
  85
  86 #define RGA_MODE_CF_ROP4_SOLID 0
  87 #define RGA_MODE_CF_ROP4_PATTERN 1
  88
  89 #define RGA_COLOR_FMT_ABGR8888 0
  90 #define RGA_COLOR_FMT_XBGR8888 1
  91 #define RGA_COLOR_FMT_RGB888 2
  92 #define RGA_COLOR_FMT_BGR565 4
  93 #define RGA_COLOR_FMT_ABGR1555 5
  94 #define RGA_COLOR_FMT_ABGR4444 6
  95 #define RGA_COLOR_FMT_YUV422SP 8
  96 #define RGA_COLOR_FMT_YUV422P 9
  97 #define RGA_COLOR_FMT_YUV420SP 10
  98 #define RGA_COLOR_FMT_YUV420P 11
  99 /* SRC_COLOR Palette */
 100 #define RGA_COLOR_FMT_CP_1BPP 12
 101 #define RGA_COLOR_FMT_CP_2BPP 13
 102 #define RGA_COLOR_FMT_CP_4BPP 14
 103 #define RGA_COLOR_FMT_CP_8BPP 15
 104 #define RGA_COLOR_FMT_MASK 15
 105
 106 #define RGA_COLOR_NONE_SWAP 0
 107 #define RGA_COLOR_RB_SWAP 1
 108 #define RGA_COLOR_ALPHA_SWAP 2
 109 #define RGA_COLOR_UV_SWAP 4
 110
 111 #define RGA_SRC_CSC_MODE_BYPASS 0
 112 #define RGA_SRC_CSC_MODE_BT601_R0 1
 113 #define RGA_SRC_CSC_MODE_BT601_R1 2
 114 #define RGA_SRC_CSC_MODE_BT709_R0 3
 115 #define RGA_SRC_CSC_MODE_BT709_R1 4
 116
 117 #define RGA_SRC_ROT_MODE_0_DEGREE 0
 118 #define RGA_SRC_ROT_MODE_90_DEGREE 1
 119 #define RGA_SRC_ROT_MODE_180_DEGREE 2
 120 #define RGA_SRC_ROT_MODE_270_DEGREE 3
 121
 122 #define RGA_SRC_MIRR_MODE_NO 0
 123 #define RGA_SRC_MIRR_MODE_X 1
 124 #define RGA_SRC_MIRR_MODE_Y 2
 125 #define RGA_SRC_MIRR_MODE_X_Y 3
 126
 127 #define RGA_SRC_HSCL_MODE_NO 0
 128 #define RGA_SRC_HSCL_MODE_DOWN 1
 129 #define RGA_SRC_HSCL_MODE_UP 2
 130
 131 #define RGA_SRC_VSCL_MODE_NO 0
 132 #define RGA_SRC_VSCL_MODE_DOWN 1
 133 #define RGA_SRC_VSCL_MODE_UP 2
 134
 135 #define RGA_SRC_TRANS_ENABLE_R 1
 136 #define RGA_SRC_TRANS_ENABLE_G 2
 137 #define RGA_SRC_TRANS_ENABLE_B 4
 138 #define RGA_SRC_TRANS_ENABLE_A 8
 139
 140 #define RGA_SRC_BIC_COE_SELEC_CATROM 0
 141 #define RGA_SRC_BIC_COE_SELEC_MITCHELL 1
 142 #define RGA_SRC_BIC_COE_SELEC_HERMITE 2
 143 #define RGA_SRC_BIC_COE_SELEC_BSPLINE 3
 144
 145 #define RGA_DST_DITHER_MODE_888_TO_666 0
 146 #define RGA_DST_DITHER_MODE_888_TO_565 1
 147 #define RGA_DST_DITHER_MODE_888_TO_555 2
 148 #define RGA_DST_DITHER_MODE_888_TO_444 3
 149
 150 #define RGA_DST_CSC_MODE_BYPASS 0
 151 #define RGA_DST_CSC_MODE_BT601_R0 1
 152 #define RGA_DST_CSC_MODE_BT601_R1 2
 153 #define RGA_DST_CSC_MODE_BT709_R0 3
 154
 155 #define RGA_ALPHA_ROP_MODE_2 0
 156 #define RGA_ALPHA_ROP_MODE_3 1
 157 #define RGA_ALPHA_ROP_MODE_4 2
 158
 159 #define RGA_ALPHA_SELECT_ALPHA 0
 160 #define RGA_ALPHA_SELECT_ROP 1
 161
 162 #define RGA_ALPHA_MASK_BIG_ENDIAN 0
 163 #define RGA_ALPHA_MASK_LITTLE_ENDIAN 1
 164
 165 #define RGA_ALPHA_NORMAL 0
 166 #define RGA_ALPHA_REVERSE 1
 167
 168 #define RGA_ALPHA_BLEND_GLOBAL 0
 169 #define RGA_ALPHA_BLEND_NORMAL 1
 170 #define RGA_ALPHA_BLEND_MULTIPLY 2
 171
 172 #define RGA_ALPHA_CAL_CUT 0
 173 #define RGA_ALPHA_CAL_NORMAL 1
 174
 175 #define RGA_ALPHA_FACTOR_ZERO 0
 176 #define RGA_ALPHA_FACTOR_ONE 1
 177 #define RGA_ALPHA_FACTOR_OTHER 2
 178 #define RGA_ALPHA_FACTOR_OTHER_REVERSE 3
 179 #define RGA_ALPHA_FACTOR_SELF 4
 180
 181 #define RGA_ALPHA_COLOR_NORMAL 0
 182 #define RGA_ALPHA_COLOR_MULTIPLY_CAL 1
 183
 184 /* Registers union */
 185 union rga_mode_ctrl {
 186         unsigned int val;
 187         struct {
 188                 /* [0:2] */
 189                 unsigned int render:3;
 190                 /* [3:6] */
 191                 unsigned int bitblt:1;
 192                 unsigned int cf_rop4_pat:1;
 193                 unsigned int alpha_zero_key:1;
 194                 unsigned int gradient_sat:1;
 195                 /* [7:31] */
 196                 unsigned int reserved:25;
 197         } data;
 198 };
 199
 200 union rga_src_info {
 201         unsigned int val;
 202         struct {
 203                 /* [0:3] */
 204                 unsigned int format:4;
 205                 /* [4:7] */
 206                 unsigned int swap:3;
 207                 unsigned int cp_endian:1;
 208                 /* [8:17] */
 209                 unsigned int csc_mode:2;
 210                 unsigned int rot_mode:2;
 211                 unsigned int mir_mode:2;
 212                 unsigned int hscl_mode:2;
 213                 unsigned int vscl_mode:2;
 214                 /* [18:22] */
 215                 unsigned int trans_mode:1;
 216                 unsigned int trans_enable:4;
 217                 /* [23:25] */
 218                 unsigned int dither_up_en:1;
 219                 unsigned int bic_coe_sel:2;
 220                 /* [26:31] */
 221                 unsigned int reserved:6;
 222         } data;
 223 };
 224
 225 union rga_src_vir_info {
 226         unsigned int val;
 227         struct {
 228                 /* [0:15] */
 229                 unsigned int vir_width:15;
 230                 unsigned int reserved:1;
 231                 /* [16:25] */
 232                 unsigned int vir_stride:10;
 233                 /* [26:31] */
 234                 unsigned int reserved1:6;
 235         } data;
 236 };
 237
 238 union rga_src_act_info {
 239         unsigned int val;
 240         struct {
 241                 /* [0:15] */
 242                 unsigned int act_width:13;
 243                 unsigned int reserved:3;
 244                 /* [16:31] */
 245                 unsigned int act_height:13;
 246                 unsigned int reserved1:3;
 247         } data;
 248 };
 249
 250 union rga_src_x_factor {
 251         unsigned int val;
 252         struct {
 253                 /* [0:15] */
 254                 unsigned int down_scale_factor:16;
 255                 /* [16:31] */
 256                 unsigned int up_scale_factor:16;
 257         } data;
 258 };
 259
 260 union rga_src_y_factor {
 261         unsigned int val;
 262         struct {
 263                 /* [0:15] */
 264                 unsigned int down_scale_factor:16;
 265                 /* [16:31] */
 266                 unsigned int up_scale_factor:16;
 267         } data;
 268 };
 269
 270 /* Alpha / Red / Green / Blue */
 271 union rga_src_cp_gr_color {
 272         unsigned int val;
 273         struct {
 274                 /* [0:15] */
 275                 unsigned int gradient_x:16;
 276                 /* [16:31] */
 277                 unsigned int gradient_y:16;
 278         } data;
 279 };
 280
 281 union rga_src_transparency_color0 {
 282         unsigned int val;
 283         struct {
 284                 /* [0:7] */
 285                 unsigned int trans_rmin:8;
 286                 /* [8:15] */
 287                 unsigned int trans_gmin:8;
 288                 /* [16:23] */
 289                 unsigned int trans_bmin:8;
 290                 /* [24:31] */
 291                 unsigned int trans_amin:8;
 292         } data;
 293 };
 294
 295 union rga_src_transparency_color1 {
 296         unsigned int val;
 297         struct {
 298                 /* [0:7] */
 299                 unsigned int trans_rmax:8;
 300                 /* [8:15] */
 301                 unsigned int trans_gmax:8;
 302                 /* [16:23] */
 303                 unsigned int trans_bmax:8;
 304                 /* [24:31] */
 305                 unsigned int trans_amax:8;
 306         } data;
 307 };
 308
 309 union rga_dst_info {
 310         unsigned int val;
 311         struct {
 312                 /* [0:3] */
 313                 unsigned int format:4;
 314                 /* [4:6] */
 315                 unsigned int swap:3;
 316                 /* [7:9] */
 317                 unsigned int src1_format:3;
 318                 /* [10:11] */
 319                 unsigned int src1_swap:2;
 320                 /* [12:15] */
 321                 unsigned int dither_up_en:1;
 322                 unsigned int dither_down_en:1;
 323                 unsigned int dither_down_mode:2;
 324                 /* [16:18] */
 325                 unsigned int csc_mode:2;
 326                 unsigned int csc_clip:1;
 327                 /* [19:31] */
 328                 unsigned int reserved:13;
 329         } data;
 330 };
 331
 332 union rga_dst_vir_info {
 333         unsigned int val;
 334         struct {
 335                 /* [0:15] */
 336                 unsigned int vir_stride:15;
 337                 unsigned int reserved:1;
 338                 /* [16:31] */
 339                 unsigned int src1_vir_stride:15;
 340                 unsigned int reserved1:1;
 341         } data;
 342 };
 343
 344 union rga_dst_act_info {
 345         unsigned int val;
 346         struct {
 347                 /* [0:15] */
 348                 unsigned int act_width:12;
 349                 unsigned int reserved:4;
 350                 /* [16:31] */
 351                 unsigned int act_height:12;
 352                 unsigned int reserved1:4;
 353         } data;
 354 };
 355
 356 union rga_alpha_ctrl0 {
 357         unsigned int val;
 358         struct {
 359                 /* [0:3] */
 360                 unsigned int rop_en:1;
 361                 unsigned int rop_select:1;
 362                 unsigned int rop_mode:2;
 363                 /* [4:11] */
 364                 unsigned int src_fading_val:8;
 365                 /* [12:20] */
 366                 unsigned int dst_fading_val:8;
 367                 unsigned int mask_endian:1;
 368                 /* [21:31] */
 369                 unsigned int reserved:11;
 370         } data;
 371 };
 372
 373 union rga_alpha_ctrl1 {
 374         unsigned int val;
 375         struct {
 376                 /* [0:1] */
 377                 unsigned int dst_color_m0:1;
 378                 unsigned int src_color_m0:1;
 379                 /* [2:7] */
 380                 unsigned int dst_factor_m0:3;
 381                 unsigned int src_factor_m0:3;
 382                 /* [8:9] */
 383                 unsigned int dst_alpha_cal_m0:1;
 384                 unsigned int src_alpha_cal_m0:1;
 385                 /* [10:13] */
 386                 unsigned int dst_blend_m0:2;
 387                 unsigned int src_blend_m0:2;
 388                 /* [14:15] */
 389                 unsigned int dst_alpha_m0:1;
 390                 unsigned int src_alpha_m0:1;
 391                 /* [16:21] */
 392                 unsigned int dst_factor_m1:3;
 393                 unsigned int src_factor_m1:3;
 394                 /* [22:23] */
 395                 unsigned int dst_alpha_cal_m1:1;
 396                 unsigned int src_alpha_cal_m1:1;
 397                 /* [24:27] */
 398                 unsigned int dst_blend_m1:2;
 399                 unsigned int src_blend_m1:2;
 400                 /* [28:29] */
 401                 unsigned int dst_alpha_m1:1;
 402                 unsigned int src_alpha_m1:1;
 403                 /* [30:31] */
 404                 unsigned int reserved:2;
 405         } data;
 406 };
 407
 408 union rga_fading_ctrl {
 409         unsigned int val;
 410         struct {
 411                 /* [0:7] */
 412                 unsigned int fading_offset_r:8;
 413                 /* [8:15] */
 414                 unsigned int fading_offset_g:8;
 415                 /* [16:23] */
 416                 unsigned int fading_offset_b:8;
 417                 /* [24:31] */
 418                 unsigned int fading_en:1;
 419                 unsigned int reserved:7;
 420         } data;
 421 };
 422
 423 union rga_pat_con {
 424         unsigned int val;
 425         struct {
 426                 /* [0:7] */
 427                 unsigned int width:8;
 428                 /* [8:15] */
 429                 unsigned int height:8;
 430                 /* [16:23] */
 431                 unsigned int offset_x:8;
 432                 /* [24:31] */
 433                 unsigned int offset_y:8;
 434         } data;
 435 };
 436
 437 #endif