drivers/media/rc/fintek-cir.h

   1 /*
   2  * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
   3  *
   4  * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
   5  *
   6  * Special thanks to Fintek for providing hardware and spec sheets.
   7  * This driver is based upon the nuvoton, ite and ene drivers for
   8  * similar hardware.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of the
  13  * License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  */
  20
  21 #include <linux/spinlock.h>
  22 #include <linux/ioctl.h>
  23
  24 /* platform driver name to register */
  25 #define FINTEK_DRIVER_NAME      "fintek-cir"
  26 #define FINTEK_DESCRIPTION      "Fintek LPC SuperIO Consumer IR Transceiver"
  27 #define VENDOR_ID_FINTEK        0x1934
  28
  29
  30 /* debugging module parameter */
  31 static int debug;
  32
  33 #define fit_pr(level, text, ...) \
  34         printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
  35
  36 #define fit_dbg(text, ...) \
  37         if (debug) \
  38                 printk(KERN_DEBUG \
  39                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  40
  41 #define fit_dbg_verbose(text, ...) \
  42         if (debug > 1) \
  43                 printk(KERN_DEBUG \
  44                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  45
  46 #define fit_dbg_wake(text, ...) \
  47         if (debug > 2) \
  48                 printk(KERN_DEBUG \
  49                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  50
  51
  52 #define TX_BUF_LEN 256
  53 #define RX_BUF_LEN 32
  54
  55 struct fintek_dev {
  56         struct pnp_dev *pdev;
  57         struct rc_dev *rdev;
  58
  59         spinlock_t fintek_lock;
  60
  61         /* for rx */
  62         u8 buf[RX_BUF_LEN];
  63         unsigned int pkts;
  64
  65         struct {
  66                 spinlock_t lock;
  67                 u8 buf[TX_BUF_LEN];
  68                 unsigned int buf_count;
  69                 unsigned int cur_buf_num;
  70                 wait_queue_head_t queue;
  71         } tx;
  72
  73         /* Config register index/data port pair */
  74         u32 cr_ip;
  75         u32 cr_dp;
  76
  77         /* hardware I/O settings */
  78         unsigned long cir_addr;
  79         int cir_irq;
  80         int cir_port_len;
  81
  82         /* hardware id */
  83         u8 chip_major;
  84         u8 chip_minor;
  85         u16 chip_vendor;
  86         u8 logical_dev_cir;
  87
  88         /* hardware features */
  89         bool hw_learning_capable;
  90         bool hw_tx_capable;
  91
  92         /* rx settings */
  93         bool learning_enabled;
  94         bool carrier_detect_enabled;
  95
  96         enum {
  97                 CMD_HEADER = 0,
  98                 SUBCMD,
  99                 CMD_DATA,
 100                 PARSE_IRDATA,
 101         } parser_state;
 102
 103         u8 cmd, rem;
 104
 105         /* carrier period = 1 / frequency */
 106         u32 carrier;
 107 };
 108
 109 /* buffer packet constants, largely identical to mceusb.c */
 110 #define BUF_PULSE_BIT           0x80
 111 #define BUF_LEN_MASK            0x1f
 112 #define BUF_SAMPLE_MASK         0x7f
 113
 114 #define BUF_COMMAND_HEADER      0x9f
 115 #define BUF_COMMAND_MASK        0xe0
 116 #define BUF_COMMAND_NULL        0x00
 117 #define BUF_HW_CMD_HEADER       0xff
 118 #define BUF_CMD_G_REVISION      0x0b
 119 #define BUF_CMD_S_CARRIER       0x06
 120 #define BUF_CMD_S_TIMEOUT       0x0c
 121 #define BUF_CMD_SIG_END         0x01
 122 #define BUF_CMD_S_TXMASK        0x08
 123 #define BUF_CMD_S_RXSENSOR      0x14
 124 #define BUF_RSP_PULSE_COUNT     0x15
 125
 126 #define CIR_SAMPLE_PERIOD       50
 127
 128 /*
 129  * Configuration Register:
 130  *  Index Port
 131  *  Data Port
 132  */
 133 #define CR_INDEX_PORT           0x2e
 134 #define CR_DATA_PORT            0x2f
 135
 136 /* Possible alternate values, depends on how the chip is wired */
 137 #define CR_INDEX_PORT2          0x4e
 138 #define CR_DATA_PORT2           0x4f
 139
 140 /*
 141  * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is
 142  * active. 1 = 0x4e, 0 = 0x2e
 143  */
 144 #define PORT_SEL_PORT_4E_EN     0x10
 145
 146 /* Extended Function Mode enable/disable magic values */
 147 #define CONFIG_REG_ENABLE       0x87
 148 #define CONFIG_REG_DISABLE      0xaa
 149
 150 /* Chip IDs found in CR_CHIP_ID_{HI,LO} */
 151 #define CHIP_ID_HIGH_F71809U    0x04
 152 #define CHIP_ID_LOW_F71809U     0x08
 153
 154 /*
 155  * Global control regs we need to care about:
 156  *      Global Control                  def.
 157  *      Register name           addr    val. */
 158 #define GCR_SOFTWARE_RESET      0x02 /* 0x00 */
 159 #define GCR_LOGICAL_DEV_NO      0x07 /* 0x00 */
 160 #define GCR_CHIP_ID_HI          0x20 /* 0x04 */
 161 #define GCR_CHIP_ID_LO          0x21 /* 0x08 */
 162 #define GCR_VENDOR_ID_HI        0x23 /* 0x19 */
 163 #define GCR_VENDOR_ID_LO        0x24 /* 0x34 */
 164 #define GCR_CONFIG_PORT_SEL     0x25 /* 0x01 */
 165 #define GCR_KBMOUSE_WAKEUP      0x27
 166
 167 #define LOGICAL_DEV_DISABLE     0x00
 168 #define LOGICAL_DEV_ENABLE      0x01
 169
 170 /* Logical device number of the CIR function */
 171 #define LOGICAL_DEV_CIR_REV1    0x05
 172 #define LOGICAL_DEV_CIR_REV2    0x08
 173
 174 /* CIR Logical Device (LDN 0x08) config registers */
 175 #define CIR_CR_COMMAND_INDEX    0x04
 176 #define CIR_CR_IRCS             0x05 /* Before host writes command to IR, host
 177                                         must set to 1. When host finshes write
 178                                         command to IR, host must clear to 0. */
 179 #define CIR_CR_COMMAND_DATA     0x06 /* Host read or write comand data */
 180 #define CIR_CR_CLASS            0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx,
 181                                         0x33 = rx + 1 tx */
 182 #define CIR_CR_DEV_EN           0x30 /* bit0 = 1 enables CIR */
 183 #define CIR_CR_BASE_ADDR_HI     0x60 /* MSB of CIR IO base addr */
 184 #define CIR_CR_BASE_ADDR_LO     0x61 /* LSB of CIR IO base addr */
 185 #define CIR_CR_IRQ_SEL          0x70 /* bits3-0 store CIR IRQ */
 186 #define CIR_CR_PSOUT_STATUS     0xf1
 187 #define CIR_CR_WAKE_KEY3_ADDR   0xf8
 188 #define CIR_CR_WAKE_KEY3_CODE   0xf9
 189 #define CIR_CR_WAKE_KEY3_DC     0xfa
 190 #define CIR_CR_WAKE_CONTROL     0xfb
 191 #define CIR_CR_WAKE_KEY12_ADDR  0xfc
 192 #define CIR_CR_WAKE_KEY4_ADDR   0xfd
 193 #define CIR_CR_WAKE_KEY5_ADDR   0xfe
 194
 195 #define CLASS_RX_ONLY           0xff
 196 #define CLASS_RX_2TX            0x66
 197 #define CLASS_RX_1TX            0x33
 198
 199 /* CIR device registers */
 200 #define CIR_STATUS              0x00
 201 #define CIR_RX_DATA             0x01
 202 #define CIR_TX_CONTROL          0x02
 203 #define CIR_TX_DATA             0x03
 204 #define CIR_CONTROL             0x04
 205
 206 /* Bits to enable CIR wake */
 207 #define LOGICAL_DEV_ACPI        0x01
 208 #define LDEV_ACPI_WAKE_EN_REG   0xe8
 209 #define ACPI_WAKE_EN_CIR_BIT    0x04
 210
 211 #define LDEV_ACPI_PME_EN_REG    0xf0
 212 #define LDEV_ACPI_PME_CLR_REG   0xf1
 213 #define ACPI_PME_CIR_BIT        0x02
 214
 215 #define LDEV_ACPI_STATE_REG     0xf4
 216 #define ACPI_STATE_CIR_BIT      0x20
 217
 218 /*
 219  * CIR status register (0x00):
 220  *   7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable)
 221  *   3 - TX_FINISH (1 when TX finished, write 1 to clear)
 222  *   2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear)
 223  *   1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear)
 224  *   0 - RX_RECEIVE (1 on RX receive, write 1 to clear)
 225  */
 226 #define CIR_STATUS_IRQ_EN       0x80
 227 #define CIR_STATUS_TX_FINISH    0x08
 228 #define CIR_STATUS_TX_UNDERRUN  0x04
 229 #define CIR_STATUS_RX_TIMEOUT   0x02
 230 #define CIR_STATUS_RX_RECEIVE   0x01
 231 #define CIR_STATUS_IRQ_MASK     0x0f
 232
 233 /*
 234  * CIR TX control register (0x02):
 235  *   7 - TX_START (1 to indicate TX start, auto-cleared when done)
 236  *   6 - TX_END (1 to indicate TX data written to TX fifo)
 237  */
 238 #define CIR_TX_CONTROL_TX_START 0x80
 239 #define CIR_TX_CONTROL_TX_END   0x40
 240