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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / mtd / nand / mtk_ecc.c
blob40d86a861a70de669ad0acf34898fb28820d65dd
1 /*
2 * MTK ECC controller driver.
3 * Copyright (C) 2016 MediaTek Inc.
4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/module.h>
22 #include <linux/iopoll.h>
23 #include <linux/of.h>
24 #include <linux/of_platform.h>
25 #include <linux/mutex.h>
26
27 #include "mtk_ecc.h"
28
29 #define ECC_IDLE_MASK BIT(0)
30 #define ECC_IRQ_EN BIT(0)
31 #define ECC_PG_IRQ_SEL BIT(1)
32 #define ECC_OP_ENABLE (1)
33 #define ECC_OP_DISABLE (0)
34
35 #define ECC_ENCCON (0x00)
36 #define ECC_ENCCNFG (0x04)
37 #define ECC_MS_SHIFT (16)
38 #define ECC_ENCDIADDR (0x08)
39 #define ECC_ENCIDLE (0x0C)
40 #define ECC_DECCON (0x100)
41 #define ECC_DECCNFG (0x104)
42 #define DEC_EMPTY_EN BIT(31)
43 #define DEC_CNFG_CORRECT (0x3 << 12)
44 #define ECC_DECIDLE (0x10C)
45 #define ECC_DECENUM0 (0x114)
46
47 #define ECC_TIMEOUT (500000)
48
49 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
50 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
51
52 struct mtk_ecc_caps {
53 u32 err_mask;
54 const u8 *ecc_strength;
55 const u32 *ecc_regs;
56 u8 num_ecc_strength;
57 u8 ecc_mode_shift;
58 u32 parity_bits;
59 int pg_irq_sel;
60 };
61
62 struct mtk_ecc {
63 struct device *dev;
64 const struct mtk_ecc_caps *caps;
65 void __iomem *regs;
66 struct clk *clk;
67
68 struct completion done;
69 struct mutex lock;
70 u32 sectors;
71
72 u8 *eccdata;
73 };
74
75 /* ecc strength that each IP supports */
76 static const u8 ecc_strength_mt2701[] = {
77 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
78 40, 44, 48, 52, 56, 60
79 };
80
81 static const u8 ecc_strength_mt2712[] = {
82 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
83 40, 44, 48, 52, 56, 60, 68, 72, 80
84 };
85
86 static const u8 ecc_strength_mt7622[] = {
87 4, 6, 8, 10, 12, 14, 16
88 };
89
90 enum mtk_ecc_regs {
91 ECC_ENCPAR00,
92 ECC_ENCIRQ_EN,
93 ECC_ENCIRQ_STA,
94 ECC_DECDONE,
95 ECC_DECIRQ_EN,
96 ECC_DECIRQ_STA,
97 };
98
99 static int mt2701_ecc_regs[] = {
100 [ECC_ENCPAR00] = 0x10,
101 [ECC_ENCIRQ_EN] = 0x80,
102 [ECC_ENCIRQ_STA] = 0x84,
103 [ECC_DECDONE] = 0x124,
104 [ECC_DECIRQ_EN] = 0x200,
105 [ECC_DECIRQ_STA] = 0x204,
106 };
107
108 static int mt2712_ecc_regs[] = {
109 [ECC_ENCPAR00] = 0x300,
110 [ECC_ENCIRQ_EN] = 0x80,
111 [ECC_ENCIRQ_STA] = 0x84,
112 [ECC_DECDONE] = 0x124,
113 [ECC_DECIRQ_EN] = 0x200,
114 [ECC_DECIRQ_STA] = 0x204,
115 };
116
117 static int mt7622_ecc_regs[] = {
118 [ECC_ENCPAR00] = 0x10,
119 [ECC_ENCIRQ_EN] = 0x30,
120 [ECC_ENCIRQ_STA] = 0x34,
121 [ECC_DECDONE] = 0x11c,
122 [ECC_DECIRQ_EN] = 0x140,
123 [ECC_DECIRQ_STA] = 0x144,
124 };
125
126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
127 enum mtk_ecc_operation op)
128 {
129 struct device *dev = ecc->dev;
130 u32 val;
131 int ret;
132
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
134 val & ECC_IDLE_MASK,
135 10, ECC_TIMEOUT);
136 if (ret)
137 dev_warn(dev, "%s NOT idle\n",
138 op == ECC_ENCODE ? "encoder" : "decoder");
139 }
140
141 static irqreturn_t mtk_ecc_irq(int irq, void *id)
142 {
143 struct mtk_ecc *ecc = id;
144 u32 dec, enc;
145
146 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
147 & ECC_IRQ_EN;
148 if (dec) {
149 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
150 if (dec & ecc->sectors) {
151 /*
152 * Clear decode IRQ status once again to ensure that
153 * there will be no extra IRQ.
154 */
155 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
156 ecc->sectors = 0;
157 complete(&ecc->done);
158 } else {
159 return IRQ_HANDLED;
160 }
161 } else {
162 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
163 & ECC_IRQ_EN;
164 if (enc)
165 complete(&ecc->done);
166 else
167 return IRQ_NONE;
168 }
169
170 return IRQ_HANDLED;
171 }
172
173 static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
174 {
175 u32 ecc_bit, dec_sz, enc_sz;
176 u32 reg, i;
177
178 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
179 if (ecc->caps->ecc_strength[i] == config->strength)
180 break;
181 }
182
183 if (i == ecc->caps->num_ecc_strength) {
184 dev_err(ecc->dev, "invalid ecc strength %d\n",
185 config->strength);
186 return -EINVAL;
187 }
188
189 ecc_bit = i;
190
191 if (config->op == ECC_ENCODE) {
192 /* configure ECC encoder (in bits) */
193 enc_sz = config->len << 3;
194
195 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
196 reg |= (enc_sz << ECC_MS_SHIFT);
197 writel(reg, ecc->regs + ECC_ENCCNFG);
198
199 if (config->mode != ECC_NFI_MODE)
200 writel(lower_32_bits(config->addr),
201 ecc->regs + ECC_ENCDIADDR);
202
203 } else {
204 /* configure ECC decoder (in bits) */
205 dec_sz = (config->len << 3) +
206 config->strength * ecc->caps->parity_bits;
207
208 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
209 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
210 reg |= DEC_EMPTY_EN;
211 writel(reg, ecc->regs + ECC_DECCNFG);
212
213 if (config->sectors)
214 ecc->sectors = 1 << (config->sectors - 1);
215 }
216
217 return 0;
218 }
219
220 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
221 int sectors)
222 {
223 u32 offset, i, err;
224 u32 bitflips = 0;
225
226 stats->corrected = 0;
227 stats->failed = 0;
228
229 for (i = 0; i < sectors; i++) {
230 offset = (i >> 2) << 2;
231 err = readl(ecc->regs + ECC_DECENUM0 + offset);
232 err = err >> ((i % 4) * 8);
233 err &= ecc->caps->err_mask;
234 if (err == ecc->caps->err_mask) {
235 /* uncorrectable errors */
236 stats->failed++;
237 continue;
238 }
239
240 stats->corrected += err;
241 bitflips = max_t(u32, bitflips, err);
242 }
243
244 stats->bitflips = bitflips;
245 }
246 EXPORT_SYMBOL(mtk_ecc_get_stats);
247
248 void mtk_ecc_release(struct mtk_ecc *ecc)
249 {
250 clk_disable_unprepare(ecc->clk);
251 put_device(ecc->dev);
252 }
253 EXPORT_SYMBOL(mtk_ecc_release);
254
255 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
256 {
257 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
258 writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
259
260 mtk_ecc_wait_idle(ecc, ECC_DECODE);
261 writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
262 }
263
264 static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
265 {
266 struct platform_device *pdev;
267 struct mtk_ecc *ecc;
268
269 pdev = of_find_device_by_node(np);
270 if (!pdev || !platform_get_drvdata(pdev))
271 return ERR_PTR(-EPROBE_DEFER);
272
273 get_device(&pdev->dev);
274 ecc = platform_get_drvdata(pdev);
275 clk_prepare_enable(ecc->clk);
276 mtk_ecc_hw_init(ecc);
277
278 return ecc;
279 }
280
281 struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
282 {
283 struct mtk_ecc *ecc = NULL;
284 struct device_node *np;
285
286 np = of_parse_phandle(of_node, "ecc-engine", 0);
287 if (np) {
288 ecc = mtk_ecc_get(np);
289 of_node_put(np);
290 }
291
292 return ecc;
293 }
294 EXPORT_SYMBOL(of_mtk_ecc_get);
295
296 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
297 {
298 enum mtk_ecc_operation op = config->op;
299 u16 reg_val;
300 int ret;
301
302 ret = mutex_lock_interruptible(&ecc->lock);
303 if (ret) {
304 dev_err(ecc->dev, "interrupted when attempting to lock\n");
305 return ret;
306 }
307
308 mtk_ecc_wait_idle(ecc, op);
309
310 ret = mtk_ecc_config(ecc, config);
311 if (ret) {
312 mutex_unlock(&ecc->lock);
313 return ret;
314 }
315
316 if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
317 init_completion(&ecc->done);
318 reg_val = ECC_IRQ_EN;
319 /*
320 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
321 * means this chip can only generate one ecc irq during page
322 * read / write. If is 0, generate one ecc irq each ecc step.
323 */
324 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
325 reg_val |= ECC_PG_IRQ_SEL;
326 if (op == ECC_ENCODE)
327 writew(reg_val, ecc->regs +
328 ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
329 else
330 writew(reg_val, ecc->regs +
331 ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
332 }
333
334 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
335
336 return 0;
337 }
338 EXPORT_SYMBOL(mtk_ecc_enable);
339
340 void mtk_ecc_disable(struct mtk_ecc *ecc)
341 {
342 enum mtk_ecc_operation op = ECC_ENCODE;
343
344 /* find out the running operation */
345 if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
346 op = ECC_DECODE;
347
348 /* disable it */
349 mtk_ecc_wait_idle(ecc, op);
350 if (op == ECC_DECODE) {
351 /*
352 * Clear decode IRQ status in case there is a timeout to wait
353 * decode IRQ.
354 */
355 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
356 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
357 } else {
358 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
359 }
360
361 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
362
363 mutex_unlock(&ecc->lock);
364 }
365 EXPORT_SYMBOL(mtk_ecc_disable);
366
367 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
368 {
369 int ret;
370
371 ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
372 if (!ret) {
373 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
374 (op == ECC_ENCODE) ? "encoder" : "decoder");
375 return -ETIMEDOUT;
376 }
377
378 return 0;
379 }
380 EXPORT_SYMBOL(mtk_ecc_wait_done);
381
382 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
383 u8 *data, u32 bytes)
384 {
385 dma_addr_t addr;
386 u32 len;
387 int ret;
388
389 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
390 ret = dma_mapping_error(ecc->dev, addr);
391 if (ret) {
392 dev_err(ecc->dev, "dma mapping error\n");
393 return -EINVAL;
394 }
395
396 config->op = ECC_ENCODE;
397 config->addr = addr;
398 ret = mtk_ecc_enable(ecc, config);
399 if (ret) {
400 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
401 return ret;
402 }
403
404 ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
405 if (ret)
406 goto timeout;
407
408 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
409
410 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
411 len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
412
413 /* write the parity bytes generated by the ECC back to temp buffer */
414 __ioread32_copy(ecc->eccdata,
415 ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
416 round_up(len, 4));
417
418 /* copy into possibly unaligned OOB region with actual length */
419 memcpy(data + bytes, ecc->eccdata, len);
420 timeout:
421
422 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
423 mtk_ecc_disable(ecc);
424
425 return ret;
426 }
427 EXPORT_SYMBOL(mtk_ecc_encode);
428
429 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
430 {
431 const u8 *ecc_strength = ecc->caps->ecc_strength;
432 int i;
433
434 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
435 if (*p <= ecc_strength[i]) {
436 if (!i)
437 *p = ecc_strength[i];
438 else if (*p != ecc_strength[i])
439 *p = ecc_strength[i - 1];
440 return;
441 }
442 }
443
444 *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
445 }
446 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
447
448 unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
449 {
450 return ecc->caps->parity_bits;
451 }
452 EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
453
454 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
455 .err_mask = 0x3f,
456 .ecc_strength = ecc_strength_mt2701,
457 .ecc_regs = mt2701_ecc_regs,
458 .num_ecc_strength = 20,
459 .ecc_mode_shift = 5,
460 .parity_bits = 14,
461 .pg_irq_sel = 0,
462 };
463
464 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
465 .err_mask = 0x7f,
466 .ecc_strength = ecc_strength_mt2712,
467 .ecc_regs = mt2712_ecc_regs,
468 .num_ecc_strength = 23,
469 .ecc_mode_shift = 5,
470 .parity_bits = 14,
471 .pg_irq_sel = 1,
472 };
473
474 static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
475 .err_mask = 0x3f,
476 .ecc_strength = ecc_strength_mt7622,
477 .ecc_regs = mt7622_ecc_regs,
478 .num_ecc_strength = 7,
479 .ecc_mode_shift = 4,
480 .parity_bits = 13,
481 .pg_irq_sel = 0,
482 };
483
484 static const struct of_device_id mtk_ecc_dt_match[] = {
485 {
486 .compatible = "mediatek,mt2701-ecc",
487 .data = &mtk_ecc_caps_mt2701,
488 }, {
489 .compatible = "mediatek,mt2712-ecc",
490 .data = &mtk_ecc_caps_mt2712,
491 }, {
492 .compatible = "mediatek,mt7622-ecc",
493 .data = &mtk_ecc_caps_mt7622,
494 },
495 {},
496 };
497
498 static int mtk_ecc_probe(struct platform_device *pdev)
499 {
500 struct device *dev = &pdev->dev;
501 struct mtk_ecc *ecc;
502 struct resource *res;
503 const struct of_device_id *of_ecc_id = NULL;
504 u32 max_eccdata_size;
505 int irq, ret;
506
507 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
508 if (!ecc)
509 return -ENOMEM;
510
511 of_ecc_id = of_match_device(mtk_ecc_dt_match, &pdev->dev);
512 if (!of_ecc_id)
513 return -ENODEV;
514
515 ecc->caps = of_ecc_id->data;
516
517 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
518 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
519 max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
520 max_eccdata_size = round_up(max_eccdata_size, 4);
521 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
522 if (!ecc->eccdata)
523 return -ENOMEM;
524
525 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
526 ecc->regs = devm_ioremap_resource(dev, res);
527 if (IS_ERR(ecc->regs)) {
528 dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
529 return PTR_ERR(ecc->regs);
530 }
531
532 ecc->clk = devm_clk_get(dev, NULL);
533 if (IS_ERR(ecc->clk)) {
534 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
535 return PTR_ERR(ecc->clk);
536 }
537
538 irq = platform_get_irq(pdev, 0);
539 if (irq < 0) {
540 dev_err(dev, "failed to get irq: %d\n", irq);
541 return irq;
542 }
543
544 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
545 if (ret) {
546 dev_err(dev, "failed to set DMA mask\n");
547 return ret;
548 }
549
550 ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
551 if (ret) {
552 dev_err(dev, "failed to request irq\n");
553 return -EINVAL;
554 }
555
556 ecc->dev = dev;
557 mutex_init(&ecc->lock);
558 platform_set_drvdata(pdev, ecc);
559 dev_info(dev, "probed\n");
560
561 return 0;
562 }
563
564 #ifdef CONFIG_PM_SLEEP
565 static int mtk_ecc_suspend(struct device *dev)
566 {
567 struct mtk_ecc *ecc = dev_get_drvdata(dev);
568
569 clk_disable_unprepare(ecc->clk);
570
571 return 0;
572 }
573
574 static int mtk_ecc_resume(struct device *dev)
575 {
576 struct mtk_ecc *ecc = dev_get_drvdata(dev);
577 int ret;
578
579 ret = clk_prepare_enable(ecc->clk);
580 if (ret) {
581 dev_err(dev, "failed to enable clk\n");
582 return ret;
583 }
584
585 return 0;
586 }
587
588 static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
589 #endif
590
591 MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
592
593 static struct platform_driver mtk_ecc_driver = {
594 .probe = mtk_ecc_probe,
595 .driver = {
596 .name = "mtk-ecc",
597 .of_match_table = of_match_ptr(mtk_ecc_dt_match),
598 #ifdef CONFIG_PM_SLEEP
599 .pm = &mtk_ecc_pm_ops,
600 #endif
601 },
602 };
603
604 module_platform_driver(mtk_ecc_driver);
605
606 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
607 MODULE_DESCRIPTION("MTK Nand ECC Driver");
608 MODULE_LICENSE("GPL");
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