drivers/net/wireless/intel/iwlegacy/3945.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #ifndef __il_3945_h__
  28 #define __il_3945_h__
  29
  30 #include <linux/pci.h>          /* for struct pci_device_id */
  31 #include <linux/kernel.h>
  32 #include <net/ieee80211_radiotap.h>
  33
  34 /* Hardware specific file defines the PCI IDs table for that hardware module */
  35 extern const struct pci_device_id il3945_hw_card_ids[];
  36
  37 #include "common.h"
  38
  39 extern const struct il_ops il3945_ops;
  40
  41 /* Highest firmware API version supported */
  42 #define IL3945_UCODE_API_MAX 2
  43
  44 /* Lowest firmware API version supported */
  45 #define IL3945_UCODE_API_MIN 1
  46
  47 #define IL3945_FW_PRE   "iwlwifi-3945-"
  48 #define _IL3945_MODULE_FIRMWARE(api) IL3945_FW_PRE #api ".ucode"
  49 #define IL3945_MODULE_FIRMWARE(api) _IL3945_MODULE_FIRMWARE(api)
  50
  51 /* Default noise level to report when noise measurement is not available.
  52  *   This may be because we're:
  53  *   1)  Not associated (4965, no beacon stats being sent to driver)
  54  *   2)  Scanning (noise measurement does not apply to associated channel)
  55  *   3)  Receiving CCK (3945 delivers noise info only for OFDM frames)
  56  * Use default noise value of -127 ... this is below the range of measurable
  57  *   Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
  58  *   Also, -127 works better than 0 when averaging frames with/without
  59  *   noise info (e.g. averaging might be done in app); measured dBm values are
  60  *   always negative ... using a negative value as the default keeps all
  61  *   averages within an s8's (used in some apps) range of negative values. */
  62 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
  63
  64 /* Module parameters accessible from iwl-*.c */
  65 extern struct il_mod_params il3945_mod_params;
  66
  67 struct il3945_rate_scale_data {
  68         u64 data;
  69         s32 success_counter;
  70         s32 success_ratio;
  71         s32 counter;
  72         s32 average_tpt;
  73         unsigned long stamp;
  74 };
  75
  76 struct il3945_rs_sta {
  77         spinlock_t lock;
  78         struct il_priv *il;
  79         s32 *expected_tpt;
  80         unsigned long last_partial_flush;
  81         unsigned long last_flush;
  82         u32 flush_time;
  83         u32 last_tx_packets;
  84         u32 tx_packets;
  85         u8 tgg;
  86         u8 flush_pending;
  87         u8 start_rate;
  88         struct timer_list rate_scale_flush;
  89         struct il3945_rate_scale_data win[RATE_COUNT_3945];
  90 #ifdef CONFIG_MAC80211_DEBUGFS
  91         struct dentry *rs_sta_dbgfs_stats_table_file;
  92 #endif
  93
  94         /* used to be in sta_info */
  95         int last_txrate_idx;
  96 };
  97
  98 /*
  99  * The common struct MUST be first because it is shared between
 100  * 3945 and 4965!
 101  */
 102 struct il3945_sta_priv {
 103         struct il_station_priv_common common;
 104         struct il3945_rs_sta rs_sta;
 105 };
 106
 107 enum il3945_antenna {
 108         IL_ANTENNA_DIVERSITY,
 109         IL_ANTENNA_MAIN,
 110         IL_ANTENNA_AUX
 111 };
 112
 113 /*
 114  * RTS threshold here is total size [2347] minus 4 FCS bytes
 115  * Per spec:
 116  *   a value of 0 means RTS on all data/management packets
 117  *   a value > max MSDU size means no RTS
 118  * else RTS for data/management frames where MPDU is larger
 119  *   than RTS value.
 120  */
 121 #define DEFAULT_RTS_THRESHOLD     2347U
 122 #define MIN_RTS_THRESHOLD         0U
 123 #define MAX_RTS_THRESHOLD         2347U
 124 #define MAX_MSDU_SIZE             2304U
 125 #define MAX_MPDU_SIZE             2346U
 126 #define DEFAULT_BEACON_INTERVAL   100U
 127 #define DEFAULT_SHORT_RETRY_LIMIT 7U
 128 #define DEFAULT_LONG_RETRY_LIMIT  4U
 129
 130 #define IL_TX_FIFO_AC0  0
 131 #define IL_TX_FIFO_AC1  1
 132 #define IL_TX_FIFO_AC2  2
 133 #define IL_TX_FIFO_AC3  3
 134 #define IL_TX_FIFO_HCCA_1       5
 135 #define IL_TX_FIFO_HCCA_2       6
 136 #define IL_TX_FIFO_NONE 7
 137
 138 #define IEEE80211_DATA_LEN              2304
 139 #define IEEE80211_4ADDR_LEN             30
 140 #define IEEE80211_HLEN                  (IEEE80211_4ADDR_LEN)
 141 #define IEEE80211_FRAME_LEN             (IEEE80211_DATA_LEN + IEEE80211_HLEN)
 142
 143 struct il3945_frame {
 144         union {
 145                 struct ieee80211_hdr frame;
 146                 struct il3945_tx_beacon_cmd beacon;
 147                 u8 raw[IEEE80211_FRAME_LEN];
 148                 u8 cmd[360];
 149         } u;
 150         struct list_head list;
 151 };
 152
 153 #define SUP_RATE_11A_MAX_NUM_CHANNELS  8
 154 #define SUP_RATE_11B_MAX_NUM_CHANNELS  4
 155 #define SUP_RATE_11G_MAX_NUM_CHANNELS  12
 156
 157 #define IL_SUPPORTED_RATES_IE_LEN         8
 158
 159 #define SCAN_INTERVAL 100
 160
 161 #define MAX_TID_COUNT        9
 162
 163 #define IL_INVALID_RATE     0xFF
 164 #define IL_INVALID_VALUE    -1
 165
 166 #define STA_PS_STATUS_WAKE             0
 167 #define STA_PS_STATUS_SLEEP            1
 168
 169 struct il3945_ibss_seq {
 170         u8 mac[ETH_ALEN];
 171         u16 seq_num;
 172         u16 frag_num;
 173         unsigned long packet_time;
 174         struct list_head list;
 175 };
 176
 177 #define IL_RX_HDR(x) ((struct il3945_rx_frame_hdr *)(\
 178                        x->u.rx_frame.stats.payload + \
 179                        x->u.rx_frame.stats.phy_count))
 180 #define IL_RX_END(x) ((struct il3945_rx_frame_end *)(\
 181                        IL_RX_HDR(x)->payload + \
 182                        le16_to_cpu(IL_RX_HDR(x)->len)))
 183 #define IL_RX_STATS(x) (&x->u.rx_frame.stats)
 184 #define IL_RX_DATA(x) (IL_RX_HDR(x)->payload)
 185
 186 /******************************************************************************
 187  *
 188  * Functions implemented in iwl3945-base.c which are forward declared here
 189  * for use by iwl-*.c
 190  *
 191  *****************************************************************************/
 192 int il3945_calc_db_from_ratio(int sig_ratio);
 193 void il3945_rx_replenish(void *data);
 194 void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
 195 unsigned int il3945_fill_beacon_frame(struct il_priv *il,
 196                                       struct ieee80211_hdr *hdr, int left);
 197 int il3945_dump_nic_event_log(struct il_priv *il, bool full_log, char **buf,
 198                               bool display);
 199 void il3945_dump_nic_error_log(struct il_priv *il);
 200
 201 /******************************************************************************
 202  *
 203  * Functions implemented in iwl-[34]*.c which are forward declared here
 204  * for use by iwl3945-base.c
 205  *
 206  * NOTE:  The implementation of these functions are hardware specific
 207  * which is why they are in the hardware specific files (vs. iwl-base.c)
 208  *
 209  * Naming convention --
 210  * il3945_         <-- Its part of iwlwifi (should be changed to il3945_)
 211  * il3945_hw_      <-- Hardware specific (implemented in iwl-XXXX.c by all HW)
 212  * iwlXXXX_     <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
 213  * il3945_bg_      <-- Called from work queue context
 214  * il3945_mac_     <-- mac80211 callback
 215  *
 216  ****************************************************************************/
 217 void il3945_hw_handler_setup(struct il_priv *il);
 218 void il3945_hw_setup_deferred_work(struct il_priv *il);
 219 void il3945_hw_cancel_deferred_work(struct il_priv *il);
 220 int il3945_hw_rxq_stop(struct il_priv *il);
 221 int il3945_hw_set_hw_params(struct il_priv *il);
 222 int il3945_hw_nic_init(struct il_priv *il);
 223 int il3945_hw_nic_stop_master(struct il_priv *il);
 224 void il3945_hw_txq_ctx_free(struct il_priv *il);
 225 void il3945_hw_txq_ctx_stop(struct il_priv *il);
 226 int il3945_hw_nic_reset(struct il_priv *il);
 227 int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
 228                                     dma_addr_t addr, u16 len, u8 reset, u8 pad);
 229 void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
 230 int il3945_hw_get_temperature(struct il_priv *il);
 231 int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
 232 unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il,
 233                                       struct il3945_frame *frame, u8 rate);
 234 void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
 235                                  struct ieee80211_tx_info *info,
 236                                  struct ieee80211_hdr *hdr, int sta_id);
 237 int il3945_hw_reg_send_txpower(struct il_priv *il);
 238 int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power);
 239 void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);
 240 void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);
 241 void il3945_disable_events(struct il_priv *il);
 242 int il4965_get_temperature(const struct il_priv *il);
 243 void il3945_post_associate(struct il_priv *il);
 244 void il3945_config_ap(struct il_priv *il);
 245
 246 int il3945_commit_rxon(struct il_priv *il);
 247
 248 /**
 249  * il3945_hw_find_station - Find station id for a given BSSID
 250  * @bssid: MAC address of station ID to find
 251  *
 252  * NOTE:  This should not be hardware specific but the code has
 253  * not yet been merged into a single common layer for managing the
 254  * station tables.
 255  */
 256 u8 il3945_hw_find_station(struct il_priv *il, const u8 *bssid);
 257
 258 __le32 il3945_get_antenna_flags(const struct il_priv *il);
 259 int il3945_init_hw_rate_table(struct il_priv *il);
 260 void il3945_reg_txpower_periodic(struct il_priv *il);
 261 int il3945_txpower_set_from_eeprom(struct il_priv *il);
 262
 263 int il3945_rs_next_rate(struct il_priv *il, int rate);
 264
 265 /* scanning */
 266 int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
 267 void il3945_post_scan(struct il_priv *il);
 268
 269 /* rates */
 270 extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945];
 271
 272 /* RSSI to dBm */
 273 #define IL39_RSSI_OFFSET        95
 274
 275 /*
 276  * EEPROM related constants, enums, and structures.
 277  */
 278 #define EEPROM_SKU_CAP_OP_MODE_MRC                      (1 << 7)
 279
 280 /*
 281  * Mapping of a Tx power level, at factory calibration temperature,
 282  *   to a radio/DSP gain table idx.
 283  * One for each of 5 "sample" power levels in each band.
 284  * v_det is measured at the factory, using the 3945's built-in power amplifier
 285  *   (PA) output voltage detector.  This same detector is used during Tx of
 286  *   long packets in normal operation to provide feedback as to proper output
 287  *   level.
 288  * Data copied from EEPROM.
 289  * DO NOT ALTER THIS STRUCTURE!!!
 290  */
 291 struct il3945_eeprom_txpower_sample {
 292         u8 gain_idx;            /* idx into power (gain) setup table ... */
 293         s8 power;               /* ... for this pwr level for this chnl group */
 294         u16 v_det;              /* PA output voltage */
 295 } __packed;
 296
 297 /*
 298  * Mappings of Tx power levels -> nominal radio/DSP gain table idxes.
 299  * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
 300  * Tx power setup code interpolates between the 5 "sample" power levels
 301  *    to determine the nominal setup for a requested power level.
 302  * Data copied from EEPROM.
 303  * DO NOT ALTER THIS STRUCTURE!!!
 304  */
 305 struct il3945_eeprom_txpower_group {
 306         struct il3945_eeprom_txpower_sample samples[5]; /* 5 power levels */
 307         s32 a, b, c, d, e;      /* coefficients for voltage->power
 308                                  * formula (signed) */
 309         s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
 310                                  * frequency (signed) */
 311         s8 saturation_power;    /* highest power possible by h/w in this
 312                                  * band */
 313         u8 group_channel;       /* "representative" channel # in this band */
 314         s16 temperature;        /* h/w temperature at factory calib this band
 315                                  * (signed) */
 316 } __packed;
 317
 318 /*
 319  * Temperature-based Tx-power compensation data, not band-specific.
 320  * These coefficients are use to modify a/b/c/d/e coeffs based on
 321  *   difference between current temperature and factory calib temperature.
 322  * Data copied from EEPROM.
 323  */
 324 struct il3945_eeprom_temperature_corr {
 325         u32 Ta;
 326         u32 Tb;
 327         u32 Tc;
 328         u32 Td;
 329         u32 Te;
 330 } __packed;
 331
 332 /*
 333  * EEPROM map
 334  */
 335 struct il3945_eeprom {
 336         u8 reserved0[16];
 337         u16 device_id;          /* abs.ofs: 16 */
 338         u8 reserved1[2];
 339         u16 pmc;                /* abs.ofs: 20 */
 340         u8 reserved2[20];
 341         u8 mac_address[6];      /* abs.ofs: 42 */
 342         u8 reserved3[58];
 343         u16 board_revision;     /* abs.ofs: 106 */
 344         u8 reserved4[11];
 345         u8 board_pba_number[9]; /* abs.ofs: 119 */
 346         u8 reserved5[8];
 347         u16 version;            /* abs.ofs: 136 */
 348         u8 sku_cap;             /* abs.ofs: 138 */
 349         u8 leds_mode;           /* abs.ofs: 139 */
 350         u16 oem_mode;
 351         u16 wowlan_mode;        /* abs.ofs: 142 */
 352         u16 leds_time_interval; /* abs.ofs: 144 */
 353         u8 leds_off_time;       /* abs.ofs: 146 */
 354         u8 leds_on_time;        /* abs.ofs: 147 */
 355         u8 almgor_m_version;    /* abs.ofs: 148 */
 356         u8 antenna_switch_type; /* abs.ofs: 149 */
 357         u8 reserved6[42];
 358         u8 sku_id[4];           /* abs.ofs: 192 */
 359
 360 /*
 361  * Per-channel regulatory data.
 362  *
 363  * Each channel that *might* be supported by 3945 has a fixed location
 364  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
 365  * txpower (MSB).
 366  *
 367  * Entries immediately below are for 20 MHz channel width.
 368  *
 369  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 370  */
 371         u16 band_1_count;       /* abs.ofs: 196 */
 372         struct il_eeprom_channel band_1_channels[14];   /* abs.ofs: 198 */
 373
 374 /*
 375  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
 376  * 5.0 GHz channels 7, 8, 11, 12, 16
 377  * (4915-5080MHz) (none of these is ever supported)
 378  */
 379         u16 band_2_count;       /* abs.ofs: 226 */
 380         struct il_eeprom_channel band_2_channels[13];   /* abs.ofs: 228 */
 381
 382 /*
 383  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 384  * (5170-5320MHz)
 385  */
 386         u16 band_3_count;       /* abs.ofs: 254 */
 387         struct il_eeprom_channel band_3_channels[12];   /* abs.ofs: 256 */
 388
 389 /*
 390  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 391  * (5500-5700MHz)
 392  */
 393         u16 band_4_count;       /* abs.ofs: 280 */
 394         struct il_eeprom_channel band_4_channels[11];   /* abs.ofs: 282 */
 395
 396 /*
 397  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
 398  * (5725-5825MHz)
 399  */
 400         u16 band_5_count;       /* abs.ofs: 304 */
 401         struct il_eeprom_channel band_5_channels[6];    /* abs.ofs: 306 */
 402
 403         u8 reserved9[194];
 404
 405 /*
 406  * 3945 Txpower calibration data.
 407  */
 408 #define IL_NUM_TX_CALIB_GROUPS 5
 409         struct il3945_eeprom_txpower_group groups[IL_NUM_TX_CALIB_GROUPS];
 410 /* abs.ofs: 512 */
 411         struct il3945_eeprom_temperature_corr corrections;      /* abs.ofs: 832 */
 412         u8 reserved16[172];     /* fill out to full 1024 byte block */
 413 } __packed;
 414
 415 #define IL3945_EEPROM_IMG_SIZE 1024
 416
 417 /* End of EEPROM */
 418
 419 #define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)      /* bit 6    */
 420 #define PCI_CFG_REV_ID_BIT_RTP                      (0x80)      /* bit 7    */
 421
 422 /* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */
 423 #define IL39_NUM_QUEUES        5
 424 #define IL39_CMD_QUEUE_NUM      4
 425
 426 #define IL_DEFAULT_TX_RETRY  15
 427
 428 /*********************************************/
 429
 430 #define RFD_SIZE                              4
 431 #define NUM_TFD_CHUNKS                        4
 432
 433 #define TFD_CTL_COUNT_SET(n)       (n << 24)
 434 #define TFD_CTL_COUNT_GET(ctl)     ((ctl >> 24) & 7)
 435 #define TFD_CTL_PAD_SET(n)         (n << 28)
 436 #define TFD_CTL_PAD_GET(ctl)       (ctl >> 28)
 437
 438 /* Sizes and addresses for instruction and data memory (SRAM) in
 439  * 3945's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */
 440 #define IL39_RTC_INST_LOWER_BOUND               (0x000000)
 441 #define IL39_RTC_INST_UPPER_BOUND               (0x014000)
 442
 443 #define IL39_RTC_DATA_LOWER_BOUND               (0x800000)
 444 #define IL39_RTC_DATA_UPPER_BOUND               (0x808000)
 445
 446 #define IL39_RTC_INST_SIZE (IL39_RTC_INST_UPPER_BOUND - \
 447                                 IL39_RTC_INST_LOWER_BOUND)
 448 #define IL39_RTC_DATA_SIZE (IL39_RTC_DATA_UPPER_BOUND - \
 449                                 IL39_RTC_DATA_LOWER_BOUND)
 450
 451 #define IL39_MAX_INST_SIZE IL39_RTC_INST_SIZE
 452 #define IL39_MAX_DATA_SIZE IL39_RTC_DATA_SIZE
 453
 454 /* Size of uCode instruction memory in bootstrap state machine */
 455 #define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE
 456
 457 static inline int
 458 il3945_hw_valid_rtc_data_addr(u32 addr)
 459 {
 460         return (addr >= IL39_RTC_DATA_LOWER_BOUND &&
 461                 addr < IL39_RTC_DATA_UPPER_BOUND);
 462 }
 463
 464 /* Base physical address of il3945_shared is provided to FH39_TSSR_CBB_BASE
 465  * and &il3945_shared.rx_read_ptr[0] is provided to FH39_RCSR_RPTR_ADDR(0) */
 466 struct il3945_shared {
 467         __le32 tx_base_ptr[8];
 468 } __packed;
 469
 470 /************************************/
 471 /* iwl3945 Flow Handler Definitions */
 472 /************************************/
 473
 474 /**
 475  * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
 476  * Addresses are offsets from device's PCI hardware base address.
 477  */
 478 #define FH39_MEM_LOWER_BOUND                   (0x0800)
 479 #define FH39_MEM_UPPER_BOUND                   (0x1000)
 480
 481 #define FH39_CBCC_TBL           (FH39_MEM_LOWER_BOUND + 0x140)
 482 #define FH39_TFDB_TBL           (FH39_MEM_LOWER_BOUND + 0x180)
 483 #define FH39_RCSR_TBL           (FH39_MEM_LOWER_BOUND + 0x400)
 484 #define FH39_RSSR_TBL           (FH39_MEM_LOWER_BOUND + 0x4c0)
 485 #define FH39_TCSR_TBL           (FH39_MEM_LOWER_BOUND + 0x500)
 486 #define FH39_TSSR_TBL           (FH39_MEM_LOWER_BOUND + 0x680)
 487
 488 /* TFDB (Transmit Frame Buffer Descriptor) */
 489 #define FH39_TFDB(_ch, buf)                     (FH39_TFDB_TBL + \
 490                                                  ((_ch) * 2 + (buf)) * 0x28)
 491 #define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch)        (FH39_TFDB_TBL + 0x50 * (_ch))
 492
 493 /* CBCC channel is [0,2] */
 494 #define FH39_CBCC(_ch)          (FH39_CBCC_TBL + (_ch) * 0x8)
 495 #define FH39_CBCC_CTRL(_ch)     (FH39_CBCC(_ch) + 0x00)
 496 #define FH39_CBCC_BASE(_ch)     (FH39_CBCC(_ch) + 0x04)
 497
 498 /* RCSR channel is [0,2] */
 499 #define FH39_RCSR(_ch)                  (FH39_RCSR_TBL + (_ch) * 0x40)
 500 #define FH39_RCSR_CONFIG(_ch)           (FH39_RCSR(_ch) + 0x00)
 501 #define FH39_RCSR_RBD_BASE(_ch)         (FH39_RCSR(_ch) + 0x04)
 502 #define FH39_RCSR_WPTR(_ch)             (FH39_RCSR(_ch) + 0x20)
 503 #define FH39_RCSR_RPTR_ADDR(_ch)        (FH39_RCSR(_ch) + 0x24)
 504
 505 #define FH39_RSCSR_CHNL0_WPTR           (FH39_RCSR_WPTR(0))
 506
 507 /* RSSR */
 508 #define FH39_RSSR_CTRL                  (FH39_RSSR_TBL + 0x000)
 509 #define FH39_RSSR_STATUS                (FH39_RSSR_TBL + 0x004)
 510
 511 /* TCSR */
 512 #define FH39_TCSR(_ch)                  (FH39_TCSR_TBL + (_ch) * 0x20)
 513 #define FH39_TCSR_CONFIG(_ch)           (FH39_TCSR(_ch) + 0x00)
 514 #define FH39_TCSR_CREDIT(_ch)           (FH39_TCSR(_ch) + 0x04)
 515 #define FH39_TCSR_BUFF_STTS(_ch)        (FH39_TCSR(_ch) + 0x08)
 516
 517 /* TSSR */
 518 #define FH39_TSSR_CBB_BASE        (FH39_TSSR_TBL + 0x000)
 519 #define FH39_TSSR_MSG_CONFIG      (FH39_TSSR_TBL + 0x008)
 520 #define FH39_TSSR_TX_STATUS       (FH39_TSSR_TBL + 0x010)
 521
 522 /* DBM */
 523
 524 #define FH39_SRVC_CHNL                            (6)
 525
 526 #define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE     (20)
 527 #define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH      (4)
 528
 529 #define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN    (0x08000000)
 530
 531 #define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE        (0x80000000)
 532
 533 #define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE           (0x20000000)
 534
 535 #define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128           (0x01000000)
 536
 537 #define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST           (0x00001000)
 538
 539 #define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH                 (0x00000000)
 540
 541 #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF                (0x00000000)
 542 #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER             (0x00000001)
 543
 544 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL      (0x00000000)
 545 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL       (0x00000008)
 546
 547 #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD             (0x00200000)
 548
 549 #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT              (0x00000000)
 550
 551 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE              (0x00000000)
 552 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE             (0x80000000)
 553
 554 #define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID            (0x00004000)
 555
 556 #define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR             (0x00000001)
 557
 558 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON        (0xFF000000)
 559 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON        (0x00FF0000)
 560
 561 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B      (0x00000400)
 562
 563 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON         (0x00000100)
 564 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON         (0x00000080)
 565
 566 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH       (0x00000020)
 567 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH             (0x00000005)
 568
 569 #define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch)     (BIT(_ch) << 24)
 570 #define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch)    (BIT(_ch) << 16)
 571
 572 #define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \
 573         (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \
 574          FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))
 575
 576 #define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE                     (0x01000000)
 577
 578 struct il3945_tfd_tb {
 579         __le32 addr;
 580         __le32 len;
 581 } __packed;
 582
 583 struct il3945_tfd {
 584         __le32 control_flags;
 585         struct il3945_tfd_tb tbs[4];
 586         u8 __pad[28];
 587 } __packed;
 588
 589 #ifdef CONFIG_IWLEGACY_DEBUGFS
 590 extern const struct il_debugfs_ops il3945_debugfs_ops;
 591 #endif
 592
 593 #endif