drivers/net/wireless/intel/iwlwifi/fw/api/debug.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called COPYING.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <linuxwifi@intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  * BSD LICENSE
  29  *
  30  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  31  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  32  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  33  * All rights reserved.
  34  *
  35  * Redistribution and use in source and binary forms, with or without
  36  * modification, are permitted provided that the following conditions
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  38  *
  39  *  * Redistributions of source code must retain the above copyright
  40  *    notice, this list of conditions and the following disclaimer.
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  44  *    distribution.
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  47  *    from this software without specific prior written permission.
  48  *
  49  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  50  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  51  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  52  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  53  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  54  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  55  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  56  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  58  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  59  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  60  *
  61  *****************************************************************************/
  62 #ifndef __iwl_fw_api_debug_h__
  63 #define __iwl_fw_api_debug_h__
  64
  65 /**
  66  * enum iwl_debug_cmds - debug commands
  67  */
  68 enum iwl_debug_cmds {
  69         /**
  70          * @LMAC_RD_WR:
  71          * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
  72          * &struct iwl_dbg_mem_access_rsp
  73          */
  74         LMAC_RD_WR = 0x0,
  75         /**
  76          * @UMAC_RD_WR:
  77          * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
  78          * &struct iwl_dbg_mem_access_rsp
  79          */
  80         UMAC_RD_WR = 0x1,
  81         /**
  82          * @MFU_ASSERT_DUMP_NTF:
  83          * &struct iwl_mfu_assert_dump_notif
  84          */
  85         MFU_ASSERT_DUMP_NTF = 0xFE,
  86 };
  87
  88 /* Error response/notification */
  89 enum {
  90         FW_ERR_UNKNOWN_CMD = 0x0,
  91         FW_ERR_INVALID_CMD_PARAM = 0x1,
  92         FW_ERR_SERVICE = 0x2,
  93         FW_ERR_ARC_MEMORY = 0x3,
  94         FW_ERR_ARC_CODE = 0x4,
  95         FW_ERR_WATCH_DOG = 0x5,
  96         FW_ERR_WEP_GRP_KEY_INDX = 0x10,
  97         FW_ERR_WEP_KEY_SIZE = 0x11,
  98         FW_ERR_OBSOLETE_FUNC = 0x12,
  99         FW_ERR_UNEXPECTED = 0xFE,
 100         FW_ERR_FATAL = 0xFF
 101 };
 102
 103 /**
 104  * struct iwl_error_resp - FW error indication
 105  * ( REPLY_ERROR = 0x2 )
 106  * @error_type: one of FW_ERR_*
 107  * @cmd_id: the command ID for which the error occurred
 108  * @reserved1: reserved
 109  * @bad_cmd_seq_num: sequence number of the erroneous command
 110  * @error_service: which service created the error, applicable only if
 111  *     error_type = 2, otherwise 0
 112  * @timestamp: TSF in usecs.
 113  */
 114 struct iwl_error_resp {
 115         __le32 error_type;
 116         u8 cmd_id;
 117         u8 reserved1;
 118         __le16 bad_cmd_seq_num;
 119         __le32 error_service;
 120         __le64 timestamp;
 121 } __packed;
 122
 123 #define TX_FIFO_MAX_NUM_9000            8
 124 #define TX_FIFO_MAX_NUM                 15
 125 #define RX_FIFO_MAX_NUM                 2
 126 #define TX_FIFO_INTERNAL_MAX_NUM        6
 127
 128 /**
 129  * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
 130  *
 131  * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
 132  *      accessible)
 133  * @shared_mem_size: shared memory size
 134  * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
 135  *      0x0 as accessible only via DBGM RDAT)
 136  * @sample_buff_size: internal sample buff size
 137  * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
 138  *      8000 HW set to 0x0 as not accessible)
 139  * @txfifo_size: size of TXF0 ... TXF7
 140  * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
 141  * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
 142  *      when paging is not supported this should be 0
 143  * @page_buff_size: size of %page_buff_addr
 144  * @rxfifo_addr: Start address of rxFifo
 145  * @internal_txfifo_addr: start address of internalFifo
 146  * @internal_txfifo_size: internal fifos' size
 147  *
 148  * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
 149  *       set, the last 3 members don't exist.
 150  */
 151 struct iwl_shared_mem_cfg_v2 {
 152         __le32 shared_mem_addr;
 153         __le32 shared_mem_size;
 154         __le32 sample_buff_addr;
 155         __le32 sample_buff_size;
 156         __le32 txfifo_addr;
 157         __le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
 158         __le32 rxfifo_size[RX_FIFO_MAX_NUM];
 159         __le32 page_buff_addr;
 160         __le32 page_buff_size;
 161         __le32 rxfifo_addr;
 162         __le32 internal_txfifo_addr;
 163         __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
 164 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
 165
 166 /**
 167  * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
 168  *
 169  * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
 170  * @txfifo_size: size of TX FIFOs
 171  * @rxfifo1_addr: RXF1 addr
 172  * @rxfifo1_size: RXF1 size
 173  */
 174 struct iwl_shared_mem_lmac_cfg {
 175         __le32 txfifo_addr;
 176         __le32 txfifo_size[TX_FIFO_MAX_NUM];
 177         __le32 rxfifo1_addr;
 178         __le32 rxfifo1_size;
 179
 180 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
 181
 182 /**
 183  * struct iwl_shared_mem_cfg - Shared memory configuration information
 184  *
 185  * @shared_mem_addr: shared memory address
 186  * @shared_mem_size: shared memory size
 187  * @sample_buff_addr: internal sample (mon/adc) buff addr
 188  * @sample_buff_size: internal sample buff size
 189  * @rxfifo2_addr: start addr of RXF2
 190  * @rxfifo2_size: size of RXF2
 191  * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
 192  *      when paging is not supported this should be 0
 193  * @page_buff_size: size of %page_buff_addr
 194  * @lmac_num: number of LMACs (1 or 2)
 195  * @lmac_smem: per - LMAC smem data
 196  */
 197 struct iwl_shared_mem_cfg {
 198         __le32 shared_mem_addr;
 199         __le32 shared_mem_size;
 200         __le32 sample_buff_addr;
 201         __le32 sample_buff_size;
 202         __le32 rxfifo2_addr;
 203         __le32 rxfifo2_size;
 204         __le32 page_buff_addr;
 205         __le32 page_buff_size;
 206         __le32 lmac_num;
 207         struct iwl_shared_mem_lmac_cfg lmac_smem[2];
 208 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_3 */
 209
 210 /**
 211  * struct iwl_mfuart_load_notif - mfuart image version & status
 212  * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
 213  * @installed_ver: installed image version
 214  * @external_ver: external image version
 215  * @status: MFUART loading status
 216  * @duration: MFUART loading time
 217  * @image_size: MFUART image size in bytes
 218 */
 219 struct iwl_mfuart_load_notif {
 220         __le32 installed_ver;
 221         __le32 external_ver;
 222         __le32 status;
 223         __le32 duration;
 224         /* image size valid only in v2 of the command */
 225         __le32 image_size;
 226 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
 227
 228 /**
 229  * struct iwl_mfu_assert_dump_notif - mfuart dump logs
 230  * ( MFU_ASSERT_DUMP_NTF = 0xfe )
 231  * @assert_id: mfuart assert id that cause the notif
 232  * @curr_reset_num: number of asserts since uptime
 233  * @index_num: current chunk id
 234  * @parts_num: total number of chunks
 235  * @data_size: number of data bytes sent
 236  * @data: data buffer
 237  */
 238 struct iwl_mfu_assert_dump_notif {
 239         __le32   assert_id;
 240         __le32   curr_reset_num;
 241         __le16   index_num;
 242         __le16   parts_num;
 243         __le32   data_size;
 244         __le32   data[0];
 245 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
 246
 247 /**
 248  * enum iwl_mvm_marker_id - marker ids
 249  *
 250  * The ids for different type of markers to insert into the usniffer logs
 251  *
 252  * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
 253  * @MARKER_ID_SYNC_CLOCK: sync FW time and systime
 254  */
 255 enum iwl_mvm_marker_id {
 256         MARKER_ID_TX_FRAME_LATENCY = 1,
 257         MARKER_ID_SYNC_CLOCK = 2,
 258 }; /* MARKER_ID_API_E_VER_2 */
 259
 260 /**
 261  * struct iwl_mvm_marker - mark info into the usniffer logs
 262  *
 263  * (MARKER_CMD = 0xcb)
 264  *
 265  * Mark the UTC time stamp into the usniffer logs together with additional
 266  * metadata, so the usniffer output can be parsed.
 267  * In the command response the ucode will return the GP2 time.
 268  *
 269  * @dw_len: The amount of dwords following this byte including this byte.
 270  * @marker_id: A unique marker id (iwl_mvm_marker_id).
 271  * @reserved: reserved.
 272  * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
 273  * @metadata: additional meta data that will be written to the unsiffer log
 274  */
 275 struct iwl_mvm_marker {
 276         u8 dw_len;
 277         u8 marker_id;
 278         __le16 reserved;
 279         __le64 timestamp;
 280         __le32 metadata[0];
 281 } __packed; /* MARKER_API_S_VER_1 */
 282
 283 /**
 284  * struct iwl_mvm_marker_rsp - Response to marker cmd
 285  *
 286  * @gp2: The gp2 clock value in the FW
 287  */
 288 struct iwl_mvm_marker_rsp {
 289         __le32 gp2;
 290 } __packed;
 291
 292 /* Operation types for the debug mem access */
 293 enum {
 294         DEBUG_MEM_OP_READ = 0,
 295         DEBUG_MEM_OP_WRITE = 1,
 296         DEBUG_MEM_OP_WRITE_BYTES = 2,
 297 };
 298
 299 #define DEBUG_MEM_MAX_SIZE_DWORDS 32
 300
 301 /**
 302  * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
 303  * @op: DEBUG_MEM_OP_*
 304  * @addr: address to read/write from/to
 305  * @len: in dwords, to read/write
 306  * @data: for write opeations, contains the source buffer
 307  */
 308 struct iwl_dbg_mem_access_cmd {
 309         __le32 op;
 310         __le32 addr;
 311         __le32 len;
 312         __le32 data[];
 313 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
 314
 315 /* Status responses for the debug mem access */
 316 enum {
 317         DEBUG_MEM_STATUS_SUCCESS = 0x0,
 318         DEBUG_MEM_STATUS_FAILED = 0x1,
 319         DEBUG_MEM_STATUS_LOCKED = 0x2,
 320         DEBUG_MEM_STATUS_HIDDEN = 0x3,
 321         DEBUG_MEM_STATUS_LENGTH = 0x4,
 322 };
 323
 324 /**
 325  * struct iwl_dbg_mem_access_rsp - Response to debug mem commands
 326  * @status: DEBUG_MEM_STATUS_*
 327  * @len: read dwords (0 for write operations)
 328  * @data: contains the read DWs
 329  */
 330 struct iwl_dbg_mem_access_rsp {
 331         __le32 status;
 332         __le32 len;
 333         __le32 data[];
 334 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
 335
 336 #define CONT_REC_COMMAND_SIZE   80
 337 #define ENABLE_CONT_RECORDING   0x15
 338 #define DISABLE_CONT_RECORDING  0x16
 339
 340 /*
 341  * struct iwl_continuous_record_mode - recording mode
 342  */
 343 struct iwl_continuous_record_mode {
 344         __le16 enable_recording;
 345 } __packed;
 346
 347 /*
 348  * struct iwl_continuous_record_cmd - enable/disable continuous recording
 349  */
 350 struct iwl_continuous_record_cmd {
 351         struct iwl_continuous_record_mode record_mode;
 352         u8 pad[CONT_REC_COMMAND_SIZE -
 353                 sizeof(struct iwl_continuous_record_mode)];
 354 } __packed;
 355
 356 #endif /* __iwl_fw_api_debug_h__ */