drivers/net/wireless/ti/wlcore/acx.h

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
   5  * Copyright (C) 2008-2010 Nokia Corporation
   6  *
   7  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #ifndef __ACX_H__
  26 #define __ACX_H__
  27
  28 #include "wlcore.h"
  29 #include "cmd.h"
  30
  31 /*************************************************************************
  32
  33     Host Interrupt Register (WiLink -> Host)
  34
  35 **************************************************************************/
  36 /* HW Initiated interrupt Watchdog timer expiration */
  37 #define WL1271_ACX_INTR_WATCHDOG           BIT(0)
  38 /* Init sequence is done (masked interrupt, detection through polling only ) */
  39 #define WL1271_ACX_INTR_INIT_COMPLETE      BIT(1)
  40 /* Event was entered to Event MBOX #A*/
  41 #define WL1271_ACX_INTR_EVENT_A            BIT(2)
  42 /* Event was entered to Event MBOX #B*/
  43 #define WL1271_ACX_INTR_EVENT_B            BIT(3)
  44 /* Command processing completion*/
  45 #define WL1271_ACX_INTR_CMD_COMPLETE       BIT(4)
  46 /* Signaling the host on HW wakeup */
  47 #define WL1271_ACX_INTR_HW_AVAILABLE       BIT(5)
  48 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
  49 #define WL1271_ACX_INTR_DATA               BIT(6)
  50 /* Trace message on MBOX #A */
  51 #define WL1271_ACX_INTR_TRACE_A            BIT(7)
  52 /* Trace message on MBOX #B */
  53 #define WL1271_ACX_INTR_TRACE_B            BIT(8)
  54 /* SW FW Initiated interrupt Watchdog timer expiration */
  55 #define WL1271_ACX_SW_INTR_WATCHDOG        BIT(9)
  56
  57 #define WL1271_ACX_INTR_ALL             0xFFFFFFFF
  58
  59 /* all possible interrupts - only appropriate ones will be masked in */
  60 #define WLCORE_ALL_INTR_MASK            (WL1271_ACX_INTR_WATCHDOG     | \
  61                                         WL1271_ACX_INTR_EVENT_A       | \
  62                                         WL1271_ACX_INTR_EVENT_B       | \
  63                                         WL1271_ACX_INTR_HW_AVAILABLE  | \
  64                                         WL1271_ACX_INTR_DATA          | \
  65                                         WL1271_ACX_SW_INTR_WATCHDOG)
  66
  67 /* Target's information element */
  68 struct acx_header {
  69         struct wl1271_cmd_header cmd;
  70
  71         /* acx (or information element) header */
  72         __le16 id;
  73
  74         /* payload length (not including headers */
  75         __le16 len;
  76 } __packed;
  77
  78 struct acx_error_counter {
  79         struct acx_header header;
  80
  81         /* The number of PLCP errors since the last time this */
  82         /* information element was interrogated. This field is */
  83         /* automatically cleared when it is interrogated.*/
  84         __le32 PLCP_error;
  85
  86         /* The number of FCS errors since the last time this */
  87         /* information element was interrogated. This field is */
  88         /* automatically cleared when it is interrogated.*/
  89         __le32 FCS_error;
  90
  91         /* The number of MPDUs without PLCP header errors received*/
  92         /* since the last time this information element was interrogated. */
  93         /* This field is automatically cleared when it is interrogated.*/
  94         __le32 valid_frame;
  95
  96         /* the number of missed sequence numbers in the squentially */
  97         /* values of frames seq numbers */
  98         __le32 seq_num_miss;
  99 } __packed;
 100
 101 enum wl12xx_role {
 102         WL1271_ROLE_STA = 0,
 103         WL1271_ROLE_IBSS,
 104         WL1271_ROLE_AP,
 105         WL1271_ROLE_DEVICE,
 106         WL1271_ROLE_P2P_CL,
 107         WL1271_ROLE_P2P_GO,
 108         WL1271_ROLE_MESH_POINT,
 109
 110         WL12XX_INVALID_ROLE_TYPE = 0xff
 111 };
 112
 113 enum wl1271_psm_mode {
 114         /* Active mode */
 115         WL1271_PSM_CAM = 0,
 116
 117         /* Power save mode */
 118         WL1271_PSM_PS = 1,
 119
 120         /* Extreme low power */
 121         WL1271_PSM_ELP = 2,
 122
 123         WL1271_PSM_MAX = WL1271_PSM_ELP,
 124
 125         /* illegal out of band value of PSM mode */
 126         WL1271_PSM_ILLEGAL = 0xff
 127 };
 128
 129 struct acx_sleep_auth {
 130         struct acx_header header;
 131
 132         /* The sleep level authorization of the device. */
 133         /* 0 - Always active*/
 134         /* 1 - Power down mode: light / fast sleep*/
 135         /* 2 - ELP mode: Deep / Max sleep*/
 136         u8  sleep_auth;
 137         u8  padding[3];
 138 } __packed;
 139
 140 enum {
 141         HOSTIF_PCI_MASTER_HOST_INDIRECT,
 142         HOSTIF_PCI_MASTER_HOST_DIRECT,
 143         HOSTIF_SLAVE,
 144         HOSTIF_PKT_RING,
 145         HOSTIF_DONTCARE = 0xFF
 146 };
 147
 148 #define DEFAULT_UCAST_PRIORITY          0
 149 #define DEFAULT_RX_Q_PRIORITY           0
 150 #define DEFAULT_RXQ_PRIORITY            0 /* low 0 .. 15 high  */
 151 #define DEFAULT_RXQ_TYPE                0x07    /* All frames, Data/Ctrl/Mgmt */
 152 #define TRACE_BUFFER_MAX_SIZE           256
 153
 154 #define  DP_RX_PACKET_RING_CHUNK_SIZE 1600
 155 #define  DP_TX_PACKET_RING_CHUNK_SIZE 1600
 156 #define  DP_RX_PACKET_RING_CHUNK_NUM 2
 157 #define  DP_TX_PACKET_RING_CHUNK_NUM 2
 158 #define  DP_TX_COMPLETE_TIME_OUT 20
 159
 160 #define TX_MSDU_LIFETIME_MIN       0
 161 #define TX_MSDU_LIFETIME_MAX       3000
 162 #define TX_MSDU_LIFETIME_DEF       512
 163 #define RX_MSDU_LIFETIME_MIN       0
 164 #define RX_MSDU_LIFETIME_MAX       0xFFFFFFFF
 165 #define RX_MSDU_LIFETIME_DEF       512000
 166
 167 struct acx_rx_msdu_lifetime {
 168         struct acx_header header;
 169
 170         /*
 171          * The maximum amount of time, in TU, before the
 172          * firmware discards the MSDU.
 173          */
 174         __le32 lifetime;
 175 } __packed;
 176
 177 enum acx_slot_type {
 178         SLOT_TIME_LONG = 0,
 179         SLOT_TIME_SHORT = 1,
 180         DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
 181         MAX_SLOT_TIMES = 0xFF
 182 };
 183
 184 #define STATION_WONE_INDEX 0
 185
 186 struct acx_slot {
 187         struct acx_header header;
 188
 189         u8 role_id;
 190         u8 wone_index; /* Reserved */
 191         u8 slot_time;
 192         u8 reserved[5];
 193 } __packed;
 194
 195
 196 #define ACX_MC_ADDRESS_GROUP_MAX        (8)
 197 #define ADDRESS_GROUP_MAX_LEN           (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
 198
 199 struct acx_dot11_grp_addr_tbl {
 200         struct acx_header header;
 201
 202         u8 role_id;
 203         u8 enabled;
 204         u8 num_groups;
 205         u8 pad[1];
 206         u8 mac_table[ADDRESS_GROUP_MAX_LEN];
 207 } __packed;
 208
 209 struct acx_rx_timeout {
 210         struct acx_header header;
 211
 212         u8 role_id;
 213         u8 reserved;
 214         __le16 ps_poll_timeout;
 215         __le16 upsd_timeout;
 216         u8 padding[2];
 217 } __packed;
 218
 219 struct acx_rts_threshold {
 220         struct acx_header header;
 221
 222         u8 role_id;
 223         u8 reserved;
 224         __le16 threshold;
 225 } __packed;
 226
 227 struct acx_beacon_filter_option {
 228         struct acx_header header;
 229
 230         u8 role_id;
 231         u8 enable;
 232         /*
 233          * The number of beacons without the unicast TIM
 234          * bit set that the firmware buffers before
 235          * signaling the host about ready frames.
 236          * When set to 0 and the filter is enabled, beacons
 237          * without the unicast TIM bit set are dropped.
 238          */
 239         u8 max_num_beacons;
 240         u8 pad[1];
 241 } __packed;
 242
 243 /*
 244  * ACXBeaconFilterEntry (not 221)
 245  * Byte Offset     Size (Bytes)    Definition
 246  * ===========     ============    ==========
 247  * 0               1               IE identifier
 248  * 1               1               Treatment bit mask
 249  *
 250  * ACXBeaconFilterEntry (221)
 251  * Byte Offset     Size (Bytes)    Definition
 252  * ===========     ============    ==========
 253  * 0               1               IE identifier
 254  * 1               1               Treatment bit mask
 255  * 2               3               OUI
 256  * 5               1               Type
 257  * 6               2               Version
 258  *
 259  *
 260  * Treatment bit mask - The information element handling:
 261  * bit 0 - The information element is compared and transferred
 262  * in case of change.
 263  * bit 1 - The information element is transferred to the host
 264  * with each appearance or disappearance.
 265  * Note that both bits can be set at the same time.
 266  */
 267 #define BEACON_FILTER_TABLE_MAX_IE_NUM                 (32)
 268 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
 269 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE              (2)
 270 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
 271 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
 272                             BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
 273                            (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
 274                             BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
 275
 276 struct acx_beacon_filter_ie_table {
 277         struct acx_header header;
 278
 279         u8 role_id;
 280         u8 num_ie;
 281         u8 pad[2];
 282         u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
 283 } __packed;
 284
 285 struct acx_conn_monit_params {
 286        struct acx_header header;
 287
 288            u8 role_id;
 289            u8 padding[3];
 290        __le32 synch_fail_thold; /* number of beacons missed */
 291        __le32 bss_lose_timeout; /* number of TU's from synch fail */
 292 } __packed;
 293
 294 struct acx_bt_wlan_coex {
 295         struct acx_header header;
 296
 297         u8 enable;
 298         u8 pad[3];
 299 } __packed;
 300
 301 struct acx_bt_wlan_coex_param {
 302         struct acx_header header;
 303
 304         __le32 params[WLCORE_CONF_SG_PARAMS_MAX];
 305         u8 param_idx;
 306         u8 padding[3];
 307 } __packed;
 308
 309 struct acx_dco_itrim_params {
 310         struct acx_header header;
 311
 312         u8 enable;
 313         u8 padding[3];
 314         __le32 timeout;
 315 } __packed;
 316
 317 struct acx_energy_detection {
 318         struct acx_header header;
 319
 320         /* The RX Clear Channel Assessment threshold in the PHY */
 321         __le16 rx_cca_threshold;
 322         u8 tx_energy_detection;
 323         u8 pad;
 324 } __packed;
 325
 326 struct acx_beacon_broadcast {
 327         struct acx_header header;
 328
 329         u8 role_id;
 330         /* Enables receiving of broadcast packets in PS mode */
 331         u8 rx_broadcast_in_ps;
 332
 333         __le16 beacon_rx_timeout;
 334         __le16 broadcast_timeout;
 335
 336         /* Consecutive PS Poll failures before updating the host */
 337         u8 ps_poll_threshold;
 338         u8 pad[1];
 339 } __packed;
 340
 341 struct acx_event_mask {
 342         struct acx_header header;
 343
 344         __le32 event_mask;
 345         __le32 high_event_mask; /* Unused */
 346 } __packed;
 347
 348 #define SCAN_PASSIVE            BIT(0)
 349 #define SCAN_5GHZ_BAND          BIT(1)
 350 #define SCAN_TRIGGERED          BIT(2)
 351 #define SCAN_PRIORITY_HIGH      BIT(3)
 352
 353 /* When set, disable HW encryption */
 354 #define DF_ENCRYPTION_DISABLE      0x01
 355 #define DF_SNIFF_MODE_ENABLE       0x80
 356
 357 struct acx_feature_config {
 358         struct acx_header header;
 359
 360         u8 role_id;
 361         u8 padding[3];
 362         __le32 options;
 363         __le32 data_flow_options;
 364 } __packed;
 365
 366 struct acx_current_tx_power {
 367         struct acx_header header;
 368
 369         u8  role_id;
 370         u8  current_tx_power;
 371         u8  padding[2];
 372 } __packed;
 373
 374 struct acx_wake_up_condition {
 375         struct acx_header header;
 376
 377         u8 role_id;
 378         u8 wake_up_event; /* Only one bit can be set */
 379         u8 listen_interval;
 380         u8 pad[1];
 381 } __packed;
 382
 383 struct acx_aid {
 384         struct acx_header header;
 385
 386         /*
 387          * To be set when associated with an AP.
 388          */
 389         u8 role_id;
 390         u8 reserved;
 391         __le16 aid;
 392 } __packed;
 393
 394 enum acx_preamble_type {
 395         ACX_PREAMBLE_LONG = 0,
 396         ACX_PREAMBLE_SHORT = 1
 397 };
 398
 399 struct acx_preamble {
 400         struct acx_header header;
 401
 402         /*
 403          * When set, the WiLink transmits the frames with a short preamble and
 404          * when cleared, the WiLink transmits the frames with a long preamble.
 405          */
 406         u8 role_id;
 407         u8 preamble;
 408         u8 padding[2];
 409 } __packed;
 410
 411 enum acx_ctsprotect_type {
 412         CTSPROTECT_DISABLE = 0,
 413         CTSPROTECT_ENABLE = 1
 414 };
 415
 416 struct acx_ctsprotect {
 417         struct acx_header header;
 418         u8 role_id;
 419         u8 ctsprotect;
 420         u8 padding[2];
 421 } __packed;
 422
 423 struct acx_rate_class {
 424         __le32 enabled_rates;
 425         u8 short_retry_limit;
 426         u8 long_retry_limit;
 427         u8 aflags;
 428         u8 reserved;
 429 };
 430
 431 struct acx_rate_policy {
 432         struct acx_header header;
 433
 434         __le32 rate_policy_idx;
 435         struct acx_rate_class rate_policy;
 436 } __packed;
 437
 438 struct acx_ac_cfg {
 439         struct acx_header header;
 440         u8 role_id;
 441         u8 ac;
 442         u8 aifsn;
 443         u8 cw_min;
 444         __le16 cw_max;
 445         __le16 tx_op_limit;
 446 } __packed;
 447
 448 struct acx_tid_config {
 449         struct acx_header header;
 450         u8 role_id;
 451         u8 queue_id;
 452         u8 channel_type;
 453         u8 tsid;
 454         u8 ps_scheme;
 455         u8 ack_policy;
 456         u8 padding[2];
 457         __le32 apsd_conf[2];
 458 } __packed;
 459
 460 struct acx_frag_threshold {
 461         struct acx_header header;
 462         __le16 frag_threshold;
 463         u8 padding[2];
 464 } __packed;
 465
 466 struct acx_tx_config_options {
 467         struct acx_header header;
 468         __le16 tx_compl_timeout;     /* msec */
 469         __le16 tx_compl_threshold;   /* number of packets */
 470 } __packed;
 471
 472 struct wl12xx_acx_config_memory {
 473         struct acx_header header;
 474
 475         u8 rx_mem_block_num;
 476         u8 tx_min_mem_block_num;
 477         u8 num_stations;
 478         u8 num_ssid_profiles;
 479         __le32 total_tx_descriptors;
 480         u8 dyn_mem_enable;
 481         u8 tx_free_req;
 482         u8 rx_free_req;
 483         u8 tx_min;
 484         u8 fwlog_blocks;
 485         u8 padding[3];
 486 } __packed;
 487
 488 struct wl1271_acx_mem_map {
 489         struct acx_header header;
 490
 491         __le32 code_start;
 492         __le32 code_end;
 493
 494         __le32 wep_defkey_start;
 495         __le32 wep_defkey_end;
 496
 497         __le32 sta_table_start;
 498         __le32 sta_table_end;
 499
 500         __le32 packet_template_start;
 501         __le32 packet_template_end;
 502
 503         /* Address of the TX result interface (control block) */
 504         __le32 tx_result;
 505         __le32 tx_result_queue_start;
 506
 507         __le32 queue_memory_start;
 508         __le32 queue_memory_end;
 509
 510         __le32 packet_memory_pool_start;
 511         __le32 packet_memory_pool_end;
 512
 513         __le32 debug_buffer1_start;
 514         __le32 debug_buffer1_end;
 515
 516         __le32 debug_buffer2_start;
 517         __le32 debug_buffer2_end;
 518
 519         /* Number of blocks FW allocated for TX packets */
 520         __le32 num_tx_mem_blocks;
 521
 522         /* Number of blocks FW allocated for RX packets */
 523         __le32 num_rx_mem_blocks;
 524
 525         /* the following 4 fields are valid in SLAVE mode only */
 526         u8 *tx_cbuf;
 527         u8 *rx_cbuf;
 528         __le32 rx_ctrl;
 529         __le32 tx_ctrl;
 530 } __packed;
 531
 532 struct wl1271_acx_rx_config_opt {
 533         struct acx_header header;
 534
 535         __le16 mblk_threshold;
 536         __le16 threshold;
 537         __le16 timeout;
 538         u8 queue_type;
 539         u8 reserved;
 540 } __packed;
 541
 542
 543 struct wl1271_acx_bet_enable {
 544         struct acx_header header;
 545
 546         u8 role_id;
 547         u8 enable;
 548         u8 max_consecutive;
 549         u8 padding[1];
 550 } __packed;
 551
 552 #define ACX_IPV4_VERSION 4
 553 #define ACX_IPV6_VERSION 6
 554 #define ACX_IPV4_ADDR_SIZE 4
 555
 556 /* bitmap of enabled arp_filter features */
 557 #define ACX_ARP_FILTER_ARP_FILTERING    BIT(0)
 558 #define ACX_ARP_FILTER_AUTO_ARP         BIT(1)
 559
 560 struct wl1271_acx_arp_filter {
 561         struct acx_header header;
 562         u8 role_id;
 563         u8 version;         /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
 564         u8 enable;          /* bitmap of enabled ARP filtering features */
 565         u8 padding[1];
 566         u8 address[16];     /* The configured device IP address - all ARP
 567                                requests directed to this IP address will pass
 568                                through. For IPv4, the first four bytes are
 569                                used. */
 570 } __packed;
 571
 572 struct wl1271_acx_pm_config {
 573         struct acx_header header;
 574
 575         __le32 host_clk_settling_time;
 576         u8 host_fast_wakeup_support;
 577         u8 padding[3];
 578 } __packed;
 579
 580 struct wl1271_acx_keep_alive_mode {
 581         struct acx_header header;
 582
 583         u8 role_id;
 584         u8 enabled;
 585         u8 padding[2];
 586 } __packed;
 587
 588 enum {
 589         ACX_KEEP_ALIVE_NO_TX = 0,
 590         ACX_KEEP_ALIVE_PERIOD_ONLY
 591 };
 592
 593 enum {
 594         ACX_KEEP_ALIVE_TPL_INVALID = 0,
 595         ACX_KEEP_ALIVE_TPL_VALID
 596 };
 597
 598 struct wl1271_acx_keep_alive_config {
 599         struct acx_header header;
 600
 601         u8 role_id;
 602         u8 index;
 603         u8 tpl_validation;
 604         u8 trigger;
 605         __le32 period;
 606 } __packed;
 607
 608 /* TODO: maybe this needs to be moved somewhere else? */
 609 #define HOST_IF_CFG_RX_FIFO_ENABLE     BIT(0)
 610 #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1)
 611 #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3)
 612 #define HOST_IF_CFG_RX_PAD_TO_SDIO_BLK BIT(4)
 613 #define HOST_IF_CFG_ADD_RX_ALIGNMENT   BIT(6)
 614
 615 enum {
 616         WL1271_ACX_TRIG_TYPE_LEVEL = 0,
 617         WL1271_ACX_TRIG_TYPE_EDGE,
 618 };
 619
 620 enum {
 621         WL1271_ACX_TRIG_DIR_LOW = 0,
 622         WL1271_ACX_TRIG_DIR_HIGH,
 623         WL1271_ACX_TRIG_DIR_BIDIR,
 624 };
 625
 626 enum {
 627         WL1271_ACX_TRIG_ENABLE = 1,
 628         WL1271_ACX_TRIG_DISABLE,
 629 };
 630
 631 enum {
 632         WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
 633         WL1271_ACX_TRIG_METRIC_RSSI_DATA,
 634         WL1271_ACX_TRIG_METRIC_SNR_BEACON,
 635         WL1271_ACX_TRIG_METRIC_SNR_DATA,
 636 };
 637
 638 enum {
 639         WL1271_ACX_TRIG_IDX_RSSI = 0,
 640         WL1271_ACX_TRIG_COUNT = 8,
 641 };
 642
 643 struct wl1271_acx_rssi_snr_trigger {
 644         struct acx_header header;
 645
 646         u8 role_id;
 647         u8 metric;
 648         u8 type;
 649         u8 dir;
 650         __le16 threshold;
 651         __le16 pacing; /* 0 - 60000 ms */
 652         u8 hysteresis;
 653         u8 index;
 654         u8 enable;
 655         u8 padding[1];
 656 };
 657
 658 struct wl1271_acx_rssi_snr_avg_weights {
 659         struct acx_header header;
 660
 661         u8 role_id;
 662         u8 padding[3];
 663         u8 rssi_beacon;
 664         u8 rssi_data;
 665         u8 snr_beacon;
 666         u8 snr_data;
 667 };
 668
 669
 670 /* special capability bit (not employed by the 802.11n spec) */
 671 #define WL12XX_HT_CAP_HT_OPERATION BIT(16)
 672
 673 /*
 674  * ACX_PEER_HT_CAP
 675  * Configure HT capabilities - declare the capabilities of the peer
 676  * we are connected to.
 677  */
 678 struct wl1271_acx_ht_capabilities {
 679         struct acx_header header;
 680
 681         /* bitmask of capability bits supported by the peer */
 682         __le32 ht_capabilites;
 683
 684         /* Indicates to which link these capabilities apply. */
 685         u8 hlid;
 686
 687         /*
 688          * This the maximum A-MPDU length supported by the AP. The FW may not
 689          * exceed this length when sending A-MPDUs
 690          */
 691         u8 ampdu_max_length;
 692
 693         /* This is the minimal spacing required when sending A-MPDUs to the AP*/
 694         u8 ampdu_min_spacing;
 695
 696         u8 padding;
 697 } __packed;
 698
 699 /*
 700  * ACX_HT_BSS_OPERATION
 701  * Configure HT capabilities - AP rules for behavior in the BSS.
 702  */
 703 struct wl1271_acx_ht_information {
 704         struct acx_header header;
 705
 706         u8 role_id;
 707
 708         /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
 709         u8 rifs_mode;
 710
 711         /* Values: 0 - 3 like in spec */
 712         u8 ht_protection;
 713
 714         /* Values: 0 - GF protection not required, 1 - GF protection required */
 715         u8 gf_protection;
 716
 717         /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
 718         u8 ht_tx_burst_limit;
 719
 720         /*
 721          * Values: 0 - Dual CTS protection not required,
 722          *         1 - Dual CTS Protection required
 723          * Note: When this value is set to 1 FW will protect all TXOP with RTS
 724          * frame and will not use CTS-to-self regardless of the value of the
 725          * ACX_CTS_PROTECTION information element
 726          */
 727         u8 dual_cts_protection;
 728
 729         u8 padding[2];
 730 } __packed;
 731
 732 struct wl1271_acx_ba_initiator_policy {
 733         struct acx_header header;
 734
 735         /* Specifies role Id, Range 0-7, 0xFF means ANY role. */
 736         u8 role_id;
 737
 738         /*
 739          * Per TID setting for allowing TX BA. Set a bit to 1 to allow
 740          * TX BA sessions for the corresponding TID.
 741          */
 742         u8 tid_bitmap;
 743
 744         /* Windows size in number of packets */
 745         u8 win_size;
 746
 747         u8 padding1[1];
 748
 749         /* As initiator inactivity timeout in time units(TU) of 1024us */
 750         u16 inactivity_timeout;
 751
 752         u8 padding[2];
 753 } __packed;
 754
 755 struct wl1271_acx_ba_receiver_setup {
 756         struct acx_header header;
 757
 758         /* Specifies link id, range 0-31 */
 759         u8 hlid;
 760
 761         u8 tid;
 762
 763         u8 enable;
 764
 765         /* Windows size in number of packets */
 766         u8 win_size;
 767
 768         /* BA session starting sequence number.  RANGE 0-FFF */
 769         u16 ssn;
 770
 771         u8 padding[2];
 772 } __packed;
 773
 774 struct wl12xx_acx_fw_tsf_information {
 775         struct acx_header header;
 776
 777         u8 role_id;
 778         u8 padding1[3];
 779         __le32 current_tsf_high;
 780         __le32 current_tsf_low;
 781         __le32 last_bttt_high;
 782         __le32 last_tbtt_low;
 783         u8 last_dtim_count;
 784         u8 padding2[3];
 785 } __packed;
 786
 787 struct wl1271_acx_ps_rx_streaming {
 788         struct acx_header header;
 789
 790         u8 role_id;
 791         u8 tid;
 792         u8 enable;
 793
 794         /* interval between triggers (10-100 msec) */
 795         u8 period;
 796
 797         /* timeout before first trigger (0-200 msec) */
 798         u8 timeout;
 799         u8 padding[3];
 800 } __packed;
 801
 802 struct wl1271_acx_ap_max_tx_retry {
 803         struct acx_header header;
 804
 805         u8 role_id;
 806         u8 padding_1;
 807
 808         /*
 809          * the number of frames transmission failures before
 810          * issuing the aging event.
 811          */
 812         __le16 max_tx_retry;
 813 } __packed;
 814
 815 struct wl1271_acx_config_ps {
 816         struct acx_header header;
 817
 818         u8 exit_retries;
 819         u8 enter_retries;
 820         u8 padding[2];
 821         __le32 null_data_rate;
 822 } __packed;
 823
 824 struct wl1271_acx_inconnection_sta {
 825         struct acx_header header;
 826
 827         u8 addr[ETH_ALEN];
 828         u8 role_id;
 829         u8 padding;
 830 } __packed;
 831
 832 /*
 833  * ACX_FM_COEX_CFG
 834  * set the FM co-existence parameters.
 835  */
 836 struct wl1271_acx_fm_coex {
 837         struct acx_header header;
 838         /* enable(1) / disable(0) the FM Coex feature */
 839         u8 enable;
 840         /*
 841          * Swallow period used in COEX PLL swallowing mechanism.
 842          * 0xFF = use FW default
 843          */
 844         u8 swallow_period;
 845         /*
 846          * The N divider used in COEX PLL swallowing mechanism for Fref of
 847          * 38.4/19.2 Mhz. 0xFF = use FW default
 848          */
 849         u8 n_divider_fref_set_1;
 850         /*
 851          * The N divider used in COEX PLL swallowing mechanism for Fref of
 852          * 26/52 Mhz. 0xFF = use FW default
 853          */
 854         u8 n_divider_fref_set_2;
 855         /*
 856          * The M divider used in COEX PLL swallowing mechanism for Fref of
 857          * 38.4/19.2 Mhz. 0xFFFF = use FW default
 858          */
 859         __le16 m_divider_fref_set_1;
 860         /*
 861          * The M divider used in COEX PLL swallowing mechanism for Fref of
 862          * 26/52 Mhz. 0xFFFF = use FW default
 863          */
 864         __le16 m_divider_fref_set_2;
 865         /*
 866          * The time duration in uSec required for COEX PLL to stabilize.
 867          * 0xFFFFFFFF = use FW default
 868          */
 869         __le32 coex_pll_stabilization_time;
 870         /*
 871          * The time duration in uSec required for LDO to stabilize.
 872          * 0xFFFFFFFF = use FW default
 873          */
 874         __le16 ldo_stabilization_time;
 875         /*
 876          * The disturbed frequency band margin around the disturbed frequency
 877          * center (single sided).
 878          * For example, if 2 is configured, the following channels will be
 879          * considered disturbed channel:
 880          *   80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH
 881          * 0xFF = use FW default
 882          */
 883         u8 fm_disturbed_band_margin;
 884         /*
 885          * The swallow clock difference of the swallowing mechanism.
 886          * 0xFF = use FW default
 887          */
 888         u8 swallow_clk_diff;
 889 } __packed;
 890
 891 #define ACX_RATE_MGMT_ALL_PARAMS 0xff
 892 struct wl12xx_acx_set_rate_mgmt_params {
 893         struct acx_header header;
 894
 895         u8 index; /* 0xff to configure all params */
 896         u8 padding1;
 897         __le16 rate_retry_score;
 898         __le16 per_add;
 899         __le16 per_th1;
 900         __le16 per_th2;
 901         __le16 max_per;
 902         u8 inverse_curiosity_factor;
 903         u8 tx_fail_low_th;
 904         u8 tx_fail_high_th;
 905         u8 per_alpha_shift;
 906         u8 per_add_shift;
 907         u8 per_beta1_shift;
 908         u8 per_beta2_shift;
 909         u8 rate_check_up;
 910         u8 rate_check_down;
 911         u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
 912         u8 padding2[2];
 913 } __packed;
 914
 915 struct wl12xx_acx_config_hangover {
 916         struct acx_header header;
 917
 918         __le32 recover_time;
 919         u8 hangover_period;
 920         u8 dynamic_mode;
 921         u8 early_termination_mode;
 922         u8 max_period;
 923         u8 min_period;
 924         u8 increase_delta;
 925         u8 decrease_delta;
 926         u8 quiet_time;
 927         u8 increase_time;
 928         u8 window_size;
 929         u8 padding[2];
 930 } __packed;
 931
 932
 933 struct acx_default_rx_filter {
 934         struct acx_header header;
 935         u8 enable;
 936
 937         /* action of type FILTER_XXX */
 938         u8 default_action;
 939
 940         u8 pad[2];
 941 } __packed;
 942
 943
 944 struct acx_rx_filter_cfg {
 945         struct acx_header header;
 946
 947         u8 enable;
 948
 949         /* 0 - WL1271_MAX_RX_FILTERS-1 */
 950         u8 index;
 951
 952         u8 action;
 953
 954         u8 num_fields;
 955         u8 fields[0];
 956 } __packed;
 957
 958 struct acx_roaming_stats {
 959         struct acx_header header;
 960
 961         u8      role_id;
 962         u8      pad[3];
 963         u32     missed_beacons;
 964         u8      snr_data;
 965         u8      snr_bacon;
 966         s8      rssi_data;
 967         s8      rssi_beacon;
 968 } __packed;
 969
 970 enum {
 971         ACX_WAKE_UP_CONDITIONS           = 0x0000,
 972         ACX_MEM_CFG                      = 0x0001,
 973         ACX_SLOT                         = 0x0002,
 974         ACX_AC_CFG                       = 0x0003,
 975         ACX_MEM_MAP                      = 0x0004,
 976         ACX_AID                          = 0x0005,
 977         ACX_MEDIUM_USAGE                 = 0x0006,
 978         ACX_STATISTICS                   = 0x0007,
 979         ACX_PWR_CONSUMPTION_STATISTICS   = 0x0008,
 980         ACX_TID_CFG                      = 0x0009,
 981         ACX_PS_RX_STREAMING              = 0x000A,
 982         ACX_BEACON_FILTER_OPT            = 0x000B,
 983         ACX_NOISE_HIST                   = 0x000C,
 984         ACX_HDK_VERSION                  = 0x000D,
 985         ACX_PD_THRESHOLD                 = 0x000E,
 986         ACX_TX_CONFIG_OPT                = 0x000F,
 987         ACX_CCA_THRESHOLD                = 0x0010,
 988         ACX_EVENT_MBOX_MASK              = 0x0011,
 989         ACX_CONN_MONIT_PARAMS            = 0x0012,
 990         ACX_DISABLE_BROADCASTS           = 0x0013,
 991         ACX_BCN_DTIM_OPTIONS             = 0x0014,
 992         ACX_SG_ENABLE                    = 0x0015,
 993         ACX_SG_CFG                       = 0x0016,
 994         ACX_FM_COEX_CFG                  = 0x0017,
 995         ACX_BEACON_FILTER_TABLE          = 0x0018,
 996         ACX_ARP_IP_FILTER                = 0x0019,
 997         ACX_ROAMING_STATISTICS_TBL       = 0x001A,
 998         ACX_RATE_POLICY                  = 0x001B,
 999         ACX_CTS_PROTECTION               = 0x001C,
1000         ACX_SLEEP_AUTH                   = 0x001D,
1001         ACX_PREAMBLE_TYPE                = 0x001E,
1002         ACX_ERROR_CNT                    = 0x001F,
1003         ACX_IBSS_FILTER                  = 0x0020,
1004         ACX_SERVICE_PERIOD_TIMEOUT       = 0x0021,
1005         ACX_TSF_INFO                     = 0x0022,
1006         ACX_CONFIG_PS_WMM                = 0x0023,
1007         ACX_ENABLE_RX_DATA_FILTER        = 0x0024,
1008         ACX_SET_RX_DATA_FILTER           = 0x0025,
1009         ACX_GET_DATA_FILTER_STATISTICS   = 0x0026,
1010         ACX_RX_CONFIG_OPT                = 0x0027,
1011         ACX_FRAG_CFG                     = 0x0028,
1012         ACX_BET_ENABLE                   = 0x0029,
1013         ACX_RSSI_SNR_TRIGGER             = 0x002A,
1014         ACX_RSSI_SNR_WEIGHTS             = 0x002B,
1015         ACX_KEEP_ALIVE_MODE              = 0x002C,
1016         ACX_SET_KEEP_ALIVE_CONFIG        = 0x002D,
1017         ACX_BA_SESSION_INIT_POLICY       = 0x002E,
1018         ACX_BA_SESSION_RX_SETUP          = 0x002F,
1019         ACX_PEER_HT_CAP                  = 0x0030,
1020         ACX_HT_BSS_OPERATION             = 0x0031,
1021         ACX_COEX_ACTIVITY                = 0x0032,
1022         ACX_BURST_MODE                   = 0x0033,
1023         ACX_SET_RATE_MGMT_PARAMS         = 0x0034,
1024         ACX_GET_RATE_MGMT_PARAMS         = 0x0035,
1025         ACX_SET_RATE_ADAPT_PARAMS        = 0x0036,
1026         ACX_SET_DCO_ITRIM_PARAMS         = 0x0037,
1027         ACX_GEN_FW_CMD                   = 0x0038,
1028         ACX_HOST_IF_CFG_BITMAP           = 0x0039,
1029         ACX_MAX_TX_FAILURE               = 0x003A,
1030         ACX_UPDATE_INCONNECTION_STA_LIST = 0x003B,
1031         DOT11_RX_MSDU_LIFE_TIME          = 0x003C,
1032         DOT11_CUR_TX_PWR                 = 0x003D,
1033         DOT11_RTS_THRESHOLD              = 0x003E,
1034         DOT11_GROUP_ADDRESS_TBL          = 0x003F,
1035         ACX_PM_CONFIG                    = 0x0040,
1036         ACX_CONFIG_PS                    = 0x0041,
1037         ACX_CONFIG_HANGOVER              = 0x0042,
1038         ACX_FEATURE_CFG                  = 0x0043,
1039         ACX_PROTECTION_CFG               = 0x0044,
1040 };
1041
1042
1043 int wl1271_acx_wake_up_conditions(struct wl1271 *wl,
1044                                   struct wl12xx_vif *wlvif,
1045                                   u8 wake_up_event, u8 listen_interval);
1046 int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1047 int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1048                         int power);
1049 int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1050 int wl1271_acx_mem_map(struct wl1271 *wl,
1051                        struct acx_header *mem_map, size_t len);
1052 int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1053 int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1054                     enum acx_slot_type slot_time);
1055 int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1056                                  bool enable, void *mc_list, u32 mc_list_len);
1057 int wl1271_acx_service_period_timeout(struct wl1271 *wl,
1058                                       struct wl12xx_vif *wlvif);
1059 int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1060                              u32 rts_threshold);
1061 int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1062 int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1063                                  bool enable_filter);
1064 int wl1271_acx_beacon_filter_table(struct wl1271 *wl,
1065                                    struct wl12xx_vif *wlvif);
1066 int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1067                                  bool enable);
1068 int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1069 int wl12xx_acx_sg_cfg(struct wl1271 *wl);
1070 int wl1271_acx_cca_threshold(struct wl1271 *wl);
1071 int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1072 int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid);
1073 int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1074 int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1075                             enum acx_preamble_type preamble);
1076 int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1077                            enum acx_ctsprotect_type ctsprotect);
1078 int wl1271_acx_statistics(struct wl1271 *wl, void *stats);
1079 int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1080 int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c,
1081                       u8 idx);
1082 int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1083                       u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop);
1084 int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1085                        u8 queue_id, u8 channel_type,
1086                        u8 tsid, u8 ps_scheme, u8 ack_policy,
1087                        u32 apsd_conf0, u32 apsd_conf1);
1088 int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold);
1089 int wl1271_acx_tx_config_options(struct wl1271 *wl);
1090 int wl12xx_acx_mem_cfg(struct wl1271 *wl);
1091 int wl1271_acx_init_mem_config(struct wl1271 *wl);
1092 int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1093 int wl1271_acx_smart_reflex(struct wl1271 *wl);
1094 int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1095                           bool enable);
1096 int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1097                              u8 enable, __be32 address);
1098 int wl1271_acx_pm_config(struct wl1271 *wl);
1099 int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif,
1100                                bool enable);
1101 int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1102                                  u8 index, u8 tpl_valid);
1103 int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1104                                 bool enable, s16 thold, u8 hyst);
1105 int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl,
1106                                     struct wl12xx_vif *wlvif);
1107 int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
1108                                     struct ieee80211_sta_ht_cap *ht_cap,
1109                                     bool allow_ht_operation, u8 hlid);
1110 int wl1271_acx_set_ht_information(struct wl1271 *wl,
1111                                    struct wl12xx_vif *wlvif,
1112                                    u16 ht_operation_mode);
1113 int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl,
1114                                        struct wl12xx_vif *wlvif);
1115 int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index,
1116                                        u16 ssn, bool enable, u8 peer_hlid,
1117                                        u8 win_size);
1118 int wl12xx_acx_tsf_info(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1119                         u64 *mactime);
1120 int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1121                                bool enable);
1122 int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1123 int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1124 int wl1271_acx_set_inconnection_sta(struct wl1271 *wl,
1125                                     struct wl12xx_vif *wlvif, u8 *addr);
1126 int wl1271_acx_fm_coex(struct wl1271 *wl);
1127 int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl);
1128 int wl12xx_acx_config_hangover(struct wl1271 *wl);
1129 int wlcore_acx_average_rssi(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1130                             s8 *avg_rssi);
1131
1132 int wl1271_acx_default_rx_filter_enable(struct wl1271 *wl, bool enable,
1133                                         enum rx_filter_action action);
1134 int wl1271_acx_set_rx_filter(struct wl1271 *wl, u8 index, bool enable,
1135                              struct wl12xx_rx_filter *filter);
1136 #endif /* __WL1271_ACX_H__ */