drivers/pinctrl/sh-pfc/core.c

   1 /*
   2  * Pin Control and GPIO driver for SuperH Pin Function Controller.
   3  *
   4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  * Copyright (C) 2009 - 2012 Paul Mundt
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #define DRV_NAME "sh-pfc"
  15
  16 #include <linux/bitops.h>
  17 #include <linux/err.h>
  18 #include <linux/errno.h>
  19 #include <linux/io.h>
  20 #include <linux/ioport.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/pinctrl/machine.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/psci.h>
  28 #include <linux/slab.h>
  29
  30 #include "core.h"
  31
  32 static int sh_pfc_map_resources(struct sh_pfc *pfc,
  33                                 struct platform_device *pdev)
  34 {
  35         unsigned int num_windows, num_irqs;
  36         struct sh_pfc_window *windows;
  37         unsigned int *irqs = NULL;
  38         struct resource *res;
  39         unsigned int i;
  40         int irq;
  41
  42         /* Count the MEM and IRQ resources. */
  43         for (num_windows = 0;; num_windows++) {
  44                 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
  45                 if (!res)
  46                         break;
  47         }
  48         for (num_irqs = 0;; num_irqs++) {
  49                 irq = platform_get_irq(pdev, num_irqs);
  50                 if (irq == -EPROBE_DEFER)
  51                         return irq;
  52                 if (irq < 0)
  53                         break;
  54         }
  55
  56         if (num_windows == 0)
  57                 return -EINVAL;
  58
  59         /* Allocate memory windows and IRQs arrays. */
  60         windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
  61                                GFP_KERNEL);
  62         if (windows == NULL)
  63                 return -ENOMEM;
  64
  65         pfc->num_windows = num_windows;
  66         pfc->windows = windows;
  67
  68         if (num_irqs) {
  69                 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
  70                                     GFP_KERNEL);
  71                 if (irqs == NULL)
  72                         return -ENOMEM;
  73
  74                 pfc->num_irqs = num_irqs;
  75                 pfc->irqs = irqs;
  76         }
  77
  78         /* Fill them. */
  79         for (i = 0; i < num_windows; i++) {
  80                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  81                 windows->phys = res->start;
  82                 windows->size = resource_size(res);
  83                 windows->virt = devm_ioremap_resource(pfc->dev, res);
  84                 if (IS_ERR(windows->virt))
  85                         return -ENOMEM;
  86                 windows++;
  87         }
  88         for (i = 0; i < num_irqs; i++)
  89                 *irqs++ = platform_get_irq(pdev, i);
  90
  91         return 0;
  92 }
  93
  94 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
  95 {
  96         struct sh_pfc_window *window;
  97         phys_addr_t address = reg;
  98         unsigned int i;
  99
 100         /* scan through physical windows and convert address */
 101         for (i = 0; i < pfc->num_windows; i++) {
 102                 window = pfc->windows + i;
 103
 104                 if (address < window->phys)
 105                         continue;
 106
 107                 if (address >= (window->phys + window->size))
 108                         continue;
 109
 110                 return window->virt + (address - window->phys);
 111         }
 112
 113         BUG();
 114         return NULL;
 115 }
 116
 117 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
 118 {
 119         unsigned int offset;
 120         unsigned int i;
 121
 122         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
 123                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 124
 125                 if (pin <= range->end)
 126                         return pin >= range->start
 127                              ? offset + pin - range->start : -1;
 128
 129                 offset += range->end - range->start + 1;
 130         }
 131
 132         return -EINVAL;
 133 }
 134
 135 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
 136 {
 137         if (enum_id < r->begin)
 138                 return 0;
 139
 140         if (enum_id > r->end)
 141                 return 0;
 142
 143         return 1;
 144 }
 145
 146 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
 147 {
 148         switch (reg_width) {
 149         case 8:
 150                 return ioread8(mapped_reg);
 151         case 16:
 152                 return ioread16(mapped_reg);
 153         case 32:
 154                 return ioread32(mapped_reg);
 155         }
 156
 157         BUG();
 158         return 0;
 159 }
 160
 161 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 162                           u32 data)
 163 {
 164         switch (reg_width) {
 165         case 8:
 166                 iowrite8(data, mapped_reg);
 167                 return;
 168         case 16:
 169                 iowrite16(data, mapped_reg);
 170                 return;
 171         case 32:
 172                 iowrite32(data, mapped_reg);
 173                 return;
 174         }
 175
 176         BUG();
 177 }
 178
 179 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 180 {
 181         return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
 182 }
 183
 184 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 185 {
 186         if (pfc->info->unlock_reg)
 187                 sh_pfc_write_raw_reg(
 188                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 189                         ~data);
 190
 191         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
 192 }
 193
 194 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 195                                      const struct pinmux_cfg_reg *crp,
 196                                      unsigned int in_pos,
 197                                      void __iomem **mapped_regp, u32 *maskp,
 198                                      unsigned int *posp)
 199 {
 200         unsigned int k;
 201
 202         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 203
 204         if (crp->field_width) {
 205                 *maskp = (1 << crp->field_width) - 1;
 206                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 207         } else {
 208                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 209                 *posp = crp->reg_width;
 210                 for (k = 0; k <= in_pos; k++)
 211                         *posp -= crp->var_field_width[k];
 212         }
 213 }
 214
 215 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 216                                     const struct pinmux_cfg_reg *crp,
 217                                     unsigned int field, u32 value)
 218 {
 219         void __iomem *mapped_reg;
 220         unsigned int pos;
 221         u32 mask, data;
 222
 223         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 224
 225         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 226                 "r_width = %u, f_width = %u\n",
 227                 crp->reg, value, field, crp->reg_width, crp->field_width);
 228
 229         mask = ~(mask << pos);
 230         value = value << pos;
 231
 232         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 233         data &= mask;
 234         data |= value;
 235
 236         if (pfc->info->unlock_reg)
 237                 sh_pfc_write_raw_reg(
 238                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 239                         ~data);
 240
 241         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 242 }
 243
 244 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 245                                  const struct pinmux_cfg_reg **crp,
 246                                  unsigned int *fieldp, u32 *valuep)
 247 {
 248         unsigned int k = 0;
 249
 250         while (1) {
 251                 const struct pinmux_cfg_reg *config_reg =
 252                         pfc->info->cfg_regs + k;
 253                 unsigned int r_width = config_reg->reg_width;
 254                 unsigned int f_width = config_reg->field_width;
 255                 unsigned int curr_width;
 256                 unsigned int bit_pos;
 257                 unsigned int pos = 0;
 258                 unsigned int m = 0;
 259
 260                 if (!r_width)
 261                         break;
 262
 263                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 264                         u32 ncomb;
 265                         u32 n;
 266
 267                         if (f_width)
 268                                 curr_width = f_width;
 269                         else
 270                                 curr_width = config_reg->var_field_width[m];
 271
 272                         ncomb = 1 << curr_width;
 273                         for (n = 0; n < ncomb; n++) {
 274                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 275                                         *crp = config_reg;
 276                                         *fieldp = m;
 277                                         *valuep = n;
 278                                         return 0;
 279                                 }
 280                         }
 281                         pos += ncomb;
 282                         m++;
 283                 }
 284                 k++;
 285         }
 286
 287         return -EINVAL;
 288 }
 289
 290 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 291                               u16 *enum_idp)
 292 {
 293         const u16 *data = pfc->info->pinmux_data;
 294         unsigned int k;
 295
 296         if (pos) {
 297                 *enum_idp = data[pos + 1];
 298                 return pos + 1;
 299         }
 300
 301         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 302                 if (data[k] == mark) {
 303                         *enum_idp = data[k + 1];
 304                         return k + 1;
 305                 }
 306         }
 307
 308         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 309                 mark);
 310         return -EINVAL;
 311 }
 312
 313 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 314 {
 315         const struct pinmux_range *range;
 316         int pos = 0;
 317
 318         switch (pinmux_type) {
 319         case PINMUX_TYPE_GPIO:
 320         case PINMUX_TYPE_FUNCTION:
 321                 range = NULL;
 322                 break;
 323
 324         case PINMUX_TYPE_OUTPUT:
 325                 range = &pfc->info->output;
 326                 break;
 327
 328         case PINMUX_TYPE_INPUT:
 329                 range = &pfc->info->input;
 330                 break;
 331
 332         default:
 333                 return -EINVAL;
 334         }
 335
 336         /* Iterate over all the configuration fields we need to update. */
 337         while (1) {
 338                 const struct pinmux_cfg_reg *cr;
 339                 unsigned int field;
 340                 u16 enum_id;
 341                 u32 value;
 342                 int in_range;
 343                 int ret;
 344
 345                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 346                 if (pos < 0)
 347                         return pos;
 348
 349                 if (!enum_id)
 350                         break;
 351
 352                 /* Check if the configuration field selects a function. If it
 353                  * doesn't, skip the field if it's not applicable to the
 354                  * requested pinmux type.
 355                  */
 356                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 357                 if (!in_range) {
 358                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 359                                 /* Functions are allowed to modify all
 360                                  * fields.
 361                                  */
 362                                 in_range = 1;
 363                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 364                                 /* Input/output types can only modify fields
 365                                  * that correspond to their respective ranges.
 366                                  */
 367                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 368
 369                                 /*
 370                                  * special case pass through for fixed
 371                                  * input-only or output-only pins without
 372                                  * function enum register association.
 373                                  */
 374                                 if (in_range && enum_id == range->force)
 375                                         continue;
 376                         }
 377                         /* GPIOs are only allowed to modify function fields. */
 378                 }
 379
 380                 if (!in_range)
 381                         continue;
 382
 383                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 384                 if (ret < 0)
 385                         return ret;
 386
 387                 sh_pfc_write_config_reg(pfc, cr, field, value);
 388         }
 389
 390         return 0;
 391 }
 392
 393 const struct pinmux_bias_reg *
 394 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
 395                        unsigned int *bit)
 396 {
 397         unsigned int i, j;
 398
 399         for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 400                 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
 401                         if (pfc->info->bias_regs[i].pins[j] == pin) {
 402                                 *bit = j;
 403                                 return &pfc->info->bias_regs[i];
 404                         }
 405                 }
 406         }
 407
 408         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 409
 410         return NULL;
 411 }
 412
 413 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 414 {
 415         struct sh_pfc_pin_range *range;
 416         unsigned int nr_ranges;
 417         unsigned int i;
 418
 419         if (pfc->info->pins[0].pin == (u16)-1) {
 420                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 421                  * in its pin arrays yet. Consider the pin numbers range as
 422                  * continuous and allocate a single range.
 423                  */
 424                 pfc->nr_ranges = 1;
 425                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
 426                                            GFP_KERNEL);
 427                 if (pfc->ranges == NULL)
 428                         return -ENOMEM;
 429
 430                 pfc->ranges->start = 0;
 431                 pfc->ranges->end = pfc->info->nr_pins - 1;
 432                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 433
 434                 return 0;
 435         }
 436
 437         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 438          * be sorted by pin numbers, and pins without a GPIO port must come
 439          * last.
 440          */
 441         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 442                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 443                         nr_ranges++;
 444         }
 445
 446         pfc->nr_ranges = nr_ranges;
 447         pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
 448                                    GFP_KERNEL);
 449         if (pfc->ranges == NULL)
 450                 return -ENOMEM;
 451
 452         range = pfc->ranges;
 453         range->start = pfc->info->pins[0].pin;
 454
 455         for (i = 1; i < pfc->info->nr_pins; ++i) {
 456                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 457                         continue;
 458
 459                 range->end = pfc->info->pins[i-1].pin;
 460                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 461                         pfc->nr_gpio_pins = range->end + 1;
 462
 463                 range++;
 464                 range->start = pfc->info->pins[i].pin;
 465         }
 466
 467         range->end = pfc->info->pins[i-1].pin;
 468         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 469                 pfc->nr_gpio_pins = range->end + 1;
 470
 471         return 0;
 472 }
 473
 474 #ifdef CONFIG_OF
 475 static const struct of_device_id sh_pfc_of_table[] = {
 476 #ifdef CONFIG_PINCTRL_PFC_EMEV2
 477         {
 478                 .compatible = "renesas,pfc-emev2",
 479                 .data = &emev2_pinmux_info,
 480         },
 481 #endif
 482 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 483         {
 484                 .compatible = "renesas,pfc-r8a73a4",
 485                 .data = &r8a73a4_pinmux_info,
 486         },
 487 #endif
 488 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 489         {
 490                 .compatible = "renesas,pfc-r8a7740",
 491                 .data = &r8a7740_pinmux_info,
 492         },
 493 #endif
 494 #ifdef CONFIG_PINCTRL_PFC_R8A7743
 495         {
 496                 .compatible = "renesas,pfc-r8a7743",
 497                 .data = &r8a7743_pinmux_info,
 498         },
 499 #endif
 500 #ifdef CONFIG_PINCTRL_PFC_R8A7745
 501         {
 502                 .compatible = "renesas,pfc-r8a7745",
 503                 .data = &r8a7745_pinmux_info,
 504         },
 505 #endif
 506 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 507         {
 508                 .compatible = "renesas,pfc-r8a7778",
 509                 .data = &r8a7778_pinmux_info,
 510         },
 511 #endif
 512 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 513         {
 514                 .compatible = "renesas,pfc-r8a7779",
 515                 .data = &r8a7779_pinmux_info,
 516         },
 517 #endif
 518 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 519         {
 520                 .compatible = "renesas,pfc-r8a7790",
 521                 .data = &r8a7790_pinmux_info,
 522         },
 523 #endif
 524 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 525         {
 526                 .compatible = "renesas,pfc-r8a7791",
 527                 .data = &r8a7791_pinmux_info,
 528         },
 529 #endif
 530 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 531         {
 532                 .compatible = "renesas,pfc-r8a7792",
 533                 .data = &r8a7792_pinmux_info,
 534         },
 535 #endif
 536 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 537         {
 538                 .compatible = "renesas,pfc-r8a7793",
 539                 .data = &r8a7793_pinmux_info,
 540         },
 541 #endif
 542 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 543         {
 544                 .compatible = "renesas,pfc-r8a7794",
 545                 .data = &r8a7794_pinmux_info,
 546         },
 547 #endif
 548 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 549         {
 550                 .compatible = "renesas,pfc-r8a7795",
 551                 .data = &r8a7795_pinmux_info,
 552         },
 553 #endif
 554 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 555         {
 556                 .compatible = "renesas,pfc-r8a7796",
 557                 .data = &r8a7796_pinmux_info,
 558         },
 559 #endif
 560 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 561         {
 562                 .compatible = "renesas,pfc-r8a77970",
 563                 .data = &r8a77970_pinmux_info,
 564         },
 565 #endif
 566 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 567         {
 568                 .compatible = "renesas,pfc-r8a77995",
 569                 .data = &r8a77995_pinmux_info,
 570         },
 571 #endif
 572 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 573         {
 574                 .compatible = "renesas,pfc-sh73a0",
 575                 .data = &sh73a0_pinmux_info,
 576         },
 577 #endif
 578         { },
 579 };
 580 #endif
 581
 582 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
 583 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 584 {
 585 }
 586
 587 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 588 {
 589         pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
 590 }
 591
 592 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 593 {
 594         sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
 595 }
 596
 597 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
 598         void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
 599 {
 600         unsigned int i, n = 0;
 601
 602         if (pfc->info->cfg_regs)
 603                 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
 604                         do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
 605
 606         if (pfc->info->drive_regs)
 607                 for (i = 0; pfc->info->drive_regs[i].reg; i++)
 608                         do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
 609
 610         if (pfc->info->bias_regs)
 611                 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 612                         do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
 613                         if (pfc->info->bias_regs[i].pud)
 614                                 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
 615                 }
 616
 617         if (pfc->info->ioctrl_regs)
 618                 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
 619                         do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
 620
 621         return n;
 622 }
 623
 624 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
 625 {
 626         unsigned int n;
 627
 628         /* This is the best we can do to check for the presence of PSCI */
 629         if (!psci_ops.cpu_suspend)
 630                 return 0;
 631
 632         n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
 633         if (!n)
 634                 return 0;
 635
 636         pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
 637                                              sizeof(*pfc->saved_regs),
 638                                              GFP_KERNEL);
 639         if (!pfc->saved_regs)
 640                 return -ENOMEM;
 641
 642         dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
 643         return 0;
 644 }
 645
 646 static int sh_pfc_suspend_noirq(struct device *dev)
 647 {
 648         struct sh_pfc *pfc = dev_get_drvdata(dev);
 649
 650         if (pfc->saved_regs)
 651                 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
 652         return 0;
 653 }
 654
 655 static int sh_pfc_resume_noirq(struct device *dev)
 656 {
 657         struct sh_pfc *pfc = dev_get_drvdata(dev);
 658
 659         if (pfc->saved_regs)
 660                 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
 661         return 0;
 662 }
 663
 664 static const struct dev_pm_ops sh_pfc_pm  = {
 665         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
 666 };
 667 #define DEV_PM_OPS      &sh_pfc_pm
 668 #else
 669 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
 670 #define DEV_PM_OPS      NULL
 671 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
 672
 673 static int sh_pfc_probe(struct platform_device *pdev)
 674 {
 675 #ifdef CONFIG_OF
 676         struct device_node *np = pdev->dev.of_node;
 677 #endif
 678         const struct sh_pfc_soc_info *info;
 679         struct sh_pfc *pfc;
 680         int ret;
 681
 682 #ifdef CONFIG_OF
 683         if (np)
 684                 info = of_device_get_match_data(&pdev->dev);
 685         else
 686 #endif
 687                 info = (const void *)platform_get_device_id(pdev)->driver_data;
 688
 689         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
 690         if (pfc == NULL)
 691                 return -ENOMEM;
 692
 693         pfc->info = info;
 694         pfc->dev = &pdev->dev;
 695
 696         ret = sh_pfc_map_resources(pfc, pdev);
 697         if (unlikely(ret < 0))
 698                 return ret;
 699
 700         spin_lock_init(&pfc->lock);
 701
 702         if (info->ops && info->ops->init) {
 703                 ret = info->ops->init(pfc);
 704                 if (ret < 0)
 705                         return ret;
 706
 707                 /* .init() may have overridden pfc->info */
 708                 info = pfc->info;
 709         }
 710
 711         ret = sh_pfc_suspend_init(pfc);
 712         if (ret)
 713                 return ret;
 714
 715         /* Enable dummy states for those platforms without pinctrl support */
 716         if (!of_have_populated_dt())
 717                 pinctrl_provide_dummies();
 718
 719         ret = sh_pfc_init_ranges(pfc);
 720         if (ret < 0)
 721                 return ret;
 722
 723         /*
 724          * Initialize pinctrl bindings first
 725          */
 726         ret = sh_pfc_register_pinctrl(pfc);
 727         if (unlikely(ret != 0))
 728                 return ret;
 729
 730 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
 731         /*
 732          * Then the GPIO chip
 733          */
 734         ret = sh_pfc_register_gpiochip(pfc);
 735         if (unlikely(ret != 0)) {
 736                 /*
 737                  * If the GPIO chip fails to come up we still leave the
 738                  * PFC state as it is, given that there are already
 739                  * extant users of it that have succeeded by this point.
 740                  */
 741                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
 742         }
 743 #endif
 744
 745         platform_set_drvdata(pdev, pfc);
 746
 747         dev_info(pfc->dev, "%s support registered\n", info->name);
 748
 749         return 0;
 750 }
 751
 752 static const struct platform_device_id sh_pfc_id_table[] = {
 753 #ifdef CONFIG_PINCTRL_PFC_SH7203
 754         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 755 #endif
 756 #ifdef CONFIG_PINCTRL_PFC_SH7264
 757         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
 758 #endif
 759 #ifdef CONFIG_PINCTRL_PFC_SH7269
 760         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
 761 #endif
 762 #ifdef CONFIG_PINCTRL_PFC_SH7720
 763         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
 764 #endif
 765 #ifdef CONFIG_PINCTRL_PFC_SH7722
 766         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
 767 #endif
 768 #ifdef CONFIG_PINCTRL_PFC_SH7723
 769         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
 770 #endif
 771 #ifdef CONFIG_PINCTRL_PFC_SH7724
 772         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
 773 #endif
 774 #ifdef CONFIG_PINCTRL_PFC_SH7734
 775         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
 776 #endif
 777 #ifdef CONFIG_PINCTRL_PFC_SH7757
 778         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
 779 #endif
 780 #ifdef CONFIG_PINCTRL_PFC_SH7785
 781         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
 782 #endif
 783 #ifdef CONFIG_PINCTRL_PFC_SH7786
 784         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
 785 #endif
 786 #ifdef CONFIG_PINCTRL_PFC_SHX3
 787         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
 788 #endif
 789         { },
 790 };
 791
 792 static struct platform_driver sh_pfc_driver = {
 793         .probe          = sh_pfc_probe,
 794         .id_table       = sh_pfc_id_table,
 795         .driver         = {
 796                 .name   = DRV_NAME,
 797                 .of_match_table = of_match_ptr(sh_pfc_of_table),
 798                 .pm     = DEV_PM_OPS,
 799         },
 800 };
 801
 802 static int __init sh_pfc_init(void)
 803 {
 804         return platform_driver_register(&sh_pfc_driver);
 805 }
 806 postcore_initcall(sh_pfc_init);