?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795-es1.c
blob292e35d4d2f4931784c67ec996b57358dccd02b9
1 /*
2 * R8A7795 ES1.x processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11 #include <linux/kernel.h>
12
13 #include "core.h"
14 #include "sh_pfc.h"
15
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 SH_PFC_PIN_CFG_PULL_UP | \
18 SH_PFC_PIN_CFG_PULL_DOWN)
19
20 #define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
33 /*
34 * F_() : just information
35 * FM() : macro for FN_xxx / xxx_MARK
36 */
37
38 /* GPSR0 */
39 #define GPSR0_15 F_(D15, IP7_11_8)
40 #define GPSR0_14 F_(D14, IP7_7_4)
41 #define GPSR0_13 F_(D13, IP7_3_0)
42 #define GPSR0_12 F_(D12, IP6_31_28)
43 #define GPSR0_11 F_(D11, IP6_27_24)
44 #define GPSR0_10 F_(D10, IP6_23_20)
45 #define GPSR0_9 F_(D9, IP6_19_16)
46 #define GPSR0_8 F_(D8, IP6_15_12)
47 #define GPSR0_7 F_(D7, IP6_11_8)
48 #define GPSR0_6 F_(D6, IP6_7_4)
49 #define GPSR0_5 F_(D5, IP6_3_0)
50 #define GPSR0_4 F_(D4, IP5_31_28)
51 #define GPSR0_3 F_(D3, IP5_27_24)
52 #define GPSR0_2 F_(D2, IP5_23_20)
53 #define GPSR0_1 F_(D1, IP5_19_16)
54 #define GPSR0_0 F_(D0, IP5_15_12)
55
56 /* GPSR1 */
57 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
58 #define GPSR1_26 F_(WE1_N, IP5_7_4)
59 #define GPSR1_25 F_(WE0_N, IP5_3_0)
60 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
61 #define GPSR1_23 F_(RD_N, IP4_27_24)
62 #define GPSR1_22 F_(BS_N, IP4_23_20)
63 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
64 #define GPSR1_20 F_(CS0_N, IP4_15_12)
65 #define GPSR1_19 F_(A19, IP4_11_8)
66 #define GPSR1_18 F_(A18, IP4_7_4)
67 #define GPSR1_17 F_(A17, IP4_3_0)
68 #define GPSR1_16 F_(A16, IP3_31_28)
69 #define GPSR1_15 F_(A15, IP3_27_24)
70 #define GPSR1_14 F_(A14, IP3_23_20)
71 #define GPSR1_13 F_(A13, IP3_19_16)
72 #define GPSR1_12 F_(A12, IP3_15_12)
73 #define GPSR1_11 F_(A11, IP3_11_8)
74 #define GPSR1_10 F_(A10, IP3_7_4)
75 #define GPSR1_9 F_(A9, IP3_3_0)
76 #define GPSR1_8 F_(A8, IP2_31_28)
77 #define GPSR1_7 F_(A7, IP2_27_24)
78 #define GPSR1_6 F_(A6, IP2_23_20)
79 #define GPSR1_5 F_(A5, IP2_19_16)
80 #define GPSR1_4 F_(A4, IP2_15_12)
81 #define GPSR1_3 F_(A3, IP2_11_8)
82 #define GPSR1_2 F_(A2, IP2_7_4)
83 #define GPSR1_1 F_(A1, IP2_3_0)
84 #define GPSR1_0 F_(A0, IP1_31_28)
85
86 /* GPSR2 */
87 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
88 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
89 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
90 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
91 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
92 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
93 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
94 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
95 #define GPSR2_6 F_(PWM0, IP1_19_16)
96 #define GPSR2_5 F_(IRQ5, IP1_15_12)
97 #define GPSR2_4 F_(IRQ4, IP1_11_8)
98 #define GPSR2_3 F_(IRQ3, IP1_7_4)
99 #define GPSR2_2 F_(IRQ2, IP1_3_0)
100 #define GPSR2_1 F_(IRQ1, IP0_31_28)
101 #define GPSR2_0 F_(IRQ0, IP0_27_24)
102
103 /* GPSR3 */
104 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
105 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
106 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
107 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
108 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
109 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
110 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
111 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
112 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
113 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
114 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
115 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
116 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
117 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
118 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
119 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
120
121 /* GPSR4 */
122 #define GPSR4_17 FM(SD3_DS)
123 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
124 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
125 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
126 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
127 #define GPSR4_12 FM(SD3_DAT3)
128 #define GPSR4_11 FM(SD3_DAT2)
129 #define GPSR4_10 FM(SD3_DAT1)
130 #define GPSR4_9 FM(SD3_DAT0)
131 #define GPSR4_8 FM(SD3_CMD)
132 #define GPSR4_7 FM(SD3_CLK)
133 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
134 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
135 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
136 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
137 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
138 #define GPSR4_1 FM(SD2_CMD)
139 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
140
141 /* GPSR5 */
142 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
143 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
144 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
145 #define GPSR5_22 FM(MSIOF0_RXD)
146 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
147 #define GPSR5_20 FM(MSIOF0_TXD)
148 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
149 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
150 #define GPSR5_17 FM(MSIOF0_SCK)
151 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
152 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
153 #define GPSR5_14 F_(HTX0, IP12_19_16)
154 #define GPSR5_13 F_(HRX0, IP12_15_12)
155 #define GPSR5_12 F_(HSCK0, IP12_11_8)
156 #define GPSR5_11 F_(RX2_A, IP12_7_4)
157 #define GPSR5_10 F_(TX2_A, IP12_3_0)
158 #define GPSR5_9 F_(SCK2, IP11_31_28)
159 #define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
160 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
161 #define GPSR5_6 F_(TX1_A, IP11_19_16)
162 #define GPSR5_5 F_(RX1_A, IP11_15_12)
163 #define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
164 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
165 #define GPSR5_2 F_(TX0, IP11_3_0)
166 #define GPSR5_1 F_(RX0, IP10_31_28)
167 #define GPSR5_0 F_(SCK0, IP10_27_24)
168
169 /* GPSR6 */
170 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
171 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
172 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
173 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
174 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
175 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
176 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
177 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
178 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
179 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
180 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
181 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
182 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
183 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
184 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
185 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
186 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
187 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
188 #define GPSR6_13 FM(SSI_SDATA5)
189 #define GPSR6_12 FM(SSI_WS5)
190 #define GPSR6_11 FM(SSI_SCK5)
191 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
192 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
193 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
194 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
195 #define GPSR6_6 F_(SSI_WS349, IP14_15_12)
196 #define GPSR6_5 F_(SSI_SCK349, IP14_11_8)
197 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
198 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
199 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
200 #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
201 #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
202
203 /* GPSR7 */
204 #define GPSR7_3 FM(HDMI1_CEC)
205 #define GPSR7_2 FM(HDMI0_CEC)
206 #define GPSR7_1 FM(AVS2)
207 #define GPSR7_0 FM(AVS1)
208
209
210 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
211 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230
231 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
232 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318
319 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
320 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355
356 #define PINMUX_GPSR \
357 \
358 GPSR6_31 \
359 GPSR6_30 \
360 GPSR6_29 \
361 GPSR6_28 \
362 GPSR1_27 GPSR6_27 \
363 GPSR1_26 GPSR6_26 \
364 GPSR1_25 GPSR5_25 GPSR6_25 \
365 GPSR1_24 GPSR5_24 GPSR6_24 \
366 GPSR1_23 GPSR5_23 GPSR6_23 \
367 GPSR1_22 GPSR5_22 GPSR6_22 \
368 GPSR1_21 GPSR5_21 GPSR6_21 \
369 GPSR1_20 GPSR5_20 GPSR6_20 \
370 GPSR1_19 GPSR5_19 GPSR6_19 \
371 GPSR1_18 GPSR5_18 GPSR6_18 \
372 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
373 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
374 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
375 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
376 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
377 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
378 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
379 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
380 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
381 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
382 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
383 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
384 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
385 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
386 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
387 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
388 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
389 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
390
391 #define PINMUX_IPSR \
392 \
393 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
394 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
395 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
396 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
397 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
398 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
399 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
400 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
401 \
402 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
403 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
404 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
405 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
406 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
407 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
408 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
409 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
410 \
411 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
412 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
413 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
414 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
415 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
416 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
417 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
418 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
419 \
420 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
421 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
422 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
423 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
424 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
425 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
426 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
427 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
428 \
429 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
430 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
431 FM(IP16_11_8) IP16_11_8 \
432 FM(IP16_15_12) IP16_15_12 \
433 FM(IP16_19_16) IP16_19_16 \
434 FM(IP16_23_20) IP16_23_20 \
435 FM(IP16_27_24) IP16_27_24 \
436 FM(IP16_31_28) IP16_31_28
437
438 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
439 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
440 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
441 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
442 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
443 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
444 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
445 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
446 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
447 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
448 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
449 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
450 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
451 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
452 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
453 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
454 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
455 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
456 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
457 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
458 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
459 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
460
461 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
462 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
463 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
465 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
466 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
467 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
468 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
469 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
470 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
471 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
472 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
473 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
474 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
475 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
476 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
477 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
478 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
479 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
480 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
481 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
482 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
483 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
484
485 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
486 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
487 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
488 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
489 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
490
491 #define PINMUX_MOD_SELS\
492 \
493 MOD_SEL1_31_30 MOD_SEL2_31 \
494 MOD_SEL0_30_29 MOD_SEL2_30 \
495 MOD_SEL1_29_28_27 MOD_SEL2_29 \
496 MOD_SEL0_28_27 \
497 \
498 MOD_SEL0_26_25_24 MOD_SEL1_26 \
499 MOD_SEL1_25_24 \
500 \
501 MOD_SEL0_23 MOD_SEL1_23_22_21 \
502 MOD_SEL0_22 \
503 MOD_SEL0_21_20 \
504 MOD_SEL1_20 \
505 MOD_SEL0_19 MOD_SEL1_19 \
506 MOD_SEL0_18 MOD_SEL1_18_17 \
507 MOD_SEL0_17 \
508 MOD_SEL0_16_15 MOD_SEL1_16 \
509 MOD_SEL1_15_14 \
510 MOD_SEL0_14 \
511 MOD_SEL0_13 MOD_SEL1_13 \
512 MOD_SEL0_12 MOD_SEL1_12 \
513 MOD_SEL0_11 MOD_SEL1_11 \
514 MOD_SEL0_10 MOD_SEL1_10 \
515 MOD_SEL0_9 MOD_SEL1_9 \
516 MOD_SEL0_8 \
517 MOD_SEL0_7_6 \
518 MOD_SEL1_6 \
519 MOD_SEL0_5_4 MOD_SEL1_5 \
520 MOD_SEL1_4 \
521 MOD_SEL0_3 MOD_SEL1_3 \
522 MOD_SEL0_2_1 MOD_SEL1_2 \
523 MOD_SEL1_1 \
524 MOD_SEL1_0 MOD_SEL2_0
525
526 /*
527 * These pins are not able to be muxed but have other properties
528 * that can be set, such as drive-strength or pull-up/pull-down enable.
529 */
530 #define PINMUX_STATIC \
531 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
532 FM(QSPI0_IO2) FM(QSPI0_IO3) \
533 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
534 FM(QSPI1_IO2) FM(QSPI1_IO3) \
535 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
536 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
537 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
538 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
539 FM(CLKOUT) FM(PRESETOUT) \
540 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
541 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
542
543 enum {
544 PINMUX_RESERVED = 0,
545
546 PINMUX_DATA_BEGIN,
547 GP_ALL(DATA),
548 PINMUX_DATA_END,
549
550 #define F_(x, y)
551 #define FM(x) FN_##x,
552 PINMUX_FUNCTION_BEGIN,
553 GP_ALL(FN),
554 PINMUX_GPSR
555 PINMUX_IPSR
556 PINMUX_MOD_SELS
557 PINMUX_FUNCTION_END,
558 #undef F_
559 #undef FM
560
561 #define F_(x, y)
562 #define FM(x) x##_MARK,
563 PINMUX_MARK_BEGIN,
564 PINMUX_GPSR
565 PINMUX_IPSR
566 PINMUX_MOD_SELS
567 PINMUX_STATIC
568 PINMUX_MARK_END,
569 #undef F_
570 #undef FM
571 };
572
573 static const u16 pinmux_data[] = {
574 PINMUX_DATA_GP_ALL(),
575
576 PINMUX_SINGLE(AVS1),
577 PINMUX_SINGLE(AVS2),
578 PINMUX_SINGLE(HDMI0_CEC),
579 PINMUX_SINGLE(HDMI1_CEC),
580 PINMUX_SINGLE(I2C_SEL_0_1),
581 PINMUX_SINGLE(I2C_SEL_3_1),
582 PINMUX_SINGLE(I2C_SEL_5_1),
583 PINMUX_SINGLE(MSIOF0_RXD),
584 PINMUX_SINGLE(MSIOF0_SCK),
585 PINMUX_SINGLE(MSIOF0_TXD),
586 PINMUX_SINGLE(SD2_CMD),
587 PINMUX_SINGLE(SD3_CLK),
588 PINMUX_SINGLE(SD3_CMD),
589 PINMUX_SINGLE(SD3_DAT0),
590 PINMUX_SINGLE(SD3_DAT1),
591 PINMUX_SINGLE(SD3_DAT2),
592 PINMUX_SINGLE(SD3_DAT3),
593 PINMUX_SINGLE(SD3_DS),
594 PINMUX_SINGLE(SSI_SCK5),
595 PINMUX_SINGLE(SSI_SDATA5),
596 PINMUX_SINGLE(SSI_WS5),
597
598 /* IPSR0 */
599 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
600 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
601
602 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
603 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
604 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
605
606 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
607 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
609
610 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
611 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
613
614 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
615 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
617
618 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
619 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
620 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
621
622 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
623 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
624 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
625 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
626 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
627 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
628
629 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
630 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
631 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
632 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
635
636 /* IPSR1 */
637 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
638 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
639 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
640 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
642
643 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
644 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
645 PINMUX_IPSR_GPSR(IP1_7_4, A25),
646 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
647 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
648 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
649
650 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
651 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
652 PINMUX_IPSR_GPSR(IP1_11_8, A24),
653 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
654 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
655 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
656
657 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
658 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
659 PINMUX_IPSR_GPSR(IP1_15_12, A23),
660 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
661 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
662 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
663
664 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
665 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
666 PINMUX_IPSR_GPSR(IP1_19_16, A22),
667 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
668 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
669
670 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
671 PINMUX_IPSR_GPSR(IP1_23_20, A21),
672 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
673 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
675
676 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
677 PINMUX_IPSR_GPSR(IP1_27_24, A20),
678 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
679 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
680
681 PINMUX_IPSR_GPSR(IP1_31_28, A0),
682 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
683 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
684 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
685 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
686 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
687
688 /* IPSR2 */
689 PINMUX_IPSR_GPSR(IP2_3_0, A1),
690 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
691 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
692 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
693 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
694 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
695
696 PINMUX_IPSR_GPSR(IP2_7_4, A2),
697 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
698 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
699 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
700 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
701 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
702
703 PINMUX_IPSR_GPSR(IP2_11_8, A3),
704 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
705 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
706 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
707 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
708 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
709
710 PINMUX_IPSR_GPSR(IP2_15_12, A4),
711 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
712 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
713 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
714 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
715 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
716
717 PINMUX_IPSR_GPSR(IP2_19_16, A5),
718 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
719 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
720 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
721 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
722 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
723 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
724
725 PINMUX_IPSR_GPSR(IP2_23_20, A6),
726 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
727 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
728 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
729 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
730 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
731 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
732
733 PINMUX_IPSR_GPSR(IP2_27_24, A7),
734 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
735 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
736 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
737 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
738 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
739 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
740
741 PINMUX_IPSR_GPSR(IP2_31_28, A8),
742 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
743 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
744 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
745 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
746 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
747 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
748
749 /* IPSR3 */
750 PINMUX_IPSR_GPSR(IP3_3_0, A9),
751 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
752 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
753 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
754
755 PINMUX_IPSR_GPSR(IP3_7_4, A10),
756 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
757 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
758 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
759
760 PINMUX_IPSR_GPSR(IP3_11_8, A11),
761 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
762 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
763 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
764 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
765 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
766 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
767 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
768 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
769
770 PINMUX_IPSR_GPSR(IP3_15_12, A12),
771 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
772 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
773 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
774 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
775 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
776
777 PINMUX_IPSR_GPSR(IP3_19_16, A13),
778 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
779 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
780 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
781 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
782 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
783
784 PINMUX_IPSR_GPSR(IP3_23_20, A14),
785 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
786 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
788 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
789 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
790
791 PINMUX_IPSR_GPSR(IP3_27_24, A15),
792 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
793 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
795 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
796 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
797
798 PINMUX_IPSR_GPSR(IP3_31_28, A16),
799 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
800 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
801 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
802
803 /* IPSR4 */
804 PINMUX_IPSR_GPSR(IP4_3_0, A17),
805 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
806 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
807 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
808
809 PINMUX_IPSR_GPSR(IP4_7_4, A18),
810 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
811 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
812 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
813
814 PINMUX_IPSR_GPSR(IP4_11_8, A19),
815 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
816 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
817 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
818
819 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
820 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
821
822 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
823 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
824 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
825
826 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
827 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
828 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
829 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
830 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
831 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
832 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
833 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
834
835 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
836 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
837 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
838 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
839 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
840 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
841
842 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
843 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
844 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
845 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
846 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
847 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
848
849 /* IPSR5 */
850 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
851 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
852 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
853 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
854 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
855 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
856 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
857
858 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
859 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
860 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
861 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
862 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
863 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
864 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
865 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
866
867 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
868 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
869 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
870 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
871
872 PINMUX_IPSR_GPSR(IP5_15_12, D0),
873 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
874 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
875 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
876 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
877
878 PINMUX_IPSR_GPSR(IP5_19_16, D1),
879 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
880 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
881 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
882 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
883
884 PINMUX_IPSR_GPSR(IP5_23_20, D2),
885 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
886 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
887 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
888
889 PINMUX_IPSR_GPSR(IP5_27_24, D3),
890 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
891 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
892 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
893
894 PINMUX_IPSR_GPSR(IP5_31_28, D4),
895 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
896 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
897 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
898
899 /* IPSR6 */
900 PINMUX_IPSR_GPSR(IP6_3_0, D5),
901 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
902 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
903 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
904
905 PINMUX_IPSR_GPSR(IP6_7_4, D6),
906 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
907 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
908 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
909
910 PINMUX_IPSR_GPSR(IP6_11_8, D7),
911 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
912 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
913 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
914
915 PINMUX_IPSR_GPSR(IP6_15_12, D8),
916 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
917 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
918 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
919 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
920 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
921
922 PINMUX_IPSR_GPSR(IP6_19_16, D9),
923 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
924 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
925 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
926 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
927
928 PINMUX_IPSR_GPSR(IP6_23_20, D10),
929 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
930 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
931 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
932 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
933 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
934 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
935
936 PINMUX_IPSR_GPSR(IP6_27_24, D11),
937 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
938 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
940 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
941 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
942 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
943
944 PINMUX_IPSR_GPSR(IP6_31_28, D12),
945 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
946 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
947 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
948 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
949 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
950
951 /* IPSR7 */
952 PINMUX_IPSR_GPSR(IP7_3_0, D13),
953 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
954 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
955 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
956 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
957 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
958
959 PINMUX_IPSR_GPSR(IP7_7_4, D14),
960 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
961 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
962 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
963 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
964 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
965 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
966
967 PINMUX_IPSR_GPSR(IP7_11_8, D15),
968 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
969 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
970 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
971 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
972 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
973 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
974
975 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
976
977 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
978 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
979 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
980
981 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
982 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
983 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
984
985 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
986 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
987 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
988 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
989
990 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
991 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
992 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
993 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
994
995 /* IPSR8 */
996 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
997 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
998 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
999 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1000
1001 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1002 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1003 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1004 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1005
1006 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1007 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1008 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1009
1010 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1011 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1012 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1013 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1014
1015 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1016 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1017 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1019 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1020
1021 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1022 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1023 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1024 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1025 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1026
1027 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1028 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1029 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1030 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1032
1033 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1034 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1035 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1036 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1037 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1038
1039 /* IPSR9 */
1040 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1041
1042 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
1043
1044 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
1045
1046 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
1047
1048 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
1049
1050 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
1051 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
1052
1053 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
1054 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1055
1056 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
1057 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1058
1059 /* IPSR10 */
1060 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1061 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
1062
1063 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1064 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
1065
1066 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
1067 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1068 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1069
1070 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
1071 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1072
1073 PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
1074 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1075
1076 PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
1077 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1078
1079 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
1080 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1081 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1082 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1083 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1084 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1085 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1086 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1087 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
1088
1089 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
1090 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1091 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1092 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1093 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1094
1095 /* IPSR11 */
1096 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
1097 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1098 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1099 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1100 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1101
1102 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
1103 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1104 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1105 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1106 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1107 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1108 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1109 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
1110
1111 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
1112 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1113 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1114 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1116 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1117 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1118 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
1119
1120 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1121 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1122 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1123 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1124 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1125
1126 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1127 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1128 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1129 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1130 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1131
1132 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
1133 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1134 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1135 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1136 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1137 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1138 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
1139
1140 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
1141 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1142 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1143 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1144 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1145 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1146 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
1147
1148 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
1149 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1150 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1151 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1152 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1153 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1154 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
1155
1156 /* IPSR12 */
1157 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1158 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1159 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1160 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1161 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1162 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1163
1164 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1165 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1166 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1167 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1168 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1169 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1170
1171 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
1172 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1173 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1174 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1175 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1176 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1177 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1178
1179 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
1180 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1181 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1182 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1183 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1184 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1185
1186 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
1187 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1188 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1189 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1190 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1191 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1192
1193 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
1194 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1195 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1196 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1197 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1198 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1199 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1200 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1201
1202 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
1203 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1204 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1205 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1206 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1207 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1208 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1209
1210 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1211 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1212
1213 /* IPSR13 */
1214 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1215 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
1216 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1217 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1218 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1219 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1220 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1221
1222 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1223 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
1224 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1225 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1226 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1227 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1229 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
1232 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1233 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1234
1235 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1237 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1238 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1239
1240 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
1241 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1242 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1243
1244 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
1245 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1246
1247 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
1248 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1249
1250 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
1251 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1252
1253 /* IPSR14 */
1254 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1255
1256 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1257 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1258
1259 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349),
1260 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1261 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1262
1263 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349),
1264 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1265 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1266 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1267
1268 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
1269 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1270 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1271 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1272 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1273 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1274 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1275
1276 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
1277 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1278 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1279 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1280 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1281 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1282 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1283
1284 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
1285 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1286 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1287 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1288 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1289 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1290 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1291
1292 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
1293 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1294 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1295 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1296 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1297 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1298 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1299
1300 /* IPSR15 */
1301 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1302 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
1303 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1304
1305 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1306 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
1307 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1308
1309 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
1310 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1311 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
1312
1313 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
1314 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1315 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1316 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1317 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1318 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1319 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1320
1321 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
1322 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1323 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1324 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1328
1329 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
1330 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1331 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1332 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1337
1338 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
1339 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1340 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1341 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1345
1346 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1347 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1348 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1349 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1351 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
1352 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1353 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
1354
1355 /* IPSR16 */
1356 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1357 PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
1358
1359 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1360 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1361 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1362 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1363 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1364
1365 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
1366 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1367 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1368 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1369 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1370 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1371
1372 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
1373 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1374 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1375 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1376 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1377
1378 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
1379 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1380 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1382 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1383 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1384 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1385 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1386
1387 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
1388 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1389 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1391 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1392 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1393 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1394 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1395
1396 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
1397 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1398 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1399 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1400 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1401 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1402 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1403 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1404 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
1405
1406 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
1407 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1408 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1409 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1410 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1411 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1412 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1413 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1414 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
1415
1416 /* IPSR17 */
1417 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
1418 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1419 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1420 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1421 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1422 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1423 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
1424
1425 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
1426 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1427 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1428 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1429 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1430 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1431 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
1432
1433 /*
1434 * Static pins can not be muxed between different functions but
1435 * still needs a mark entry in the pinmux list. Add each static
1436 * pin to the list without an associated function. The sh-pfc
1437 * core will do the right thing and skip trying to mux then pin
1438 * while still applying configuration to it
1439 */
1440 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1441 PINMUX_STATIC
1442 #undef FM
1443 };
1444
1445 /*
1446 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1447 * Physical layout rows: A - AW, cols: 1 - 39.
1448 */
1449 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1450 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1451 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1452 #define PIN_NONE U16_MAX
1453
1454 static const struct sh_pfc_pin pinmux_pins[] = {
1455 PINMUX_GPIO_GP_ALL(),
1456
1457 /*
1458 * Pins not associated with a GPIO port.
1459 *
1460 * The pin positions are different between different r8a7795
1461 * packages, all that is needed for the pfc driver is a unique
1462 * number for each pin. To this end use the pin layout from
1463 * R-Car H3SiP to calculate a unique number for each pin.
1464 */
1465 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1466 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1467 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1468 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1469 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1470 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1471 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1472 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1473 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1474 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1475 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1476 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1477 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1478 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1479 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1480 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1481 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1482 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1483 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1484 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1485 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1486 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1487 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1488 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1489 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1490 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1491 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1492 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1493 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1494 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1495 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1496 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1497 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1498 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1499 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1500 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1501 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1502 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1503 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1504 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1505 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1506 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1507 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1508 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1509 };
1510
1511 /* - AUDIO CLOCK ------------------------------------------------------------ */
1512 static const unsigned int audio_clk_a_a_pins[] = {
1513 /* CLK A */
1514 RCAR_GP_PIN(6, 22),
1515 };
1516 static const unsigned int audio_clk_a_a_mux[] = {
1517 AUDIO_CLKA_A_MARK,
1518 };
1519 static const unsigned int audio_clk_a_b_pins[] = {
1520 /* CLK A */
1521 RCAR_GP_PIN(5, 4),
1522 };
1523 static const unsigned int audio_clk_a_b_mux[] = {
1524 AUDIO_CLKA_B_MARK,
1525 };
1526 static const unsigned int audio_clk_a_c_pins[] = {
1527 /* CLK A */
1528 RCAR_GP_PIN(5, 19),
1529 };
1530 static const unsigned int audio_clk_a_c_mux[] = {
1531 AUDIO_CLKA_C_MARK,
1532 };
1533 static const unsigned int audio_clk_b_a_pins[] = {
1534 /* CLK B */
1535 RCAR_GP_PIN(5, 12),
1536 };
1537 static const unsigned int audio_clk_b_a_mux[] = {
1538 AUDIO_CLKB_A_MARK,
1539 };
1540 static const unsigned int audio_clk_b_b_pins[] = {
1541 /* CLK B */
1542 RCAR_GP_PIN(6, 23),
1543 };
1544 static const unsigned int audio_clk_b_b_mux[] = {
1545 AUDIO_CLKB_B_MARK,
1546 };
1547 static const unsigned int audio_clk_c_a_pins[] = {
1548 /* CLK C */
1549 RCAR_GP_PIN(5, 21),
1550 };
1551 static const unsigned int audio_clk_c_a_mux[] = {
1552 AUDIO_CLKC_A_MARK,
1553 };
1554 static const unsigned int audio_clk_c_b_pins[] = {
1555 /* CLK C */
1556 RCAR_GP_PIN(5, 0),
1557 };
1558 static const unsigned int audio_clk_c_b_mux[] = {
1559 AUDIO_CLKC_B_MARK,
1560 };
1561 static const unsigned int audio_clkout_a_pins[] = {
1562 /* CLKOUT */
1563 RCAR_GP_PIN(5, 18),
1564 };
1565 static const unsigned int audio_clkout_a_mux[] = {
1566 AUDIO_CLKOUT_A_MARK,
1567 };
1568 static const unsigned int audio_clkout_b_pins[] = {
1569 /* CLKOUT */
1570 RCAR_GP_PIN(6, 28),
1571 };
1572 static const unsigned int audio_clkout_b_mux[] = {
1573 AUDIO_CLKOUT_B_MARK,
1574 };
1575 static const unsigned int audio_clkout_c_pins[] = {
1576 /* CLKOUT */
1577 RCAR_GP_PIN(5, 3),
1578 };
1579 static const unsigned int audio_clkout_c_mux[] = {
1580 AUDIO_CLKOUT_C_MARK,
1581 };
1582 static const unsigned int audio_clkout_d_pins[] = {
1583 /* CLKOUT */
1584 RCAR_GP_PIN(5, 21),
1585 };
1586 static const unsigned int audio_clkout_d_mux[] = {
1587 AUDIO_CLKOUT_D_MARK,
1588 };
1589 static const unsigned int audio_clkout1_a_pins[] = {
1590 /* CLKOUT1 */
1591 RCAR_GP_PIN(5, 15),
1592 };
1593 static const unsigned int audio_clkout1_a_mux[] = {
1594 AUDIO_CLKOUT1_A_MARK,
1595 };
1596 static const unsigned int audio_clkout1_b_pins[] = {
1597 /* CLKOUT1 */
1598 RCAR_GP_PIN(6, 29),
1599 };
1600 static const unsigned int audio_clkout1_b_mux[] = {
1601 AUDIO_CLKOUT1_B_MARK,
1602 };
1603 static const unsigned int audio_clkout2_a_pins[] = {
1604 /* CLKOUT2 */
1605 RCAR_GP_PIN(5, 16),
1606 };
1607 static const unsigned int audio_clkout2_a_mux[] = {
1608 AUDIO_CLKOUT2_A_MARK,
1609 };
1610 static const unsigned int audio_clkout2_b_pins[] = {
1611 /* CLKOUT2 */
1612 RCAR_GP_PIN(6, 30),
1613 };
1614 static const unsigned int audio_clkout2_b_mux[] = {
1615 AUDIO_CLKOUT2_B_MARK,
1616 };
1617
1618 static const unsigned int audio_clkout3_a_pins[] = {
1619 /* CLKOUT3 */
1620 RCAR_GP_PIN(5, 19),
1621 };
1622 static const unsigned int audio_clkout3_a_mux[] = {
1623 AUDIO_CLKOUT3_A_MARK,
1624 };
1625 static const unsigned int audio_clkout3_b_pins[] = {
1626 /* CLKOUT3 */
1627 RCAR_GP_PIN(6, 31),
1628 };
1629 static const unsigned int audio_clkout3_b_mux[] = {
1630 AUDIO_CLKOUT3_B_MARK,
1631 };
1632
1633 /* - EtherAVB --------------------------------------------------------------- */
1634 static const unsigned int avb_link_pins[] = {
1635 /* AVB_LINK */
1636 RCAR_GP_PIN(2, 12),
1637 };
1638 static const unsigned int avb_link_mux[] = {
1639 AVB_LINK_MARK,
1640 };
1641 static const unsigned int avb_magic_pins[] = {
1642 /* AVB_MAGIC_ */
1643 RCAR_GP_PIN(2, 10),
1644 };
1645 static const unsigned int avb_magic_mux[] = {
1646 AVB_MAGIC_MARK,
1647 };
1648 static const unsigned int avb_phy_int_pins[] = {
1649 /* AVB_PHY_INT */
1650 RCAR_GP_PIN(2, 11),
1651 };
1652 static const unsigned int avb_phy_int_mux[] = {
1653 AVB_PHY_INT_MARK,
1654 };
1655 static const unsigned int avb_mdc_pins[] = {
1656 /* AVB_MDC, AVB_MDIO */
1657 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1658 };
1659 static const unsigned int avb_mdc_mux[] = {
1660 AVB_MDC_MARK, AVB_MDIO_MARK,
1661 };
1662 static const unsigned int avb_mii_pins[] = {
1663 /*
1664 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1665 * AVB_TD1, AVB_TD2, AVB_TD3,
1666 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1667 * AVB_RD1, AVB_RD2, AVB_RD3,
1668 * AVB_TXCREFCLK
1669 */
1670 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1671 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1672 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1673 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1674 PIN_NUMBER('A', 12),
1675
1676 };
1677 static const unsigned int avb_mii_mux[] = {
1678 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1679 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1680 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1681 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1682 AVB_TXCREFCLK_MARK,
1683 };
1684 static const unsigned int avb_avtp_pps_pins[] = {
1685 /* AVB_AVTP_PPS */
1686 RCAR_GP_PIN(2, 6),
1687 };
1688 static const unsigned int avb_avtp_pps_mux[] = {
1689 AVB_AVTP_PPS_MARK,
1690 };
1691 static const unsigned int avb_avtp_match_a_pins[] = {
1692 /* AVB_AVTP_MATCH_A */
1693 RCAR_GP_PIN(2, 13),
1694 };
1695 static const unsigned int avb_avtp_match_a_mux[] = {
1696 AVB_AVTP_MATCH_A_MARK,
1697 };
1698 static const unsigned int avb_avtp_capture_a_pins[] = {
1699 /* AVB_AVTP_CAPTURE_A */
1700 RCAR_GP_PIN(2, 14),
1701 };
1702 static const unsigned int avb_avtp_capture_a_mux[] = {
1703 AVB_AVTP_CAPTURE_A_MARK,
1704 };
1705 static const unsigned int avb_avtp_match_b_pins[] = {
1706 /* AVB_AVTP_MATCH_B */
1707 RCAR_GP_PIN(1, 8),
1708 };
1709 static const unsigned int avb_avtp_match_b_mux[] = {
1710 AVB_AVTP_MATCH_B_MARK,
1711 };
1712 static const unsigned int avb_avtp_capture_b_pins[] = {
1713 /* AVB_AVTP_CAPTURE_B */
1714 RCAR_GP_PIN(1, 11),
1715 };
1716 static const unsigned int avb_avtp_capture_b_mux[] = {
1717 AVB_AVTP_CAPTURE_B_MARK,
1718 };
1719
1720 /* - CAN ------------------------------------------------------------------ */
1721 static const unsigned int can0_data_a_pins[] = {
1722 /* TX, RX */
1723 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1724 };
1725 static const unsigned int can0_data_a_mux[] = {
1726 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1727 };
1728 static const unsigned int can0_data_b_pins[] = {
1729 /* TX, RX */
1730 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1731 };
1732 static const unsigned int can0_data_b_mux[] = {
1733 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1734 };
1735 static const unsigned int can1_data_pins[] = {
1736 /* TX, RX */
1737 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1738 };
1739 static const unsigned int can1_data_mux[] = {
1740 CAN1_TX_MARK, CAN1_RX_MARK,
1741 };
1742
1743 /* - CAN Clock -------------------------------------------------------------- */
1744 static const unsigned int can_clk_pins[] = {
1745 /* CLK */
1746 RCAR_GP_PIN(1, 25),
1747 };
1748 static const unsigned int can_clk_mux[] = {
1749 CAN_CLK_MARK,
1750 };
1751
1752 /* - CAN FD --------------------------------------------------------------- */
1753 static const unsigned int canfd0_data_a_pins[] = {
1754 /* TX, RX */
1755 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1756 };
1757 static const unsigned int canfd0_data_a_mux[] = {
1758 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1759 };
1760 static const unsigned int canfd0_data_b_pins[] = {
1761 /* TX, RX */
1762 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1763 };
1764 static const unsigned int canfd0_data_b_mux[] = {
1765 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1766 };
1767 static const unsigned int canfd1_data_pins[] = {
1768 /* TX, RX */
1769 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1770 };
1771 static const unsigned int canfd1_data_mux[] = {
1772 CANFD1_TX_MARK, CANFD1_RX_MARK,
1773 };
1774
1775 /* - DRIF0 --------------------------------------------------------------- */
1776 static const unsigned int drif0_ctrl_a_pins[] = {
1777 /* CLK, SYNC */
1778 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1779 };
1780 static const unsigned int drif0_ctrl_a_mux[] = {
1781 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1782 };
1783 static const unsigned int drif0_data0_a_pins[] = {
1784 /* D0 */
1785 RCAR_GP_PIN(6, 10),
1786 };
1787 static const unsigned int drif0_data0_a_mux[] = {
1788 RIF0_D0_A_MARK,
1789 };
1790 static const unsigned int drif0_data1_a_pins[] = {
1791 /* D1 */
1792 RCAR_GP_PIN(6, 7),
1793 };
1794 static const unsigned int drif0_data1_a_mux[] = {
1795 RIF0_D1_A_MARK,
1796 };
1797 static const unsigned int drif0_ctrl_b_pins[] = {
1798 /* CLK, SYNC */
1799 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1800 };
1801 static const unsigned int drif0_ctrl_b_mux[] = {
1802 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1803 };
1804 static const unsigned int drif0_data0_b_pins[] = {
1805 /* D0 */
1806 RCAR_GP_PIN(5, 1),
1807 };
1808 static const unsigned int drif0_data0_b_mux[] = {
1809 RIF0_D0_B_MARK,
1810 };
1811 static const unsigned int drif0_data1_b_pins[] = {
1812 /* D1 */
1813 RCAR_GP_PIN(5, 2),
1814 };
1815 static const unsigned int drif0_data1_b_mux[] = {
1816 RIF0_D1_B_MARK,
1817 };
1818 static const unsigned int drif0_ctrl_c_pins[] = {
1819 /* CLK, SYNC */
1820 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1821 };
1822 static const unsigned int drif0_ctrl_c_mux[] = {
1823 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1824 };
1825 static const unsigned int drif0_data0_c_pins[] = {
1826 /* D0 */
1827 RCAR_GP_PIN(5, 13),
1828 };
1829 static const unsigned int drif0_data0_c_mux[] = {
1830 RIF0_D0_C_MARK,
1831 };
1832 static const unsigned int drif0_data1_c_pins[] = {
1833 /* D1 */
1834 RCAR_GP_PIN(5, 14),
1835 };
1836 static const unsigned int drif0_data1_c_mux[] = {
1837 RIF0_D1_C_MARK,
1838 };
1839 /* - DRIF1 --------------------------------------------------------------- */
1840 static const unsigned int drif1_ctrl_a_pins[] = {
1841 /* CLK, SYNC */
1842 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1843 };
1844 static const unsigned int drif1_ctrl_a_mux[] = {
1845 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1846 };
1847 static const unsigned int drif1_data0_a_pins[] = {
1848 /* D0 */
1849 RCAR_GP_PIN(6, 19),
1850 };
1851 static const unsigned int drif1_data0_a_mux[] = {
1852 RIF1_D0_A_MARK,
1853 };
1854 static const unsigned int drif1_data1_a_pins[] = {
1855 /* D1 */
1856 RCAR_GP_PIN(6, 20),
1857 };
1858 static const unsigned int drif1_data1_a_mux[] = {
1859 RIF1_D1_A_MARK,
1860 };
1861 static const unsigned int drif1_ctrl_b_pins[] = {
1862 /* CLK, SYNC */
1863 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1864 };
1865 static const unsigned int drif1_ctrl_b_mux[] = {
1866 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1867 };
1868 static const unsigned int drif1_data0_b_pins[] = {
1869 /* D0 */
1870 RCAR_GP_PIN(5, 7),
1871 };
1872 static const unsigned int drif1_data0_b_mux[] = {
1873 RIF1_D0_B_MARK,
1874 };
1875 static const unsigned int drif1_data1_b_pins[] = {
1876 /* D1 */
1877 RCAR_GP_PIN(5, 8),
1878 };
1879 static const unsigned int drif1_data1_b_mux[] = {
1880 RIF1_D1_B_MARK,
1881 };
1882 static const unsigned int drif1_ctrl_c_pins[] = {
1883 /* CLK, SYNC */
1884 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1885 };
1886 static const unsigned int drif1_ctrl_c_mux[] = {
1887 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1888 };
1889 static const unsigned int drif1_data0_c_pins[] = {
1890 /* D0 */
1891 RCAR_GP_PIN(5, 6),
1892 };
1893 static const unsigned int drif1_data0_c_mux[] = {
1894 RIF1_D0_C_MARK,
1895 };
1896 static const unsigned int drif1_data1_c_pins[] = {
1897 /* D1 */
1898 RCAR_GP_PIN(5, 10),
1899 };
1900 static const unsigned int drif1_data1_c_mux[] = {
1901 RIF1_D1_C_MARK,
1902 };
1903 /* - DRIF2 --------------------------------------------------------------- */
1904 static const unsigned int drif2_ctrl_a_pins[] = {
1905 /* CLK, SYNC */
1906 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1907 };
1908 static const unsigned int drif2_ctrl_a_mux[] = {
1909 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1910 };
1911 static const unsigned int drif2_data0_a_pins[] = {
1912 /* D0 */
1913 RCAR_GP_PIN(6, 7),
1914 };
1915 static const unsigned int drif2_data0_a_mux[] = {
1916 RIF2_D0_A_MARK,
1917 };
1918 static const unsigned int drif2_data1_a_pins[] = {
1919 /* D1 */
1920 RCAR_GP_PIN(6, 10),
1921 };
1922 static const unsigned int drif2_data1_a_mux[] = {
1923 RIF2_D1_A_MARK,
1924 };
1925 static const unsigned int drif2_ctrl_b_pins[] = {
1926 /* CLK, SYNC */
1927 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1928 };
1929 static const unsigned int drif2_ctrl_b_mux[] = {
1930 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1931 };
1932 static const unsigned int drif2_data0_b_pins[] = {
1933 /* D0 */
1934 RCAR_GP_PIN(6, 30),
1935 };
1936 static const unsigned int drif2_data0_b_mux[] = {
1937 RIF2_D0_B_MARK,
1938 };
1939 static const unsigned int drif2_data1_b_pins[] = {
1940 /* D1 */
1941 RCAR_GP_PIN(6, 31),
1942 };
1943 static const unsigned int drif2_data1_b_mux[] = {
1944 RIF2_D1_B_MARK,
1945 };
1946 /* - DRIF3 --------------------------------------------------------------- */
1947 static const unsigned int drif3_ctrl_a_pins[] = {
1948 /* CLK, SYNC */
1949 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1950 };
1951 static const unsigned int drif3_ctrl_a_mux[] = {
1952 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1953 };
1954 static const unsigned int drif3_data0_a_pins[] = {
1955 /* D0 */
1956 RCAR_GP_PIN(6, 19),
1957 };
1958 static const unsigned int drif3_data0_a_mux[] = {
1959 RIF3_D0_A_MARK,
1960 };
1961 static const unsigned int drif3_data1_a_pins[] = {
1962 /* D1 */
1963 RCAR_GP_PIN(6, 20),
1964 };
1965 static const unsigned int drif3_data1_a_mux[] = {
1966 RIF3_D1_A_MARK,
1967 };
1968 static const unsigned int drif3_ctrl_b_pins[] = {
1969 /* CLK, SYNC */
1970 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1971 };
1972 static const unsigned int drif3_ctrl_b_mux[] = {
1973 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1974 };
1975 static const unsigned int drif3_data0_b_pins[] = {
1976 /* D0 */
1977 RCAR_GP_PIN(6, 28),
1978 };
1979 static const unsigned int drif3_data0_b_mux[] = {
1980 RIF3_D0_B_MARK,
1981 };
1982 static const unsigned int drif3_data1_b_pins[] = {
1983 /* D1 */
1984 RCAR_GP_PIN(6, 29),
1985 };
1986 static const unsigned int drif3_data1_b_mux[] = {
1987 RIF3_D1_B_MARK,
1988 };
1989
1990 /* - DU --------------------------------------------------------------------- */
1991 static const unsigned int du_rgb666_pins[] = {
1992 /* R[7:2], G[7:2], B[7:2] */
1993 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1994 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1995 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1996 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1997 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1998 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1999 };
2000 static const unsigned int du_rgb666_mux[] = {
2001 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2002 DU_DR3_MARK, DU_DR2_MARK,
2003 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2004 DU_DG3_MARK, DU_DG2_MARK,
2005 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2006 DU_DB3_MARK, DU_DB2_MARK,
2007 };
2008 static const unsigned int du_rgb888_pins[] = {
2009 /* R[7:0], G[7:0], B[7:0] */
2010 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2011 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2012 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2013 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2014 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2015 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2016 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2017 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2018 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2019 };
2020 static const unsigned int du_rgb888_mux[] = {
2021 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2022 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2023 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2024 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2025 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2026 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2027 };
2028 static const unsigned int du_clk_out_0_pins[] = {
2029 /* CLKOUT */
2030 RCAR_GP_PIN(1, 27),
2031 };
2032 static const unsigned int du_clk_out_0_mux[] = {
2033 DU_DOTCLKOUT0_MARK
2034 };
2035 static const unsigned int du_clk_out_1_pins[] = {
2036 /* CLKOUT */
2037 RCAR_GP_PIN(2, 3),
2038 };
2039 static const unsigned int du_clk_out_1_mux[] = {
2040 DU_DOTCLKOUT1_MARK
2041 };
2042 static const unsigned int du_sync_pins[] = {
2043 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2044 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2045 };
2046 static const unsigned int du_sync_mux[] = {
2047 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2048 };
2049 static const unsigned int du_oddf_pins[] = {
2050 /* EXDISP/EXODDF/EXCDE */
2051 RCAR_GP_PIN(2, 2),
2052 };
2053 static const unsigned int du_oddf_mux[] = {
2054 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2055 };
2056 static const unsigned int du_cde_pins[] = {
2057 /* CDE */
2058 RCAR_GP_PIN(2, 0),
2059 };
2060 static const unsigned int du_cde_mux[] = {
2061 DU_CDE_MARK,
2062 };
2063 static const unsigned int du_disp_pins[] = {
2064 /* DISP */
2065 RCAR_GP_PIN(2, 1),
2066 };
2067 static const unsigned int du_disp_mux[] = {
2068 DU_DISP_MARK,
2069 };
2070 /* - HSCIF0 ----------------------------------------------------------------- */
2071 static const unsigned int hscif0_data_pins[] = {
2072 /* RX, TX */
2073 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2074 };
2075 static const unsigned int hscif0_data_mux[] = {
2076 HRX0_MARK, HTX0_MARK,
2077 };
2078 static const unsigned int hscif0_clk_pins[] = {
2079 /* SCK */
2080 RCAR_GP_PIN(5, 12),
2081 };
2082 static const unsigned int hscif0_clk_mux[] = {
2083 HSCK0_MARK,
2084 };
2085 static const unsigned int hscif0_ctrl_pins[] = {
2086 /* RTS, CTS */
2087 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2088 };
2089 static const unsigned int hscif0_ctrl_mux[] = {
2090 HRTS0_N_MARK, HCTS0_N_MARK,
2091 };
2092 /* - HSCIF1 ----------------------------------------------------------------- */
2093 static const unsigned int hscif1_data_a_pins[] = {
2094 /* RX, TX */
2095 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2096 };
2097 static const unsigned int hscif1_data_a_mux[] = {
2098 HRX1_A_MARK, HTX1_A_MARK,
2099 };
2100 static const unsigned int hscif1_clk_a_pins[] = {
2101 /* SCK */
2102 RCAR_GP_PIN(6, 21),
2103 };
2104 static const unsigned int hscif1_clk_a_mux[] = {
2105 HSCK1_A_MARK,
2106 };
2107 static const unsigned int hscif1_ctrl_a_pins[] = {
2108 /* RTS, CTS */
2109 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2110 };
2111 static const unsigned int hscif1_ctrl_a_mux[] = {
2112 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2113 };
2114
2115 static const unsigned int hscif1_data_b_pins[] = {
2116 /* RX, TX */
2117 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2118 };
2119 static const unsigned int hscif1_data_b_mux[] = {
2120 HRX1_B_MARK, HTX1_B_MARK,
2121 };
2122 static const unsigned int hscif1_clk_b_pins[] = {
2123 /* SCK */
2124 RCAR_GP_PIN(5, 0),
2125 };
2126 static const unsigned int hscif1_clk_b_mux[] = {
2127 HSCK1_B_MARK,
2128 };
2129 static const unsigned int hscif1_ctrl_b_pins[] = {
2130 /* RTS, CTS */
2131 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2132 };
2133 static const unsigned int hscif1_ctrl_b_mux[] = {
2134 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2135 };
2136 /* - HSCIF2 ----------------------------------------------------------------- */
2137 static const unsigned int hscif2_data_a_pins[] = {
2138 /* RX, TX */
2139 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2140 };
2141 static const unsigned int hscif2_data_a_mux[] = {
2142 HRX2_A_MARK, HTX2_A_MARK,
2143 };
2144 static const unsigned int hscif2_clk_a_pins[] = {
2145 /* SCK */
2146 RCAR_GP_PIN(6, 10),
2147 };
2148 static const unsigned int hscif2_clk_a_mux[] = {
2149 HSCK2_A_MARK,
2150 };
2151 static const unsigned int hscif2_ctrl_a_pins[] = {
2152 /* RTS, CTS */
2153 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2154 };
2155 static const unsigned int hscif2_ctrl_a_mux[] = {
2156 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2157 };
2158
2159 static const unsigned int hscif2_data_b_pins[] = {
2160 /* RX, TX */
2161 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2162 };
2163 static const unsigned int hscif2_data_b_mux[] = {
2164 HRX2_B_MARK, HTX2_B_MARK,
2165 };
2166 static const unsigned int hscif2_clk_b_pins[] = {
2167 /* SCK */
2168 RCAR_GP_PIN(6, 21),
2169 };
2170 static const unsigned int hscif2_clk_b_mux[] = {
2171 HSCK2_B_MARK,
2172 };
2173 static const unsigned int hscif2_ctrl_b_pins[] = {
2174 /* RTS, CTS */
2175 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2176 };
2177 static const unsigned int hscif2_ctrl_b_mux[] = {
2178 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2179 };
2180 /* - HSCIF3 ----------------------------------------------------------------- */
2181 static const unsigned int hscif3_data_a_pins[] = {
2182 /* RX, TX */
2183 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2184 };
2185 static const unsigned int hscif3_data_a_mux[] = {
2186 HRX3_A_MARK, HTX3_A_MARK,
2187 };
2188 static const unsigned int hscif3_clk_pins[] = {
2189 /* SCK */
2190 RCAR_GP_PIN(1, 22),
2191 };
2192 static const unsigned int hscif3_clk_mux[] = {
2193 HSCK3_MARK,
2194 };
2195 static const unsigned int hscif3_ctrl_pins[] = {
2196 /* RTS, CTS */
2197 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2198 };
2199 static const unsigned int hscif3_ctrl_mux[] = {
2200 HRTS3_N_MARK, HCTS3_N_MARK,
2201 };
2202
2203 static const unsigned int hscif3_data_b_pins[] = {
2204 /* RX, TX */
2205 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2206 };
2207 static const unsigned int hscif3_data_b_mux[] = {
2208 HRX3_B_MARK, HTX3_B_MARK,
2209 };
2210 static const unsigned int hscif3_data_c_pins[] = {
2211 /* RX, TX */
2212 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2213 };
2214 static const unsigned int hscif3_data_c_mux[] = {
2215 HRX3_C_MARK, HTX3_C_MARK,
2216 };
2217 static const unsigned int hscif3_data_d_pins[] = {
2218 /* RX, TX */
2219 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2220 };
2221 static const unsigned int hscif3_data_d_mux[] = {
2222 HRX3_D_MARK, HTX3_D_MARK,
2223 };
2224 /* - HSCIF4 ----------------------------------------------------------------- */
2225 static const unsigned int hscif4_data_a_pins[] = {
2226 /* RX, TX */
2227 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2228 };
2229 static const unsigned int hscif4_data_a_mux[] = {
2230 HRX4_A_MARK, HTX4_A_MARK,
2231 };
2232 static const unsigned int hscif4_clk_pins[] = {
2233 /* SCK */
2234 RCAR_GP_PIN(1, 11),
2235 };
2236 static const unsigned int hscif4_clk_mux[] = {
2237 HSCK4_MARK,
2238 };
2239 static const unsigned int hscif4_ctrl_pins[] = {
2240 /* RTS, CTS */
2241 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2242 };
2243 static const unsigned int hscif4_ctrl_mux[] = {
2244 HRTS4_N_MARK, HCTS4_N_MARK,
2245 };
2246
2247 static const unsigned int hscif4_data_b_pins[] = {
2248 /* RX, TX */
2249 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2250 };
2251 static const unsigned int hscif4_data_b_mux[] = {
2252 HRX4_B_MARK, HTX4_B_MARK,
2253 };
2254
2255 /* - I2C -------------------------------------------------------------------- */
2256 static const unsigned int i2c1_a_pins[] = {
2257 /* SDA, SCL */
2258 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2259 };
2260 static const unsigned int i2c1_a_mux[] = {
2261 SDA1_A_MARK, SCL1_A_MARK,
2262 };
2263 static const unsigned int i2c1_b_pins[] = {
2264 /* SDA, SCL */
2265 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2266 };
2267 static const unsigned int i2c1_b_mux[] = {
2268 SDA1_B_MARK, SCL1_B_MARK,
2269 };
2270 static const unsigned int i2c2_a_pins[] = {
2271 /* SDA, SCL */
2272 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2273 };
2274 static const unsigned int i2c2_a_mux[] = {
2275 SDA2_A_MARK, SCL2_A_MARK,
2276 };
2277 static const unsigned int i2c2_b_pins[] = {
2278 /* SDA, SCL */
2279 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2280 };
2281 static const unsigned int i2c2_b_mux[] = {
2282 SDA2_B_MARK, SCL2_B_MARK,
2283 };
2284 static const unsigned int i2c6_a_pins[] = {
2285 /* SDA, SCL */
2286 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2287 };
2288 static const unsigned int i2c6_a_mux[] = {
2289 SDA6_A_MARK, SCL6_A_MARK,
2290 };
2291 static const unsigned int i2c6_b_pins[] = {
2292 /* SDA, SCL */
2293 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2294 };
2295 static const unsigned int i2c6_b_mux[] = {
2296 SDA6_B_MARK, SCL6_B_MARK,
2297 };
2298 static const unsigned int i2c6_c_pins[] = {
2299 /* SDA, SCL */
2300 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2301 };
2302 static const unsigned int i2c6_c_mux[] = {
2303 SDA6_C_MARK, SCL6_C_MARK,
2304 };
2305
2306 /* - INTC-EX ---------------------------------------------------------------- */
2307 static const unsigned int intc_ex_irq0_pins[] = {
2308 /* IRQ0 */
2309 RCAR_GP_PIN(2, 0),
2310 };
2311 static const unsigned int intc_ex_irq0_mux[] = {
2312 IRQ0_MARK,
2313 };
2314 static const unsigned int intc_ex_irq1_pins[] = {
2315 /* IRQ1 */
2316 RCAR_GP_PIN(2, 1),
2317 };
2318 static const unsigned int intc_ex_irq1_mux[] = {
2319 IRQ1_MARK,
2320 };
2321 static const unsigned int intc_ex_irq2_pins[] = {
2322 /* IRQ2 */
2323 RCAR_GP_PIN(2, 2),
2324 };
2325 static const unsigned int intc_ex_irq2_mux[] = {
2326 IRQ2_MARK,
2327 };
2328 static const unsigned int intc_ex_irq3_pins[] = {
2329 /* IRQ3 */
2330 RCAR_GP_PIN(2, 3),
2331 };
2332 static const unsigned int intc_ex_irq3_mux[] = {
2333 IRQ3_MARK,
2334 };
2335 static const unsigned int intc_ex_irq4_pins[] = {
2336 /* IRQ4 */
2337 RCAR_GP_PIN(2, 4),
2338 };
2339 static const unsigned int intc_ex_irq4_mux[] = {
2340 IRQ4_MARK,
2341 };
2342 static const unsigned int intc_ex_irq5_pins[] = {
2343 /* IRQ5 */
2344 RCAR_GP_PIN(2, 5),
2345 };
2346 static const unsigned int intc_ex_irq5_mux[] = {
2347 IRQ5_MARK,
2348 };
2349
2350 /* - MSIOF0 ----------------------------------------------------------------- */
2351 static const unsigned int msiof0_clk_pins[] = {
2352 /* SCK */
2353 RCAR_GP_PIN(5, 17),
2354 };
2355 static const unsigned int msiof0_clk_mux[] = {
2356 MSIOF0_SCK_MARK,
2357 };
2358 static const unsigned int msiof0_sync_pins[] = {
2359 /* SYNC */
2360 RCAR_GP_PIN(5, 18),
2361 };
2362 static const unsigned int msiof0_sync_mux[] = {
2363 MSIOF0_SYNC_MARK,
2364 };
2365 static const unsigned int msiof0_ss1_pins[] = {
2366 /* SS1 */
2367 RCAR_GP_PIN(5, 19),
2368 };
2369 static const unsigned int msiof0_ss1_mux[] = {
2370 MSIOF0_SS1_MARK,
2371 };
2372 static const unsigned int msiof0_ss2_pins[] = {
2373 /* SS2 */
2374 RCAR_GP_PIN(5, 21),
2375 };
2376 static const unsigned int msiof0_ss2_mux[] = {
2377 MSIOF0_SS2_MARK,
2378 };
2379 static const unsigned int msiof0_txd_pins[] = {
2380 /* TXD */
2381 RCAR_GP_PIN(5, 20),
2382 };
2383 static const unsigned int msiof0_txd_mux[] = {
2384 MSIOF0_TXD_MARK,
2385 };
2386 static const unsigned int msiof0_rxd_pins[] = {
2387 /* RXD */
2388 RCAR_GP_PIN(5, 22),
2389 };
2390 static const unsigned int msiof0_rxd_mux[] = {
2391 MSIOF0_RXD_MARK,
2392 };
2393 /* - MSIOF1 ----------------------------------------------------------------- */
2394 static const unsigned int msiof1_clk_a_pins[] = {
2395 /* SCK */
2396 RCAR_GP_PIN(6, 8),
2397 };
2398 static const unsigned int msiof1_clk_a_mux[] = {
2399 MSIOF1_SCK_A_MARK,
2400 };
2401 static const unsigned int msiof1_sync_a_pins[] = {
2402 /* SYNC */
2403 RCAR_GP_PIN(6, 9),
2404 };
2405 static const unsigned int msiof1_sync_a_mux[] = {
2406 MSIOF1_SYNC_A_MARK,
2407 };
2408 static const unsigned int msiof1_ss1_a_pins[] = {
2409 /* SS1 */
2410 RCAR_GP_PIN(6, 5),
2411 };
2412 static const unsigned int msiof1_ss1_a_mux[] = {
2413 MSIOF1_SS1_A_MARK,
2414 };
2415 static const unsigned int msiof1_ss2_a_pins[] = {
2416 /* SS2 */
2417 RCAR_GP_PIN(6, 6),
2418 };
2419 static const unsigned int msiof1_ss2_a_mux[] = {
2420 MSIOF1_SS2_A_MARK,
2421 };
2422 static const unsigned int msiof1_txd_a_pins[] = {
2423 /* TXD */
2424 RCAR_GP_PIN(6, 7),
2425 };
2426 static const unsigned int msiof1_txd_a_mux[] = {
2427 MSIOF1_TXD_A_MARK,
2428 };
2429 static const unsigned int msiof1_rxd_a_pins[] = {
2430 /* RXD */
2431 RCAR_GP_PIN(6, 10),
2432 };
2433 static const unsigned int msiof1_rxd_a_mux[] = {
2434 MSIOF1_RXD_A_MARK,
2435 };
2436 static const unsigned int msiof1_clk_b_pins[] = {
2437 /* SCK */
2438 RCAR_GP_PIN(5, 9),
2439 };
2440 static const unsigned int msiof1_clk_b_mux[] = {
2441 MSIOF1_SCK_B_MARK,
2442 };
2443 static const unsigned int msiof1_sync_b_pins[] = {
2444 /* SYNC */
2445 RCAR_GP_PIN(5, 3),
2446 };
2447 static const unsigned int msiof1_sync_b_mux[] = {
2448 MSIOF1_SYNC_B_MARK,
2449 };
2450 static const unsigned int msiof1_ss1_b_pins[] = {
2451 /* SS1 */
2452 RCAR_GP_PIN(5, 4),
2453 };
2454 static const unsigned int msiof1_ss1_b_mux[] = {
2455 MSIOF1_SS1_B_MARK,
2456 };
2457 static const unsigned int msiof1_ss2_b_pins[] = {
2458 /* SS2 */
2459 RCAR_GP_PIN(5, 0),
2460 };
2461 static const unsigned int msiof1_ss2_b_mux[] = {
2462 MSIOF1_SS2_B_MARK,
2463 };
2464 static const unsigned int msiof1_txd_b_pins[] = {
2465 /* TXD */
2466 RCAR_GP_PIN(5, 8),
2467 };
2468 static const unsigned int msiof1_txd_b_mux[] = {
2469 MSIOF1_TXD_B_MARK,
2470 };
2471 static const unsigned int msiof1_rxd_b_pins[] = {
2472 /* RXD */
2473 RCAR_GP_PIN(5, 7),
2474 };
2475 static const unsigned int msiof1_rxd_b_mux[] = {
2476 MSIOF1_RXD_B_MARK,
2477 };
2478 static const unsigned int msiof1_clk_c_pins[] = {
2479 /* SCK */
2480 RCAR_GP_PIN(6, 17),
2481 };
2482 static const unsigned int msiof1_clk_c_mux[] = {
2483 MSIOF1_SCK_C_MARK,
2484 };
2485 static const unsigned int msiof1_sync_c_pins[] = {
2486 /* SYNC */
2487 RCAR_GP_PIN(6, 18),
2488 };
2489 static const unsigned int msiof1_sync_c_mux[] = {
2490 MSIOF1_SYNC_C_MARK,
2491 };
2492 static const unsigned int msiof1_ss1_c_pins[] = {
2493 /* SS1 */
2494 RCAR_GP_PIN(6, 21),
2495 };
2496 static const unsigned int msiof1_ss1_c_mux[] = {
2497 MSIOF1_SS1_C_MARK,
2498 };
2499 static const unsigned int msiof1_ss2_c_pins[] = {
2500 /* SS2 */
2501 RCAR_GP_PIN(6, 27),
2502 };
2503 static const unsigned int msiof1_ss2_c_mux[] = {
2504 MSIOF1_SS2_C_MARK,
2505 };
2506 static const unsigned int msiof1_txd_c_pins[] = {
2507 /* TXD */
2508 RCAR_GP_PIN(6, 20),
2509 };
2510 static const unsigned int msiof1_txd_c_mux[] = {
2511 MSIOF1_TXD_C_MARK,
2512 };
2513 static const unsigned int msiof1_rxd_c_pins[] = {
2514 /* RXD */
2515 RCAR_GP_PIN(6, 19),
2516 };
2517 static const unsigned int msiof1_rxd_c_mux[] = {
2518 MSIOF1_RXD_C_MARK,
2519 };
2520 static const unsigned int msiof1_clk_d_pins[] = {
2521 /* SCK */
2522 RCAR_GP_PIN(5, 12),
2523 };
2524 static const unsigned int msiof1_clk_d_mux[] = {
2525 MSIOF1_SCK_D_MARK,
2526 };
2527 static const unsigned int msiof1_sync_d_pins[] = {
2528 /* SYNC */
2529 RCAR_GP_PIN(5, 15),
2530 };
2531 static const unsigned int msiof1_sync_d_mux[] = {
2532 MSIOF1_SYNC_D_MARK,
2533 };
2534 static const unsigned int msiof1_ss1_d_pins[] = {
2535 /* SS1 */
2536 RCAR_GP_PIN(5, 16),
2537 };
2538 static const unsigned int msiof1_ss1_d_mux[] = {
2539 MSIOF1_SS1_D_MARK,
2540 };
2541 static const unsigned int msiof1_ss2_d_pins[] = {
2542 /* SS2 */
2543 RCAR_GP_PIN(5, 21),
2544 };
2545 static const unsigned int msiof1_ss2_d_mux[] = {
2546 MSIOF1_SS2_D_MARK,
2547 };
2548 static const unsigned int msiof1_txd_d_pins[] = {
2549 /* TXD */
2550 RCAR_GP_PIN(5, 14),
2551 };
2552 static const unsigned int msiof1_txd_d_mux[] = {
2553 MSIOF1_TXD_D_MARK,
2554 };
2555 static const unsigned int msiof1_rxd_d_pins[] = {
2556 /* RXD */
2557 RCAR_GP_PIN(5, 13),
2558 };
2559 static const unsigned int msiof1_rxd_d_mux[] = {
2560 MSIOF1_RXD_D_MARK,
2561 };
2562 static const unsigned int msiof1_clk_e_pins[] = {
2563 /* SCK */
2564 RCAR_GP_PIN(3, 0),
2565 };
2566 static const unsigned int msiof1_clk_e_mux[] = {
2567 MSIOF1_SCK_E_MARK,
2568 };
2569 static const unsigned int msiof1_sync_e_pins[] = {
2570 /* SYNC */
2571 RCAR_GP_PIN(3, 1),
2572 };
2573 static const unsigned int msiof1_sync_e_mux[] = {
2574 MSIOF1_SYNC_E_MARK,
2575 };
2576 static const unsigned int msiof1_ss1_e_pins[] = {
2577 /* SS1 */
2578 RCAR_GP_PIN(3, 4),
2579 };
2580 static const unsigned int msiof1_ss1_e_mux[] = {
2581 MSIOF1_SS1_E_MARK,
2582 };
2583 static const unsigned int msiof1_ss2_e_pins[] = {
2584 /* SS2 */
2585 RCAR_GP_PIN(3, 5),
2586 };
2587 static const unsigned int msiof1_ss2_e_mux[] = {
2588 MSIOF1_SS2_E_MARK,
2589 };
2590 static const unsigned int msiof1_txd_e_pins[] = {
2591 /* TXD */
2592 RCAR_GP_PIN(3, 3),
2593 };
2594 static const unsigned int msiof1_txd_e_mux[] = {
2595 MSIOF1_TXD_E_MARK,
2596 };
2597 static const unsigned int msiof1_rxd_e_pins[] = {
2598 /* RXD */
2599 RCAR_GP_PIN(3, 2),
2600 };
2601 static const unsigned int msiof1_rxd_e_mux[] = {
2602 MSIOF1_RXD_E_MARK,
2603 };
2604 static const unsigned int msiof1_clk_f_pins[] = {
2605 /* SCK */
2606 RCAR_GP_PIN(5, 23),
2607 };
2608 static const unsigned int msiof1_clk_f_mux[] = {
2609 MSIOF1_SCK_F_MARK,
2610 };
2611 static const unsigned int msiof1_sync_f_pins[] = {
2612 /* SYNC */
2613 RCAR_GP_PIN(5, 24),
2614 };
2615 static const unsigned int msiof1_sync_f_mux[] = {
2616 MSIOF1_SYNC_F_MARK,
2617 };
2618 static const unsigned int msiof1_ss1_f_pins[] = {
2619 /* SS1 */
2620 RCAR_GP_PIN(6, 1),
2621 };
2622 static const unsigned int msiof1_ss1_f_mux[] = {
2623 MSIOF1_SS1_F_MARK,
2624 };
2625 static const unsigned int msiof1_ss2_f_pins[] = {
2626 /* SS2 */
2627 RCAR_GP_PIN(6, 2),
2628 };
2629 static const unsigned int msiof1_ss2_f_mux[] = {
2630 MSIOF1_SS2_F_MARK,
2631 };
2632 static const unsigned int msiof1_txd_f_pins[] = {
2633 /* TXD */
2634 RCAR_GP_PIN(6, 0),
2635 };
2636 static const unsigned int msiof1_txd_f_mux[] = {
2637 MSIOF1_TXD_F_MARK,
2638 };
2639 static const unsigned int msiof1_rxd_f_pins[] = {
2640 /* RXD */
2641 RCAR_GP_PIN(5, 25),
2642 };
2643 static const unsigned int msiof1_rxd_f_mux[] = {
2644 MSIOF1_RXD_F_MARK,
2645 };
2646 static const unsigned int msiof1_clk_g_pins[] = {
2647 /* SCK */
2648 RCAR_GP_PIN(3, 6),
2649 };
2650 static const unsigned int msiof1_clk_g_mux[] = {
2651 MSIOF1_SCK_G_MARK,
2652 };
2653 static const unsigned int msiof1_sync_g_pins[] = {
2654 /* SYNC */
2655 RCAR_GP_PIN(3, 7),
2656 };
2657 static const unsigned int msiof1_sync_g_mux[] = {
2658 MSIOF1_SYNC_G_MARK,
2659 };
2660 static const unsigned int msiof1_ss1_g_pins[] = {
2661 /* SS1 */
2662 RCAR_GP_PIN(3, 10),
2663 };
2664 static const unsigned int msiof1_ss1_g_mux[] = {
2665 MSIOF1_SS1_G_MARK,
2666 };
2667 static const unsigned int msiof1_ss2_g_pins[] = {
2668 /* SS2 */
2669 RCAR_GP_PIN(3, 11),
2670 };
2671 static const unsigned int msiof1_ss2_g_mux[] = {
2672 MSIOF1_SS2_G_MARK,
2673 };
2674 static const unsigned int msiof1_txd_g_pins[] = {
2675 /* TXD */
2676 RCAR_GP_PIN(3, 9),
2677 };
2678 static const unsigned int msiof1_txd_g_mux[] = {
2679 MSIOF1_TXD_G_MARK,
2680 };
2681 static const unsigned int msiof1_rxd_g_pins[] = {
2682 /* RXD */
2683 RCAR_GP_PIN(3, 8),
2684 };
2685 static const unsigned int msiof1_rxd_g_mux[] = {
2686 MSIOF1_RXD_G_MARK,
2687 };
2688 /* - MSIOF2 ----------------------------------------------------------------- */
2689 static const unsigned int msiof2_clk_a_pins[] = {
2690 /* SCK */
2691 RCAR_GP_PIN(1, 9),
2692 };
2693 static const unsigned int msiof2_clk_a_mux[] = {
2694 MSIOF2_SCK_A_MARK,
2695 };
2696 static const unsigned int msiof2_sync_a_pins[] = {
2697 /* SYNC */
2698 RCAR_GP_PIN(1, 8),
2699 };
2700 static const unsigned int msiof2_sync_a_mux[] = {
2701 MSIOF2_SYNC_A_MARK,
2702 };
2703 static const unsigned int msiof2_ss1_a_pins[] = {
2704 /* SS1 */
2705 RCAR_GP_PIN(1, 6),
2706 };
2707 static const unsigned int msiof2_ss1_a_mux[] = {
2708 MSIOF2_SS1_A_MARK,
2709 };
2710 static const unsigned int msiof2_ss2_a_pins[] = {
2711 /* SS2 */
2712 RCAR_GP_PIN(1, 7),
2713 };
2714 static const unsigned int msiof2_ss2_a_mux[] = {
2715 MSIOF2_SS2_A_MARK,
2716 };
2717 static const unsigned int msiof2_txd_a_pins[] = {
2718 /* TXD */
2719 RCAR_GP_PIN(1, 11),
2720 };
2721 static const unsigned int msiof2_txd_a_mux[] = {
2722 MSIOF2_TXD_A_MARK,
2723 };
2724 static const unsigned int msiof2_rxd_a_pins[] = {
2725 /* RXD */
2726 RCAR_GP_PIN(1, 10),
2727 };
2728 static const unsigned int msiof2_rxd_a_mux[] = {
2729 MSIOF2_RXD_A_MARK,
2730 };
2731 static const unsigned int msiof2_clk_b_pins[] = {
2732 /* SCK */
2733 RCAR_GP_PIN(0, 4),
2734 };
2735 static const unsigned int msiof2_clk_b_mux[] = {
2736 MSIOF2_SCK_B_MARK,
2737 };
2738 static const unsigned int msiof2_sync_b_pins[] = {
2739 /* SYNC */
2740 RCAR_GP_PIN(0, 5),
2741 };
2742 static const unsigned int msiof2_sync_b_mux[] = {
2743 MSIOF2_SYNC_B_MARK,
2744 };
2745 static const unsigned int msiof2_ss1_b_pins[] = {
2746 /* SS1 */
2747 RCAR_GP_PIN(0, 0),
2748 };
2749 static const unsigned int msiof2_ss1_b_mux[] = {
2750 MSIOF2_SS1_B_MARK,
2751 };
2752 static const unsigned int msiof2_ss2_b_pins[] = {
2753 /* SS2 */
2754 RCAR_GP_PIN(0, 1),
2755 };
2756 static const unsigned int msiof2_ss2_b_mux[] = {
2757 MSIOF2_SS2_B_MARK,
2758 };
2759 static const unsigned int msiof2_txd_b_pins[] = {
2760 /* TXD */
2761 RCAR_GP_PIN(0, 7),
2762 };
2763 static const unsigned int msiof2_txd_b_mux[] = {
2764 MSIOF2_TXD_B_MARK,
2765 };
2766 static const unsigned int msiof2_rxd_b_pins[] = {
2767 /* RXD */
2768 RCAR_GP_PIN(0, 6),
2769 };
2770 static const unsigned int msiof2_rxd_b_mux[] = {
2771 MSIOF2_RXD_B_MARK,
2772 };
2773 static const unsigned int msiof2_clk_c_pins[] = {
2774 /* SCK */
2775 RCAR_GP_PIN(2, 12),
2776 };
2777 static const unsigned int msiof2_clk_c_mux[] = {
2778 MSIOF2_SCK_C_MARK,
2779 };
2780 static const unsigned int msiof2_sync_c_pins[] = {
2781 /* SYNC */
2782 RCAR_GP_PIN(2, 11),
2783 };
2784 static const unsigned int msiof2_sync_c_mux[] = {
2785 MSIOF2_SYNC_C_MARK,
2786 };
2787 static const unsigned int msiof2_ss1_c_pins[] = {
2788 /* SS1 */
2789 RCAR_GP_PIN(2, 10),
2790 };
2791 static const unsigned int msiof2_ss1_c_mux[] = {
2792 MSIOF2_SS1_C_MARK,
2793 };
2794 static const unsigned int msiof2_ss2_c_pins[] = {
2795 /* SS2 */
2796 RCAR_GP_PIN(2, 9),
2797 };
2798 static const unsigned int msiof2_ss2_c_mux[] = {
2799 MSIOF2_SS2_C_MARK,
2800 };
2801 static const unsigned int msiof2_txd_c_pins[] = {
2802 /* TXD */
2803 RCAR_GP_PIN(2, 14),
2804 };
2805 static const unsigned int msiof2_txd_c_mux[] = {
2806 MSIOF2_TXD_C_MARK,
2807 };
2808 static const unsigned int msiof2_rxd_c_pins[] = {
2809 /* RXD */
2810 RCAR_GP_PIN(2, 13),
2811 };
2812 static const unsigned int msiof2_rxd_c_mux[] = {
2813 MSIOF2_RXD_C_MARK,
2814 };
2815 static const unsigned int msiof2_clk_d_pins[] = {
2816 /* SCK */
2817 RCAR_GP_PIN(0, 8),
2818 };
2819 static const unsigned int msiof2_clk_d_mux[] = {
2820 MSIOF2_SCK_D_MARK,
2821 };
2822 static const unsigned int msiof2_sync_d_pins[] = {
2823 /* SYNC */
2824 RCAR_GP_PIN(0, 9),
2825 };
2826 static const unsigned int msiof2_sync_d_mux[] = {
2827 MSIOF2_SYNC_D_MARK,
2828 };
2829 static const unsigned int msiof2_ss1_d_pins[] = {
2830 /* SS1 */
2831 RCAR_GP_PIN(0, 12),
2832 };
2833 static const unsigned int msiof2_ss1_d_mux[] = {
2834 MSIOF2_SS1_D_MARK,
2835 };
2836 static const unsigned int msiof2_ss2_d_pins[] = {
2837 /* SS2 */
2838 RCAR_GP_PIN(0, 13),
2839 };
2840 static const unsigned int msiof2_ss2_d_mux[] = {
2841 MSIOF2_SS2_D_MARK,
2842 };
2843 static const unsigned int msiof2_txd_d_pins[] = {
2844 /* TXD */
2845 RCAR_GP_PIN(0, 11),
2846 };
2847 static const unsigned int msiof2_txd_d_mux[] = {
2848 MSIOF2_TXD_D_MARK,
2849 };
2850 static const unsigned int msiof2_rxd_d_pins[] = {
2851 /* RXD */
2852 RCAR_GP_PIN(0, 10),
2853 };
2854 static const unsigned int msiof2_rxd_d_mux[] = {
2855 MSIOF2_RXD_D_MARK,
2856 };
2857 /* - MSIOF3 ----------------------------------------------------------------- */
2858 static const unsigned int msiof3_clk_a_pins[] = {
2859 /* SCK */
2860 RCAR_GP_PIN(0, 0),
2861 };
2862 static const unsigned int msiof3_clk_a_mux[] = {
2863 MSIOF3_SCK_A_MARK,
2864 };
2865 static const unsigned int msiof3_sync_a_pins[] = {
2866 /* SYNC */
2867 RCAR_GP_PIN(0, 1),
2868 };
2869 static const unsigned int msiof3_sync_a_mux[] = {
2870 MSIOF3_SYNC_A_MARK,
2871 };
2872 static const unsigned int msiof3_ss1_a_pins[] = {
2873 /* SS1 */
2874 RCAR_GP_PIN(0, 14),
2875 };
2876 static const unsigned int msiof3_ss1_a_mux[] = {
2877 MSIOF3_SS1_A_MARK,
2878 };
2879 static const unsigned int msiof3_ss2_a_pins[] = {
2880 /* SS2 */
2881 RCAR_GP_PIN(0, 15),
2882 };
2883 static const unsigned int msiof3_ss2_a_mux[] = {
2884 MSIOF3_SS2_A_MARK,
2885 };
2886 static const unsigned int msiof3_txd_a_pins[] = {
2887 /* TXD */
2888 RCAR_GP_PIN(0, 3),
2889 };
2890 static const unsigned int msiof3_txd_a_mux[] = {
2891 MSIOF3_TXD_A_MARK,
2892 };
2893 static const unsigned int msiof3_rxd_a_pins[] = {
2894 /* RXD */
2895 RCAR_GP_PIN(0, 2),
2896 };
2897 static const unsigned int msiof3_rxd_a_mux[] = {
2898 MSIOF3_RXD_A_MARK,
2899 };
2900 static const unsigned int msiof3_clk_b_pins[] = {
2901 /* SCK */
2902 RCAR_GP_PIN(1, 2),
2903 };
2904 static const unsigned int msiof3_clk_b_mux[] = {
2905 MSIOF3_SCK_B_MARK,
2906 };
2907 static const unsigned int msiof3_sync_b_pins[] = {
2908 /* SYNC */
2909 RCAR_GP_PIN(1, 0),
2910 };
2911 static const unsigned int msiof3_sync_b_mux[] = {
2912 MSIOF3_SYNC_B_MARK,
2913 };
2914 static const unsigned int msiof3_ss1_b_pins[] = {
2915 /* SS1 */
2916 RCAR_GP_PIN(1, 4),
2917 };
2918 static const unsigned int msiof3_ss1_b_mux[] = {
2919 MSIOF3_SS1_B_MARK,
2920 };
2921 static const unsigned int msiof3_ss2_b_pins[] = {
2922 /* SS2 */
2923 RCAR_GP_PIN(1, 5),
2924 };
2925 static const unsigned int msiof3_ss2_b_mux[] = {
2926 MSIOF3_SS2_B_MARK,
2927 };
2928 static const unsigned int msiof3_txd_b_pins[] = {
2929 /* TXD */
2930 RCAR_GP_PIN(1, 1),
2931 };
2932 static const unsigned int msiof3_txd_b_mux[] = {
2933 MSIOF3_TXD_B_MARK,
2934 };
2935 static const unsigned int msiof3_rxd_b_pins[] = {
2936 /* RXD */
2937 RCAR_GP_PIN(1, 3),
2938 };
2939 static const unsigned int msiof3_rxd_b_mux[] = {
2940 MSIOF3_RXD_B_MARK,
2941 };
2942 static const unsigned int msiof3_clk_c_pins[] = {
2943 /* SCK */
2944 RCAR_GP_PIN(1, 12),
2945 };
2946 static const unsigned int msiof3_clk_c_mux[] = {
2947 MSIOF3_SCK_C_MARK,
2948 };
2949 static const unsigned int msiof3_sync_c_pins[] = {
2950 /* SYNC */
2951 RCAR_GP_PIN(1, 13),
2952 };
2953 static const unsigned int msiof3_sync_c_mux[] = {
2954 MSIOF3_SYNC_C_MARK,
2955 };
2956 static const unsigned int msiof3_txd_c_pins[] = {
2957 /* TXD */
2958 RCAR_GP_PIN(1, 15),
2959 };
2960 static const unsigned int msiof3_txd_c_mux[] = {
2961 MSIOF3_TXD_C_MARK,
2962 };
2963 static const unsigned int msiof3_rxd_c_pins[] = {
2964 /* RXD */
2965 RCAR_GP_PIN(1, 14),
2966 };
2967 static const unsigned int msiof3_rxd_c_mux[] = {
2968 MSIOF3_RXD_C_MARK,
2969 };
2970 static const unsigned int msiof3_clk_d_pins[] = {
2971 /* SCK */
2972 RCAR_GP_PIN(1, 22),
2973 };
2974 static const unsigned int msiof3_clk_d_mux[] = {
2975 MSIOF3_SCK_D_MARK,
2976 };
2977 static const unsigned int msiof3_sync_d_pins[] = {
2978 /* SYNC */
2979 RCAR_GP_PIN(1, 23),
2980 };
2981 static const unsigned int msiof3_sync_d_mux[] = {
2982 MSIOF3_SYNC_D_MARK,
2983 };
2984 static const unsigned int msiof3_ss1_d_pins[] = {
2985 /* SS1 */
2986 RCAR_GP_PIN(1, 26),
2987 };
2988 static const unsigned int msiof3_ss1_d_mux[] = {
2989 MSIOF3_SS1_D_MARK,
2990 };
2991 static const unsigned int msiof3_txd_d_pins[] = {
2992 /* TXD */
2993 RCAR_GP_PIN(1, 25),
2994 };
2995 static const unsigned int msiof3_txd_d_mux[] = {
2996 MSIOF3_TXD_D_MARK,
2997 };
2998 static const unsigned int msiof3_rxd_d_pins[] = {
2999 /* RXD */
3000 RCAR_GP_PIN(1, 24),
3001 };
3002 static const unsigned int msiof3_rxd_d_mux[] = {
3003 MSIOF3_RXD_D_MARK,
3004 };
3005
3006 /* - PWM0 --------------------------------------------------------------------*/
3007 static const unsigned int pwm0_pins[] = {
3008 /* PWM */
3009 RCAR_GP_PIN(2, 6),
3010 };
3011 static const unsigned int pwm0_mux[] = {
3012 PWM0_MARK,
3013 };
3014 /* - PWM1 --------------------------------------------------------------------*/
3015 static const unsigned int pwm1_a_pins[] = {
3016 /* PWM */
3017 RCAR_GP_PIN(2, 7),
3018 };
3019 static const unsigned int pwm1_a_mux[] = {
3020 PWM1_A_MARK,
3021 };
3022 static const unsigned int pwm1_b_pins[] = {
3023 /* PWM */
3024 RCAR_GP_PIN(1, 8),
3025 };
3026 static const unsigned int pwm1_b_mux[] = {
3027 PWM1_B_MARK,
3028 };
3029 /* - PWM2 --------------------------------------------------------------------*/
3030 static const unsigned int pwm2_a_pins[] = {
3031 /* PWM */
3032 RCAR_GP_PIN(2, 8),
3033 };
3034 static const unsigned int pwm2_a_mux[] = {
3035 PWM2_A_MARK,
3036 };
3037 static const unsigned int pwm2_b_pins[] = {
3038 /* PWM */
3039 RCAR_GP_PIN(1, 11),
3040 };
3041 static const unsigned int pwm2_b_mux[] = {
3042 PWM2_B_MARK,
3043 };
3044 /* - PWM3 --------------------------------------------------------------------*/
3045 static const unsigned int pwm3_a_pins[] = {
3046 /* PWM */
3047 RCAR_GP_PIN(1, 0),
3048 };
3049 static const unsigned int pwm3_a_mux[] = {
3050 PWM3_A_MARK,
3051 };
3052 static const unsigned int pwm3_b_pins[] = {
3053 /* PWM */
3054 RCAR_GP_PIN(2, 2),
3055 };
3056 static const unsigned int pwm3_b_mux[] = {
3057 PWM3_B_MARK,
3058 };
3059 /* - PWM4 --------------------------------------------------------------------*/
3060 static const unsigned int pwm4_a_pins[] = {
3061 /* PWM */
3062 RCAR_GP_PIN(1, 1),
3063 };
3064 static const unsigned int pwm4_a_mux[] = {
3065 PWM4_A_MARK,
3066 };
3067 static const unsigned int pwm4_b_pins[] = {
3068 /* PWM */
3069 RCAR_GP_PIN(2, 3),
3070 };
3071 static const unsigned int pwm4_b_mux[] = {
3072 PWM4_B_MARK,
3073 };
3074 /* - PWM5 --------------------------------------------------------------------*/
3075 static const unsigned int pwm5_a_pins[] = {
3076 /* PWM */
3077 RCAR_GP_PIN(1, 2),
3078 };
3079 static const unsigned int pwm5_a_mux[] = {
3080 PWM5_A_MARK,
3081 };
3082 static const unsigned int pwm5_b_pins[] = {
3083 /* PWM */
3084 RCAR_GP_PIN(2, 4),
3085 };
3086 static const unsigned int pwm5_b_mux[] = {
3087 PWM5_B_MARK,
3088 };
3089 /* - PWM6 --------------------------------------------------------------------*/
3090 static const unsigned int pwm6_a_pins[] = {
3091 /* PWM */
3092 RCAR_GP_PIN(1, 3),
3093 };
3094 static const unsigned int pwm6_a_mux[] = {
3095 PWM6_A_MARK,
3096 };
3097 static const unsigned int pwm6_b_pins[] = {
3098 /* PWM */
3099 RCAR_GP_PIN(2, 5),
3100 };
3101 static const unsigned int pwm6_b_mux[] = {
3102 PWM6_B_MARK,
3103 };
3104
3105 /* - QSPI0 ------------------------------------------------------------------ */
3106 static const unsigned int qspi0_ctrl_pins[] = {
3107 /* QSPI0_SPCLK, QSPI0_SSL */
3108 PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
3109 };
3110 static const unsigned int qspi0_ctrl_mux[] = {
3111 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3112 };
3113 static const unsigned int qspi0_data2_pins[] = {
3114 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3115 PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3116 };
3117 static const unsigned int qspi0_data2_mux[] = {
3118 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3119 };
3120 static const unsigned int qspi0_data4_pins[] = {
3121 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3122 PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3123 PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
3124 };
3125 static const unsigned int qspi0_data4_mux[] = {
3126 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3127 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3128 };
3129 /* - QSPI1 ------------------------------------------------------------------ */
3130 static const unsigned int qspi1_ctrl_pins[] = {
3131 /* QSPI1_SPCLK, QSPI1_SSL */
3132 PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
3133 };
3134 static const unsigned int qspi1_ctrl_mux[] = {
3135 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3136 };
3137 static const unsigned int qspi1_data2_pins[] = {
3138 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3139 PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3140 };
3141 static const unsigned int qspi1_data2_mux[] = {
3142 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3143 };
3144 static const unsigned int qspi1_data4_pins[] = {
3145 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3146 PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3147 PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
3148 };
3149 static const unsigned int qspi1_data4_mux[] = {
3150 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3151 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3152 };
3153
3154 /* - SATA --------------------------------------------------------------------*/
3155 static const unsigned int sata0_devslp_a_pins[] = {
3156 /* DEVSLP */
3157 RCAR_GP_PIN(6, 16),
3158 };
3159 static const unsigned int sata0_devslp_a_mux[] = {
3160 SATA_DEVSLP_A_MARK,
3161 };
3162 static const unsigned int sata0_devslp_b_pins[] = {
3163 /* DEVSLP */
3164 RCAR_GP_PIN(4, 6),
3165 };
3166 static const unsigned int sata0_devslp_b_mux[] = {
3167 SATA_DEVSLP_B_MARK,
3168 };
3169
3170 /* - SCIF0 ------------------------------------------------------------------ */
3171 static const unsigned int scif0_data_pins[] = {
3172 /* RX, TX */
3173 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3174 };
3175 static const unsigned int scif0_data_mux[] = {
3176 RX0_MARK, TX0_MARK,
3177 };
3178 static const unsigned int scif0_clk_pins[] = {
3179 /* SCK */
3180 RCAR_GP_PIN(5, 0),
3181 };
3182 static const unsigned int scif0_clk_mux[] = {
3183 SCK0_MARK,
3184 };
3185 static const unsigned int scif0_ctrl_pins[] = {
3186 /* RTS, CTS */
3187 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3188 };
3189 static const unsigned int scif0_ctrl_mux[] = {
3190 RTS0_N_TANS_MARK, CTS0_N_MARK,
3191 };
3192 /* - SCIF1 ------------------------------------------------------------------ */
3193 static const unsigned int scif1_data_a_pins[] = {
3194 /* RX, TX */
3195 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3196 };
3197 static const unsigned int scif1_data_a_mux[] = {
3198 RX1_A_MARK, TX1_A_MARK,
3199 };
3200 static const unsigned int scif1_clk_pins[] = {
3201 /* SCK */
3202 RCAR_GP_PIN(6, 21),
3203 };
3204 static const unsigned int scif1_clk_mux[] = {
3205 SCK1_MARK,
3206 };
3207 static const unsigned int scif1_ctrl_pins[] = {
3208 /* RTS, CTS */
3209 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3210 };
3211 static const unsigned int scif1_ctrl_mux[] = {
3212 RTS1_N_TANS_MARK, CTS1_N_MARK,
3213 };
3214
3215 static const unsigned int scif1_data_b_pins[] = {
3216 /* RX, TX */
3217 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3218 };
3219 static const unsigned int scif1_data_b_mux[] = {
3220 RX1_B_MARK, TX1_B_MARK,
3221 };
3222 /* - SCIF2 ------------------------------------------------------------------ */
3223 static const unsigned int scif2_data_a_pins[] = {
3224 /* RX, TX */
3225 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3226 };
3227 static const unsigned int scif2_data_a_mux[] = {
3228 RX2_A_MARK, TX2_A_MARK,
3229 };
3230 static const unsigned int scif2_clk_pins[] = {
3231 /* SCK */
3232 RCAR_GP_PIN(5, 9),
3233 };
3234 static const unsigned int scif2_clk_mux[] = {
3235 SCK2_MARK,
3236 };
3237 static const unsigned int scif2_data_b_pins[] = {
3238 /* RX, TX */
3239 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3240 };
3241 static const unsigned int scif2_data_b_mux[] = {
3242 RX2_B_MARK, TX2_B_MARK,
3243 };
3244 /* - SCIF3 ------------------------------------------------------------------ */
3245 static const unsigned int scif3_data_a_pins[] = {
3246 /* RX, TX */
3247 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3248 };
3249 static const unsigned int scif3_data_a_mux[] = {
3250 RX3_A_MARK, TX3_A_MARK,
3251 };
3252 static const unsigned int scif3_clk_pins[] = {
3253 /* SCK */
3254 RCAR_GP_PIN(1, 22),
3255 };
3256 static const unsigned int scif3_clk_mux[] = {
3257 SCK3_MARK,
3258 };
3259 static const unsigned int scif3_ctrl_pins[] = {
3260 /* RTS, CTS */
3261 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3262 };
3263 static const unsigned int scif3_ctrl_mux[] = {
3264 RTS3_N_TANS_MARK, CTS3_N_MARK,
3265 };
3266 static const unsigned int scif3_data_b_pins[] = {
3267 /* RX, TX */
3268 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3269 };
3270 static const unsigned int scif3_data_b_mux[] = {
3271 RX3_B_MARK, TX3_B_MARK,
3272 };
3273 /* - SCIF4 ------------------------------------------------------------------ */
3274 static const unsigned int scif4_data_a_pins[] = {
3275 /* RX, TX */
3276 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3277 };
3278 static const unsigned int scif4_data_a_mux[] = {
3279 RX4_A_MARK, TX4_A_MARK,
3280 };
3281 static const unsigned int scif4_clk_a_pins[] = {
3282 /* SCK */
3283 RCAR_GP_PIN(2, 10),
3284 };
3285 static const unsigned int scif4_clk_a_mux[] = {
3286 SCK4_A_MARK,
3287 };
3288 static const unsigned int scif4_ctrl_a_pins[] = {
3289 /* RTS, CTS */
3290 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3291 };
3292 static const unsigned int scif4_ctrl_a_mux[] = {
3293 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3294 };
3295 static const unsigned int scif4_data_b_pins[] = {
3296 /* RX, TX */
3297 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3298 };
3299 static const unsigned int scif4_data_b_mux[] = {
3300 RX4_B_MARK, TX4_B_MARK,
3301 };
3302 static const unsigned int scif4_clk_b_pins[] = {
3303 /* SCK */
3304 RCAR_GP_PIN(1, 5),
3305 };
3306 static const unsigned int scif4_clk_b_mux[] = {
3307 SCK4_B_MARK,
3308 };
3309 static const unsigned int scif4_ctrl_b_pins[] = {
3310 /* RTS, CTS */
3311 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3312 };
3313 static const unsigned int scif4_ctrl_b_mux[] = {
3314 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3315 };
3316 static const unsigned int scif4_data_c_pins[] = {
3317 /* RX, TX */
3318 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3319 };
3320 static const unsigned int scif4_data_c_mux[] = {
3321 RX4_C_MARK, TX4_C_MARK,
3322 };
3323 static const unsigned int scif4_clk_c_pins[] = {
3324 /* SCK */
3325 RCAR_GP_PIN(0, 8),
3326 };
3327 static const unsigned int scif4_clk_c_mux[] = {
3328 SCK4_C_MARK,
3329 };
3330 static const unsigned int scif4_ctrl_c_pins[] = {
3331 /* RTS, CTS */
3332 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3333 };
3334 static const unsigned int scif4_ctrl_c_mux[] = {
3335 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3336 };
3337 /* - SCIF5 ------------------------------------------------------------------ */
3338 static const unsigned int scif5_data_pins[] = {
3339 /* RX, TX */
3340 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3341 };
3342 static const unsigned int scif5_data_mux[] = {
3343 RX5_MARK, TX5_MARK,
3344 };
3345 static const unsigned int scif5_clk_pins[] = {
3346 /* SCK */
3347 RCAR_GP_PIN(6, 21),
3348 };
3349 static const unsigned int scif5_clk_mux[] = {
3350 SCK5_MARK,
3351 };
3352
3353 /* - SCIF Clock ------------------------------------------------------------- */
3354 static const unsigned int scif_clk_a_pins[] = {
3355 /* SCIF_CLK */
3356 RCAR_GP_PIN(6, 23),
3357 };
3358 static const unsigned int scif_clk_a_mux[] = {
3359 SCIF_CLK_A_MARK,
3360 };
3361 static const unsigned int scif_clk_b_pins[] = {
3362 /* SCIF_CLK */
3363 RCAR_GP_PIN(5, 9),
3364 };
3365 static const unsigned int scif_clk_b_mux[] = {
3366 SCIF_CLK_B_MARK,
3367 };
3368
3369 /* - SDHI0 ------------------------------------------------------------------ */
3370 static const unsigned int sdhi0_data1_pins[] = {
3371 /* D0 */
3372 RCAR_GP_PIN(3, 2),
3373 };
3374 static const unsigned int sdhi0_data1_mux[] = {
3375 SD0_DAT0_MARK,
3376 };
3377 static const unsigned int sdhi0_data4_pins[] = {
3378 /* D[0:3] */
3379 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3380 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3381 };
3382 static const unsigned int sdhi0_data4_mux[] = {
3383 SD0_DAT0_MARK, SD0_DAT1_MARK,
3384 SD0_DAT2_MARK, SD0_DAT3_MARK,
3385 };
3386 static const unsigned int sdhi0_ctrl_pins[] = {
3387 /* CLK, CMD */
3388 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3389 };
3390 static const unsigned int sdhi0_ctrl_mux[] = {
3391 SD0_CLK_MARK, SD0_CMD_MARK,
3392 };
3393 static const unsigned int sdhi0_cd_pins[] = {
3394 /* CD */
3395 RCAR_GP_PIN(3, 12),
3396 };
3397 static const unsigned int sdhi0_cd_mux[] = {
3398 SD0_CD_MARK,
3399 };
3400 static const unsigned int sdhi0_wp_pins[] = {
3401 /* WP */
3402 RCAR_GP_PIN(3, 13),
3403 };
3404 static const unsigned int sdhi0_wp_mux[] = {
3405 SD0_WP_MARK,
3406 };
3407 /* - SDHI1 ------------------------------------------------------------------ */
3408 static const unsigned int sdhi1_data1_pins[] = {
3409 /* D0 */
3410 RCAR_GP_PIN(3, 8),
3411 };
3412 static const unsigned int sdhi1_data1_mux[] = {
3413 SD1_DAT0_MARK,
3414 };
3415 static const unsigned int sdhi1_data4_pins[] = {
3416 /* D[0:3] */
3417 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3418 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3419 };
3420 static const unsigned int sdhi1_data4_mux[] = {
3421 SD1_DAT0_MARK, SD1_DAT1_MARK,
3422 SD1_DAT2_MARK, SD1_DAT3_MARK,
3423 };
3424 static const unsigned int sdhi1_ctrl_pins[] = {
3425 /* CLK, CMD */
3426 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3427 };
3428 static const unsigned int sdhi1_ctrl_mux[] = {
3429 SD1_CLK_MARK, SD1_CMD_MARK,
3430 };
3431 static const unsigned int sdhi1_cd_pins[] = {
3432 /* CD */
3433 RCAR_GP_PIN(3, 14),
3434 };
3435 static const unsigned int sdhi1_cd_mux[] = {
3436 SD1_CD_MARK,
3437 };
3438 static const unsigned int sdhi1_wp_pins[] = {
3439 /* WP */
3440 RCAR_GP_PIN(3, 15),
3441 };
3442 static const unsigned int sdhi1_wp_mux[] = {
3443 SD1_WP_MARK,
3444 };
3445 /* - SDHI2 ------------------------------------------------------------------ */
3446 static const unsigned int sdhi2_data1_pins[] = {
3447 /* D0 */
3448 RCAR_GP_PIN(4, 2),
3449 };
3450 static const unsigned int sdhi2_data1_mux[] = {
3451 SD2_DAT0_MARK,
3452 };
3453 static const unsigned int sdhi2_data4_pins[] = {
3454 /* D[0:3] */
3455 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3456 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3457 };
3458 static const unsigned int sdhi2_data4_mux[] = {
3459 SD2_DAT0_MARK, SD2_DAT1_MARK,
3460 SD2_DAT2_MARK, SD2_DAT3_MARK,
3461 };
3462 static const unsigned int sdhi2_data8_pins[] = {
3463 /* D[0:7] */
3464 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3465 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3466 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3467 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3468 };
3469 static const unsigned int sdhi2_data8_mux[] = {
3470 SD2_DAT0_MARK, SD2_DAT1_MARK,
3471 SD2_DAT2_MARK, SD2_DAT3_MARK,
3472 SD2_DAT4_MARK, SD2_DAT5_MARK,
3473 SD2_DAT6_MARK, SD2_DAT7_MARK,
3474 };
3475 static const unsigned int sdhi2_ctrl_pins[] = {
3476 /* CLK, CMD */
3477 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3478 };
3479 static const unsigned int sdhi2_ctrl_mux[] = {
3480 SD2_CLK_MARK, SD2_CMD_MARK,
3481 };
3482 static const unsigned int sdhi2_cd_a_pins[] = {
3483 /* CD */
3484 RCAR_GP_PIN(4, 13),
3485 };
3486 static const unsigned int sdhi2_cd_a_mux[] = {
3487 SD2_CD_A_MARK,
3488 };
3489 static const unsigned int sdhi2_cd_b_pins[] = {
3490 /* CD */
3491 RCAR_GP_PIN(5, 10),
3492 };
3493 static const unsigned int sdhi2_cd_b_mux[] = {
3494 SD2_CD_B_MARK,
3495 };
3496 static const unsigned int sdhi2_wp_a_pins[] = {
3497 /* WP */
3498 RCAR_GP_PIN(4, 14),
3499 };
3500 static const unsigned int sdhi2_wp_a_mux[] = {
3501 SD2_WP_A_MARK,
3502 };
3503 static const unsigned int sdhi2_wp_b_pins[] = {
3504 /* WP */
3505 RCAR_GP_PIN(5, 11),
3506 };
3507 static const unsigned int sdhi2_wp_b_mux[] = {
3508 SD2_WP_B_MARK,
3509 };
3510 static const unsigned int sdhi2_ds_pins[] = {
3511 /* DS */
3512 RCAR_GP_PIN(4, 6),
3513 };
3514 static const unsigned int sdhi2_ds_mux[] = {
3515 SD2_DS_MARK,
3516 };
3517 /* - SDHI3 ------------------------------------------------------------------ */
3518 static const unsigned int sdhi3_data1_pins[] = {
3519 /* D0 */
3520 RCAR_GP_PIN(4, 9),
3521 };
3522 static const unsigned int sdhi3_data1_mux[] = {
3523 SD3_DAT0_MARK,
3524 };
3525 static const unsigned int sdhi3_data4_pins[] = {
3526 /* D[0:3] */
3527 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3528 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3529 };
3530 static const unsigned int sdhi3_data4_mux[] = {
3531 SD3_DAT0_MARK, SD3_DAT1_MARK,
3532 SD3_DAT2_MARK, SD3_DAT3_MARK,
3533 };
3534 static const unsigned int sdhi3_data8_pins[] = {
3535 /* D[0:7] */
3536 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3537 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3538 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3539 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3540 };
3541 static const unsigned int sdhi3_data8_mux[] = {
3542 SD3_DAT0_MARK, SD3_DAT1_MARK,
3543 SD3_DAT2_MARK, SD3_DAT3_MARK,
3544 SD3_DAT4_MARK, SD3_DAT5_MARK,
3545 SD3_DAT6_MARK, SD3_DAT7_MARK,
3546 };
3547 static const unsigned int sdhi3_ctrl_pins[] = {
3548 /* CLK, CMD */
3549 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3550 };
3551 static const unsigned int sdhi3_ctrl_mux[] = {
3552 SD3_CLK_MARK, SD3_CMD_MARK,
3553 };
3554 static const unsigned int sdhi3_cd_pins[] = {
3555 /* CD */
3556 RCAR_GP_PIN(4, 15),
3557 };
3558 static const unsigned int sdhi3_cd_mux[] = {
3559 SD3_CD_MARK,
3560 };
3561 static const unsigned int sdhi3_wp_pins[] = {
3562 /* WP */
3563 RCAR_GP_PIN(4, 16),
3564 };
3565 static const unsigned int sdhi3_wp_mux[] = {
3566 SD3_WP_MARK,
3567 };
3568 static const unsigned int sdhi3_ds_pins[] = {
3569 /* DS */
3570 RCAR_GP_PIN(4, 17),
3571 };
3572 static const unsigned int sdhi3_ds_mux[] = {
3573 SD3_DS_MARK,
3574 };
3575
3576 /* - SSI -------------------------------------------------------------------- */
3577 static const unsigned int ssi0_data_pins[] = {
3578 /* SDATA */
3579 RCAR_GP_PIN(6, 2),
3580 };
3581 static const unsigned int ssi0_data_mux[] = {
3582 SSI_SDATA0_MARK,
3583 };
3584 static const unsigned int ssi01239_ctrl_pins[] = {
3585 /* SCK, WS */
3586 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3587 };
3588 static const unsigned int ssi01239_ctrl_mux[] = {
3589 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3590 };
3591 static const unsigned int ssi1_data_a_pins[] = {
3592 /* SDATA */
3593 RCAR_GP_PIN(6, 3),
3594 };
3595 static const unsigned int ssi1_data_a_mux[] = {
3596 SSI_SDATA1_A_MARK,
3597 };
3598 static const unsigned int ssi1_data_b_pins[] = {
3599 /* SDATA */
3600 RCAR_GP_PIN(5, 12),
3601 };
3602 static const unsigned int ssi1_data_b_mux[] = {
3603 SSI_SDATA1_B_MARK,
3604 };
3605 static const unsigned int ssi1_ctrl_a_pins[] = {
3606 /* SCK, WS */
3607 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3608 };
3609 static const unsigned int ssi1_ctrl_a_mux[] = {
3610 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3611 };
3612 static const unsigned int ssi1_ctrl_b_pins[] = {
3613 /* SCK, WS */
3614 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3615 };
3616 static const unsigned int ssi1_ctrl_b_mux[] = {
3617 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3618 };
3619 static const unsigned int ssi2_data_a_pins[] = {
3620 /* SDATA */
3621 RCAR_GP_PIN(6, 4),
3622 };
3623 static const unsigned int ssi2_data_a_mux[] = {
3624 SSI_SDATA2_A_MARK,
3625 };
3626 static const unsigned int ssi2_data_b_pins[] = {
3627 /* SDATA */
3628 RCAR_GP_PIN(5, 13),
3629 };
3630 static const unsigned int ssi2_data_b_mux[] = {
3631 SSI_SDATA2_B_MARK,
3632 };
3633 static const unsigned int ssi2_ctrl_a_pins[] = {
3634 /* SCK, WS */
3635 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3636 };
3637 static const unsigned int ssi2_ctrl_a_mux[] = {
3638 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3639 };
3640 static const unsigned int ssi2_ctrl_b_pins[] = {
3641 /* SCK, WS */
3642 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3643 };
3644 static const unsigned int ssi2_ctrl_b_mux[] = {
3645 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3646 };
3647 static const unsigned int ssi3_data_pins[] = {
3648 /* SDATA */
3649 RCAR_GP_PIN(6, 7),
3650 };
3651 static const unsigned int ssi3_data_mux[] = {
3652 SSI_SDATA3_MARK,
3653 };
3654 static const unsigned int ssi349_ctrl_pins[] = {
3655 /* SCK, WS */
3656 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3657 };
3658 static const unsigned int ssi349_ctrl_mux[] = {
3659 SSI_SCK349_MARK, SSI_WS349_MARK,
3660 };
3661 static const unsigned int ssi4_data_pins[] = {
3662 /* SDATA */
3663 RCAR_GP_PIN(6, 10),
3664 };
3665 static const unsigned int ssi4_data_mux[] = {
3666 SSI_SDATA4_MARK,
3667 };
3668 static const unsigned int ssi4_ctrl_pins[] = {
3669 /* SCK, WS */
3670 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3671 };
3672 static const unsigned int ssi4_ctrl_mux[] = {
3673 SSI_SCK4_MARK, SSI_WS4_MARK,
3674 };
3675 static const unsigned int ssi5_data_pins[] = {
3676 /* SDATA */
3677 RCAR_GP_PIN(6, 13),
3678 };
3679 static const unsigned int ssi5_data_mux[] = {
3680 SSI_SDATA5_MARK,
3681 };
3682 static const unsigned int ssi5_ctrl_pins[] = {
3683 /* SCK, WS */
3684 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3685 };
3686 static const unsigned int ssi5_ctrl_mux[] = {
3687 SSI_SCK5_MARK, SSI_WS5_MARK,
3688 };
3689 static const unsigned int ssi6_data_pins[] = {
3690 /* SDATA */
3691 RCAR_GP_PIN(6, 16),
3692 };
3693 static const unsigned int ssi6_data_mux[] = {
3694 SSI_SDATA6_MARK,
3695 };
3696 static const unsigned int ssi6_ctrl_pins[] = {
3697 /* SCK, WS */
3698 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3699 };
3700 static const unsigned int ssi6_ctrl_mux[] = {
3701 SSI_SCK6_MARK, SSI_WS6_MARK,
3702 };
3703 static const unsigned int ssi7_data_pins[] = {
3704 /* SDATA */
3705 RCAR_GP_PIN(6, 19),
3706 };
3707 static const unsigned int ssi7_data_mux[] = {
3708 SSI_SDATA7_MARK,
3709 };
3710 static const unsigned int ssi78_ctrl_pins[] = {
3711 /* SCK, WS */
3712 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3713 };
3714 static const unsigned int ssi78_ctrl_mux[] = {
3715 SSI_SCK78_MARK, SSI_WS78_MARK,
3716 };
3717 static const unsigned int ssi8_data_pins[] = {
3718 /* SDATA */
3719 RCAR_GP_PIN(6, 20),
3720 };
3721 static const unsigned int ssi8_data_mux[] = {
3722 SSI_SDATA8_MARK,
3723 };
3724 static const unsigned int ssi9_data_a_pins[] = {
3725 /* SDATA */
3726 RCAR_GP_PIN(6, 21),
3727 };
3728 static const unsigned int ssi9_data_a_mux[] = {
3729 SSI_SDATA9_A_MARK,
3730 };
3731 static const unsigned int ssi9_data_b_pins[] = {
3732 /* SDATA */
3733 RCAR_GP_PIN(5, 14),
3734 };
3735 static const unsigned int ssi9_data_b_mux[] = {
3736 SSI_SDATA9_B_MARK,
3737 };
3738 static const unsigned int ssi9_ctrl_a_pins[] = {
3739 /* SCK, WS */
3740 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3741 };
3742 static const unsigned int ssi9_ctrl_a_mux[] = {
3743 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3744 };
3745 static const unsigned int ssi9_ctrl_b_pins[] = {
3746 /* SCK, WS */
3747 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3748 };
3749 static const unsigned int ssi9_ctrl_b_mux[] = {
3750 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3751 };
3752
3753 /* - USB0 ------------------------------------------------------------------- */
3754 static const unsigned int usb0_pins[] = {
3755 /* PWEN, OVC */
3756 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3757 };
3758 static const unsigned int usb0_mux[] = {
3759 USB0_PWEN_MARK, USB0_OVC_MARK,
3760 };
3761 /* - USB1 ------------------------------------------------------------------- */
3762 static const unsigned int usb1_pins[] = {
3763 /* PWEN, OVC */
3764 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3765 };
3766 static const unsigned int usb1_mux[] = {
3767 USB1_PWEN_MARK, USB1_OVC_MARK,
3768 };
3769 /* - USB2 ------------------------------------------------------------------- */
3770 static const unsigned int usb2_pins[] = {
3771 /* PWEN, OVC */
3772 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3773 };
3774 static const unsigned int usb2_mux[] = {
3775 USB2_PWEN_MARK, USB2_OVC_MARK,
3776 };
3777
3778 /* - USB30 ------------------------------------------------------------------ */
3779 static const unsigned int usb30_pins[] = {
3780 /* PWEN, OVC */
3781 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3782 };
3783 static const unsigned int usb30_mux[] = {
3784 USB30_PWEN_MARK, USB30_OVC_MARK,
3785 };
3786 /* - USB31 ------------------------------------------------------------------ */
3787 static const unsigned int usb31_pins[] = {
3788 /* PWEN, OVC */
3789 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3790 };
3791 static const unsigned int usb31_mux[] = {
3792 USB31_PWEN_MARK, USB31_OVC_MARK,
3793 };
3794
3795 static const struct sh_pfc_pin_group pinmux_groups[] = {
3796 SH_PFC_PIN_GROUP(audio_clk_a_a),
3797 SH_PFC_PIN_GROUP(audio_clk_a_b),
3798 SH_PFC_PIN_GROUP(audio_clk_a_c),
3799 SH_PFC_PIN_GROUP(audio_clk_b_a),
3800 SH_PFC_PIN_GROUP(audio_clk_b_b),
3801 SH_PFC_PIN_GROUP(audio_clk_c_a),
3802 SH_PFC_PIN_GROUP(audio_clk_c_b),
3803 SH_PFC_PIN_GROUP(audio_clkout_a),
3804 SH_PFC_PIN_GROUP(audio_clkout_b),
3805 SH_PFC_PIN_GROUP(audio_clkout_c),
3806 SH_PFC_PIN_GROUP(audio_clkout_d),
3807 SH_PFC_PIN_GROUP(audio_clkout1_a),
3808 SH_PFC_PIN_GROUP(audio_clkout1_b),
3809 SH_PFC_PIN_GROUP(audio_clkout2_a),
3810 SH_PFC_PIN_GROUP(audio_clkout2_b),
3811 SH_PFC_PIN_GROUP(audio_clkout3_a),
3812 SH_PFC_PIN_GROUP(audio_clkout3_b),
3813 SH_PFC_PIN_GROUP(avb_link),
3814 SH_PFC_PIN_GROUP(avb_magic),
3815 SH_PFC_PIN_GROUP(avb_phy_int),
3816 SH_PFC_PIN_GROUP(avb_mdc),
3817 SH_PFC_PIN_GROUP(avb_mii),
3818 SH_PFC_PIN_GROUP(avb_avtp_pps),
3819 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3820 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3821 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3822 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3823 SH_PFC_PIN_GROUP(can0_data_a),
3824 SH_PFC_PIN_GROUP(can0_data_b),
3825 SH_PFC_PIN_GROUP(can1_data),
3826 SH_PFC_PIN_GROUP(can_clk),
3827 SH_PFC_PIN_GROUP(canfd0_data_a),
3828 SH_PFC_PIN_GROUP(canfd0_data_b),
3829 SH_PFC_PIN_GROUP(canfd1_data),
3830 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3831 SH_PFC_PIN_GROUP(drif0_data0_a),
3832 SH_PFC_PIN_GROUP(drif0_data1_a),
3833 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3834 SH_PFC_PIN_GROUP(drif0_data0_b),
3835 SH_PFC_PIN_GROUP(drif0_data1_b),
3836 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3837 SH_PFC_PIN_GROUP(drif0_data0_c),
3838 SH_PFC_PIN_GROUP(drif0_data1_c),
3839 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3840 SH_PFC_PIN_GROUP(drif1_data0_a),
3841 SH_PFC_PIN_GROUP(drif1_data1_a),
3842 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3843 SH_PFC_PIN_GROUP(drif1_data0_b),
3844 SH_PFC_PIN_GROUP(drif1_data1_b),
3845 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3846 SH_PFC_PIN_GROUP(drif1_data0_c),
3847 SH_PFC_PIN_GROUP(drif1_data1_c),
3848 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3849 SH_PFC_PIN_GROUP(drif2_data0_a),
3850 SH_PFC_PIN_GROUP(drif2_data1_a),
3851 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3852 SH_PFC_PIN_GROUP(drif2_data0_b),
3853 SH_PFC_PIN_GROUP(drif2_data1_b),
3854 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3855 SH_PFC_PIN_GROUP(drif3_data0_a),
3856 SH_PFC_PIN_GROUP(drif3_data1_a),
3857 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3858 SH_PFC_PIN_GROUP(drif3_data0_b),
3859 SH_PFC_PIN_GROUP(drif3_data1_b),
3860 SH_PFC_PIN_GROUP(du_rgb666),
3861 SH_PFC_PIN_GROUP(du_rgb888),
3862 SH_PFC_PIN_GROUP(du_clk_out_0),
3863 SH_PFC_PIN_GROUP(du_clk_out_1),
3864 SH_PFC_PIN_GROUP(du_sync),
3865 SH_PFC_PIN_GROUP(du_oddf),
3866 SH_PFC_PIN_GROUP(du_cde),
3867 SH_PFC_PIN_GROUP(du_disp),
3868 SH_PFC_PIN_GROUP(hscif0_data),
3869 SH_PFC_PIN_GROUP(hscif0_clk),
3870 SH_PFC_PIN_GROUP(hscif0_ctrl),
3871 SH_PFC_PIN_GROUP(hscif1_data_a),
3872 SH_PFC_PIN_GROUP(hscif1_clk_a),
3873 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3874 SH_PFC_PIN_GROUP(hscif1_data_b),
3875 SH_PFC_PIN_GROUP(hscif1_clk_b),
3876 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3877 SH_PFC_PIN_GROUP(hscif2_data_a),
3878 SH_PFC_PIN_GROUP(hscif2_clk_a),
3879 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3880 SH_PFC_PIN_GROUP(hscif2_data_b),
3881 SH_PFC_PIN_GROUP(hscif2_clk_b),
3882 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3883 SH_PFC_PIN_GROUP(hscif3_data_a),
3884 SH_PFC_PIN_GROUP(hscif3_clk),
3885 SH_PFC_PIN_GROUP(hscif3_ctrl),
3886 SH_PFC_PIN_GROUP(hscif3_data_b),
3887 SH_PFC_PIN_GROUP(hscif3_data_c),
3888 SH_PFC_PIN_GROUP(hscif3_data_d),
3889 SH_PFC_PIN_GROUP(hscif4_data_a),
3890 SH_PFC_PIN_GROUP(hscif4_clk),
3891 SH_PFC_PIN_GROUP(hscif4_ctrl),
3892 SH_PFC_PIN_GROUP(hscif4_data_b),
3893 SH_PFC_PIN_GROUP(i2c1_a),
3894 SH_PFC_PIN_GROUP(i2c1_b),
3895 SH_PFC_PIN_GROUP(i2c2_a),
3896 SH_PFC_PIN_GROUP(i2c2_b),
3897 SH_PFC_PIN_GROUP(i2c6_a),
3898 SH_PFC_PIN_GROUP(i2c6_b),
3899 SH_PFC_PIN_GROUP(i2c6_c),
3900 SH_PFC_PIN_GROUP(intc_ex_irq0),
3901 SH_PFC_PIN_GROUP(intc_ex_irq1),
3902 SH_PFC_PIN_GROUP(intc_ex_irq2),
3903 SH_PFC_PIN_GROUP(intc_ex_irq3),
3904 SH_PFC_PIN_GROUP(intc_ex_irq4),
3905 SH_PFC_PIN_GROUP(intc_ex_irq5),
3906 SH_PFC_PIN_GROUP(msiof0_clk),
3907 SH_PFC_PIN_GROUP(msiof0_sync),
3908 SH_PFC_PIN_GROUP(msiof0_ss1),
3909 SH_PFC_PIN_GROUP(msiof0_ss2),
3910 SH_PFC_PIN_GROUP(msiof0_txd),
3911 SH_PFC_PIN_GROUP(msiof0_rxd),
3912 SH_PFC_PIN_GROUP(msiof1_clk_a),
3913 SH_PFC_PIN_GROUP(msiof1_sync_a),
3914 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3915 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3916 SH_PFC_PIN_GROUP(msiof1_txd_a),
3917 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3918 SH_PFC_PIN_GROUP(msiof1_clk_b),
3919 SH_PFC_PIN_GROUP(msiof1_sync_b),
3920 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3921 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3922 SH_PFC_PIN_GROUP(msiof1_txd_b),
3923 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3924 SH_PFC_PIN_GROUP(msiof1_clk_c),
3925 SH_PFC_PIN_GROUP(msiof1_sync_c),
3926 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3927 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3928 SH_PFC_PIN_GROUP(msiof1_txd_c),
3929 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3930 SH_PFC_PIN_GROUP(msiof1_clk_d),
3931 SH_PFC_PIN_GROUP(msiof1_sync_d),
3932 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3933 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3934 SH_PFC_PIN_GROUP(msiof1_txd_d),
3935 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3936 SH_PFC_PIN_GROUP(msiof1_clk_e),
3937 SH_PFC_PIN_GROUP(msiof1_sync_e),
3938 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3939 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3940 SH_PFC_PIN_GROUP(msiof1_txd_e),
3941 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3942 SH_PFC_PIN_GROUP(msiof1_clk_f),
3943 SH_PFC_PIN_GROUP(msiof1_sync_f),
3944 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3945 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3946 SH_PFC_PIN_GROUP(msiof1_txd_f),
3947 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3948 SH_PFC_PIN_GROUP(msiof1_clk_g),
3949 SH_PFC_PIN_GROUP(msiof1_sync_g),
3950 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3951 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3952 SH_PFC_PIN_GROUP(msiof1_txd_g),
3953 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3954 SH_PFC_PIN_GROUP(msiof2_clk_a),
3955 SH_PFC_PIN_GROUP(msiof2_sync_a),
3956 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3957 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3958 SH_PFC_PIN_GROUP(msiof2_txd_a),
3959 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3960 SH_PFC_PIN_GROUP(msiof2_clk_b),
3961 SH_PFC_PIN_GROUP(msiof2_sync_b),
3962 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3963 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3964 SH_PFC_PIN_GROUP(msiof2_txd_b),
3965 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3966 SH_PFC_PIN_GROUP(msiof2_clk_c),
3967 SH_PFC_PIN_GROUP(msiof2_sync_c),
3968 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3969 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3970 SH_PFC_PIN_GROUP(msiof2_txd_c),
3971 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3972 SH_PFC_PIN_GROUP(msiof2_clk_d),
3973 SH_PFC_PIN_GROUP(msiof2_sync_d),
3974 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3975 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3976 SH_PFC_PIN_GROUP(msiof2_txd_d),
3977 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3978 SH_PFC_PIN_GROUP(msiof3_clk_a),
3979 SH_PFC_PIN_GROUP(msiof3_sync_a),
3980 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3981 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3982 SH_PFC_PIN_GROUP(msiof3_txd_a),
3983 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3984 SH_PFC_PIN_GROUP(msiof3_clk_b),
3985 SH_PFC_PIN_GROUP(msiof3_sync_b),
3986 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3987 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3988 SH_PFC_PIN_GROUP(msiof3_txd_b),
3989 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3990 SH_PFC_PIN_GROUP(msiof3_clk_c),
3991 SH_PFC_PIN_GROUP(msiof3_sync_c),
3992 SH_PFC_PIN_GROUP(msiof3_txd_c),
3993 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3994 SH_PFC_PIN_GROUP(msiof3_clk_d),
3995 SH_PFC_PIN_GROUP(msiof3_sync_d),
3996 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3997 SH_PFC_PIN_GROUP(msiof3_txd_d),
3998 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3999 SH_PFC_PIN_GROUP(pwm0),
4000 SH_PFC_PIN_GROUP(pwm1_a),
4001 SH_PFC_PIN_GROUP(pwm1_b),
4002 SH_PFC_PIN_GROUP(pwm2_a),
4003 SH_PFC_PIN_GROUP(pwm2_b),
4004 SH_PFC_PIN_GROUP(pwm3_a),
4005 SH_PFC_PIN_GROUP(pwm3_b),
4006 SH_PFC_PIN_GROUP(pwm4_a),
4007 SH_PFC_PIN_GROUP(pwm4_b),
4008 SH_PFC_PIN_GROUP(pwm5_a),
4009 SH_PFC_PIN_GROUP(pwm5_b),
4010 SH_PFC_PIN_GROUP(pwm6_a),
4011 SH_PFC_PIN_GROUP(pwm6_b),
4012 SH_PFC_PIN_GROUP(qspi0_ctrl),
4013 SH_PFC_PIN_GROUP(qspi0_data2),
4014 SH_PFC_PIN_GROUP(qspi0_data4),
4015 SH_PFC_PIN_GROUP(qspi1_ctrl),
4016 SH_PFC_PIN_GROUP(qspi1_data2),
4017 SH_PFC_PIN_GROUP(qspi1_data4),
4018 SH_PFC_PIN_GROUP(sata0_devslp_a),
4019 SH_PFC_PIN_GROUP(sata0_devslp_b),
4020 SH_PFC_PIN_GROUP(scif0_data),
4021 SH_PFC_PIN_GROUP(scif0_clk),
4022 SH_PFC_PIN_GROUP(scif0_ctrl),
4023 SH_PFC_PIN_GROUP(scif1_data_a),
4024 SH_PFC_PIN_GROUP(scif1_clk),
4025 SH_PFC_PIN_GROUP(scif1_ctrl),
4026 SH_PFC_PIN_GROUP(scif1_data_b),
4027 SH_PFC_PIN_GROUP(scif2_data_a),
4028 SH_PFC_PIN_GROUP(scif2_clk),
4029 SH_PFC_PIN_GROUP(scif2_data_b),
4030 SH_PFC_PIN_GROUP(scif3_data_a),
4031 SH_PFC_PIN_GROUP(scif3_clk),
4032 SH_PFC_PIN_GROUP(scif3_ctrl),
4033 SH_PFC_PIN_GROUP(scif3_data_b),
4034 SH_PFC_PIN_GROUP(scif4_data_a),
4035 SH_PFC_PIN_GROUP(scif4_clk_a),
4036 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4037 SH_PFC_PIN_GROUP(scif4_data_b),
4038 SH_PFC_PIN_GROUP(scif4_clk_b),
4039 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4040 SH_PFC_PIN_GROUP(scif4_data_c),
4041 SH_PFC_PIN_GROUP(scif4_clk_c),
4042 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4043 SH_PFC_PIN_GROUP(scif5_data),
4044 SH_PFC_PIN_GROUP(scif5_clk),
4045 SH_PFC_PIN_GROUP(scif_clk_a),
4046 SH_PFC_PIN_GROUP(scif_clk_b),
4047 SH_PFC_PIN_GROUP(sdhi0_data1),
4048 SH_PFC_PIN_GROUP(sdhi0_data4),
4049 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4050 SH_PFC_PIN_GROUP(sdhi0_cd),
4051 SH_PFC_PIN_GROUP(sdhi0_wp),
4052 SH_PFC_PIN_GROUP(sdhi1_data1),
4053 SH_PFC_PIN_GROUP(sdhi1_data4),
4054 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4055 SH_PFC_PIN_GROUP(sdhi1_cd),
4056 SH_PFC_PIN_GROUP(sdhi1_wp),
4057 SH_PFC_PIN_GROUP(sdhi2_data1),
4058 SH_PFC_PIN_GROUP(sdhi2_data4),
4059 SH_PFC_PIN_GROUP(sdhi2_data8),
4060 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4061 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4062 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4063 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4064 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4065 SH_PFC_PIN_GROUP(sdhi2_ds),
4066 SH_PFC_PIN_GROUP(sdhi3_data1),
4067 SH_PFC_PIN_GROUP(sdhi3_data4),
4068 SH_PFC_PIN_GROUP(sdhi3_data8),
4069 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4070 SH_PFC_PIN_GROUP(sdhi3_cd),
4071 SH_PFC_PIN_GROUP(sdhi3_wp),
4072 SH_PFC_PIN_GROUP(sdhi3_ds),
4073 SH_PFC_PIN_GROUP(ssi0_data),
4074 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4075 SH_PFC_PIN_GROUP(ssi1_data_a),
4076 SH_PFC_PIN_GROUP(ssi1_data_b),
4077 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4078 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4079 SH_PFC_PIN_GROUP(ssi2_data_a),
4080 SH_PFC_PIN_GROUP(ssi2_data_b),
4081 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4082 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4083 SH_PFC_PIN_GROUP(ssi3_data),
4084 SH_PFC_PIN_GROUP(ssi349_ctrl),
4085 SH_PFC_PIN_GROUP(ssi4_data),
4086 SH_PFC_PIN_GROUP(ssi4_ctrl),
4087 SH_PFC_PIN_GROUP(ssi5_data),
4088 SH_PFC_PIN_GROUP(ssi5_ctrl),
4089 SH_PFC_PIN_GROUP(ssi6_data),
4090 SH_PFC_PIN_GROUP(ssi6_ctrl),
4091 SH_PFC_PIN_GROUP(ssi7_data),
4092 SH_PFC_PIN_GROUP(ssi78_ctrl),
4093 SH_PFC_PIN_GROUP(ssi8_data),
4094 SH_PFC_PIN_GROUP(ssi9_data_a),
4095 SH_PFC_PIN_GROUP(ssi9_data_b),
4096 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4097 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4098 SH_PFC_PIN_GROUP(usb0),
4099 SH_PFC_PIN_GROUP(usb1),
4100 SH_PFC_PIN_GROUP(usb2),
4101 SH_PFC_PIN_GROUP(usb30),
4102 SH_PFC_PIN_GROUP(usb31),
4103 };
4104
4105 static const char * const audio_clk_groups[] = {
4106 "audio_clk_a_a",
4107 "audio_clk_a_b",
4108 "audio_clk_a_c",
4109 "audio_clk_b_a",
4110 "audio_clk_b_b",
4111 "audio_clk_c_a",
4112 "audio_clk_c_b",
4113 "audio_clkout_a",
4114 "audio_clkout_b",
4115 "audio_clkout_c",
4116 "audio_clkout_d",
4117 "audio_clkout1_a",
4118 "audio_clkout1_b",
4119 "audio_clkout2_a",
4120 "audio_clkout2_b",
4121 "audio_clkout3_a",
4122 "audio_clkout3_b",
4123 };
4124
4125 static const char * const avb_groups[] = {
4126 "avb_link",
4127 "avb_magic",
4128 "avb_phy_int",
4129 "avb_mdc",
4130 "avb_mii",
4131 "avb_avtp_pps",
4132 "avb_avtp_match_a",
4133 "avb_avtp_capture_a",
4134 "avb_avtp_match_b",
4135 "avb_avtp_capture_b",
4136 };
4137
4138 static const char * const can0_groups[] = {
4139 "can0_data_a",
4140 "can0_data_b",
4141 };
4142
4143 static const char * const can1_groups[] = {
4144 "can1_data",
4145 };
4146
4147 static const char * const can_clk_groups[] = {
4148 "can_clk",
4149 };
4150
4151 static const char * const canfd0_groups[] = {
4152 "canfd0_data_a",
4153 "canfd0_data_b",
4154 };
4155
4156 static const char * const canfd1_groups[] = {
4157 "canfd1_data",
4158 };
4159
4160 static const char * const drif0_groups[] = {
4161 "drif0_ctrl_a",
4162 "drif0_data0_a",
4163 "drif0_data1_a",
4164 "drif0_ctrl_b",
4165 "drif0_data0_b",
4166 "drif0_data1_b",
4167 "drif0_ctrl_c",
4168 "drif0_data0_c",
4169 "drif0_data1_c",
4170 };
4171
4172 static const char * const drif1_groups[] = {
4173 "drif1_ctrl_a",
4174 "drif1_data0_a",
4175 "drif1_data1_a",
4176 "drif1_ctrl_b",
4177 "drif1_data0_b",
4178 "drif1_data1_b",
4179 "drif1_ctrl_c",
4180 "drif1_data0_c",
4181 "drif1_data1_c",
4182 };
4183
4184 static const char * const drif2_groups[] = {
4185 "drif2_ctrl_a",
4186 "drif2_data0_a",
4187 "drif2_data1_a",
4188 "drif2_ctrl_b",
4189 "drif2_data0_b",
4190 "drif2_data1_b",
4191 };
4192
4193 static const char * const drif3_groups[] = {
4194 "drif3_ctrl_a",
4195 "drif3_data0_a",
4196 "drif3_data1_a",
4197 "drif3_ctrl_b",
4198 "drif3_data0_b",
4199 "drif3_data1_b",
4200 };
4201
4202 static const char * const du_groups[] = {
4203 "du_rgb666",
4204 "du_rgb888",
4205 "du_clk_out_0",
4206 "du_clk_out_1",
4207 "du_sync",
4208 "du_oddf",
4209 "du_cde",
4210 "du_disp",
4211 };
4212
4213 static const char * const hscif0_groups[] = {
4214 "hscif0_data",
4215 "hscif0_clk",
4216 "hscif0_ctrl",
4217 };
4218
4219 static const char * const hscif1_groups[] = {
4220 "hscif1_data_a",
4221 "hscif1_clk_a",
4222 "hscif1_ctrl_a",
4223 "hscif1_data_b",
4224 "hscif1_clk_b",
4225 "hscif1_ctrl_b",
4226 };
4227
4228 static const char * const hscif2_groups[] = {
4229 "hscif2_data_a",
4230 "hscif2_clk_a",
4231 "hscif2_ctrl_a",
4232 "hscif2_data_b",
4233 "hscif2_clk_b",
4234 "hscif2_ctrl_b",
4235 };
4236
4237 static const char * const hscif3_groups[] = {
4238 "hscif3_data_a",
4239 "hscif3_clk",
4240 "hscif3_ctrl",
4241 "hscif3_data_b",
4242 "hscif3_data_c",
4243 "hscif3_data_d",
4244 };
4245
4246 static const char * const hscif4_groups[] = {
4247 "hscif4_data_a",
4248 "hscif4_clk",
4249 "hscif4_ctrl",
4250 "hscif4_data_b",
4251 };
4252
4253 static const char * const i2c1_groups[] = {
4254 "i2c1_a",
4255 "i2c1_b",
4256 };
4257
4258 static const char * const i2c2_groups[] = {
4259 "i2c2_a",
4260 "i2c2_b",
4261 };
4262
4263 static const char * const i2c6_groups[] = {
4264 "i2c6_a",
4265 "i2c6_b",
4266 "i2c6_c",
4267 };
4268
4269 static const char * const intc_ex_groups[] = {
4270 "intc_ex_irq0",
4271 "intc_ex_irq1",
4272 "intc_ex_irq2",
4273 "intc_ex_irq3",
4274 "intc_ex_irq4",
4275 "intc_ex_irq5",
4276 };
4277
4278 static const char * const msiof0_groups[] = {
4279 "msiof0_clk",
4280 "msiof0_sync",
4281 "msiof0_ss1",
4282 "msiof0_ss2",
4283 "msiof0_txd",
4284 "msiof0_rxd",
4285 };
4286
4287 static const char * const msiof1_groups[] = {
4288 "msiof1_clk_a",
4289 "msiof1_sync_a",
4290 "msiof1_ss1_a",
4291 "msiof1_ss2_a",
4292 "msiof1_txd_a",
4293 "msiof1_rxd_a",
4294 "msiof1_clk_b",
4295 "msiof1_sync_b",
4296 "msiof1_ss1_b",
4297 "msiof1_ss2_b",
4298 "msiof1_txd_b",
4299 "msiof1_rxd_b",
4300 "msiof1_clk_c",
4301 "msiof1_sync_c",
4302 "msiof1_ss1_c",
4303 "msiof1_ss2_c",
4304 "msiof1_txd_c",
4305 "msiof1_rxd_c",
4306 "msiof1_clk_d",
4307 "msiof1_sync_d",
4308 "msiof1_ss1_d",
4309 "msiof1_ss2_d",
4310 "msiof1_txd_d",
4311 "msiof1_rxd_d",
4312 "msiof1_clk_e",
4313 "msiof1_sync_e",
4314 "msiof1_ss1_e",
4315 "msiof1_ss2_e",
4316 "msiof1_txd_e",
4317 "msiof1_rxd_e",
4318 "msiof1_clk_f",
4319 "msiof1_sync_f",
4320 "msiof1_ss1_f",
4321 "msiof1_ss2_f",
4322 "msiof1_txd_f",
4323 "msiof1_rxd_f",
4324 "msiof1_clk_g",
4325 "msiof1_sync_g",
4326 "msiof1_ss1_g",
4327 "msiof1_ss2_g",
4328 "msiof1_txd_g",
4329 "msiof1_rxd_g",
4330 };
4331
4332 static const char * const msiof2_groups[] = {
4333 "msiof2_clk_a",
4334 "msiof2_sync_a",
4335 "msiof2_ss1_a",
4336 "msiof2_ss2_a",
4337 "msiof2_txd_a",
4338 "msiof2_rxd_a",
4339 "msiof2_clk_b",
4340 "msiof2_sync_b",
4341 "msiof2_ss1_b",
4342 "msiof2_ss2_b",
4343 "msiof2_txd_b",
4344 "msiof2_rxd_b",
4345 "msiof2_clk_c",
4346 "msiof2_sync_c",
4347 "msiof2_ss1_c",
4348 "msiof2_ss2_c",
4349 "msiof2_txd_c",
4350 "msiof2_rxd_c",
4351 "msiof2_clk_d",
4352 "msiof2_sync_d",
4353 "msiof2_ss1_d",
4354 "msiof2_ss2_d",
4355 "msiof2_txd_d",
4356 "msiof2_rxd_d",
4357 };
4358
4359 static const char * const msiof3_groups[] = {
4360 "msiof3_clk_a",
4361 "msiof3_sync_a",
4362 "msiof3_ss1_a",
4363 "msiof3_ss2_a",
4364 "msiof3_txd_a",
4365 "msiof3_rxd_a",
4366 "msiof3_clk_b",
4367 "msiof3_sync_b",
4368 "msiof3_ss1_b",
4369 "msiof3_ss2_b",
4370 "msiof3_txd_b",
4371 "msiof3_rxd_b",
4372 "msiof3_clk_c",
4373 "msiof3_sync_c",
4374 "msiof3_txd_c",
4375 "msiof3_rxd_c",
4376 "msiof3_clk_d",
4377 "msiof3_sync_d",
4378 "msiof3_ss1_d",
4379 "msiof3_txd_d",
4380 "msiof3_rxd_d",
4381 };
4382
4383 static const char * const pwm0_groups[] = {
4384 "pwm0",
4385 };
4386
4387 static const char * const pwm1_groups[] = {
4388 "pwm1_a",
4389 "pwm1_b",
4390 };
4391
4392 static const char * const pwm2_groups[] = {
4393 "pwm2_a",
4394 "pwm2_b",
4395 };
4396
4397 static const char * const pwm3_groups[] = {
4398 "pwm3_a",
4399 "pwm3_b",
4400 };
4401
4402 static const char * const pwm4_groups[] = {
4403 "pwm4_a",
4404 "pwm4_b",
4405 };
4406
4407 static const char * const pwm5_groups[] = {
4408 "pwm5_a",
4409 "pwm5_b",
4410 };
4411
4412 static const char * const pwm6_groups[] = {
4413 "pwm6_a",
4414 "pwm6_b",
4415 };
4416
4417 static const char * const qspi0_groups[] = {
4418 "qspi0_ctrl",
4419 "qspi0_data2",
4420 "qspi0_data4",
4421 };
4422
4423 static const char * const qspi1_groups[] = {
4424 "qspi1_ctrl",
4425 "qspi1_data2",
4426 "qspi1_data4",
4427 };
4428
4429 static const char * const sata0_groups[] = {
4430 "sata0_devslp_a",
4431 "sata0_devslp_b",
4432 };
4433
4434 static const char * const scif0_groups[] = {
4435 "scif0_data",
4436 "scif0_clk",
4437 "scif0_ctrl",
4438 };
4439
4440 static const char * const scif1_groups[] = {
4441 "scif1_data_a",
4442 "scif1_clk",
4443 "scif1_ctrl",
4444 "scif1_data_b",
4445 };
4446
4447 static const char * const scif2_groups[] = {
4448 "scif2_data_a",
4449 "scif2_clk",
4450 "scif2_data_b",
4451 };
4452
4453 static const char * const scif3_groups[] = {
4454 "scif3_data_a",
4455 "scif3_clk",
4456 "scif3_ctrl",
4457 "scif3_data_b",
4458 };
4459
4460 static const char * const scif4_groups[] = {
4461 "scif4_data_a",
4462 "scif4_clk_a",
4463 "scif4_ctrl_a",
4464 "scif4_data_b",
4465 "scif4_clk_b",
4466 "scif4_ctrl_b",
4467 "scif4_data_c",
4468 "scif4_clk_c",
4469 "scif4_ctrl_c",
4470 };
4471
4472 static const char * const scif5_groups[] = {
4473 "scif5_data",
4474 "scif5_clk",
4475 };
4476
4477 static const char * const scif_clk_groups[] = {
4478 "scif_clk_a",
4479 "scif_clk_b",
4480 };
4481
4482 static const char * const sdhi0_groups[] = {
4483 "sdhi0_data1",
4484 "sdhi0_data4",
4485 "sdhi0_ctrl",
4486 "sdhi0_cd",
4487 "sdhi0_wp",
4488 };
4489
4490 static const char * const sdhi1_groups[] = {
4491 "sdhi1_data1",
4492 "sdhi1_data4",
4493 "sdhi1_ctrl",
4494 "sdhi1_cd",
4495 "sdhi1_wp",
4496 };
4497
4498 static const char * const sdhi2_groups[] = {
4499 "sdhi2_data1",
4500 "sdhi2_data4",
4501 "sdhi2_data8",
4502 "sdhi2_ctrl",
4503 "sdhi2_cd_a",
4504 "sdhi2_wp_a",
4505 "sdhi2_cd_b",
4506 "sdhi2_wp_b",
4507 "sdhi2_ds",
4508 };
4509
4510 static const char * const sdhi3_groups[] = {
4511 "sdhi3_data1",
4512 "sdhi3_data4",
4513 "sdhi3_data8",
4514 "sdhi3_ctrl",
4515 "sdhi3_cd",
4516 "sdhi3_wp",
4517 "sdhi3_ds",
4518 };
4519
4520 static const char * const ssi_groups[] = {
4521 "ssi0_data",
4522 "ssi01239_ctrl",
4523 "ssi1_data_a",
4524 "ssi1_data_b",
4525 "ssi1_ctrl_a",
4526 "ssi1_ctrl_b",
4527 "ssi2_data_a",
4528 "ssi2_data_b",
4529 "ssi2_ctrl_a",
4530 "ssi2_ctrl_b",
4531 "ssi3_data",
4532 "ssi349_ctrl",
4533 "ssi4_data",
4534 "ssi4_ctrl",
4535 "ssi5_data",
4536 "ssi5_ctrl",
4537 "ssi6_data",
4538 "ssi6_ctrl",
4539 "ssi7_data",
4540 "ssi78_ctrl",
4541 "ssi8_data",
4542 "ssi9_data_a",
4543 "ssi9_data_b",
4544 "ssi9_ctrl_a",
4545 "ssi9_ctrl_b",
4546 };
4547
4548 static const char * const usb0_groups[] = {
4549 "usb0",
4550 };
4551
4552 static const char * const usb1_groups[] = {
4553 "usb1",
4554 };
4555
4556 static const char * const usb2_groups[] = {
4557 "usb2",
4558 };
4559
4560 static const char * const usb30_groups[] = {
4561 "usb30",
4562 };
4563
4564 static const char * const usb31_groups[] = {
4565 "usb31",
4566 };
4567
4568 static const struct sh_pfc_function pinmux_functions[] = {
4569 SH_PFC_FUNCTION(audio_clk),
4570 SH_PFC_FUNCTION(avb),
4571 SH_PFC_FUNCTION(can0),
4572 SH_PFC_FUNCTION(can1),
4573 SH_PFC_FUNCTION(can_clk),
4574 SH_PFC_FUNCTION(canfd0),
4575 SH_PFC_FUNCTION(canfd1),
4576 SH_PFC_FUNCTION(drif0),
4577 SH_PFC_FUNCTION(drif1),
4578 SH_PFC_FUNCTION(drif2),
4579 SH_PFC_FUNCTION(drif3),
4580 SH_PFC_FUNCTION(du),
4581 SH_PFC_FUNCTION(hscif0),
4582 SH_PFC_FUNCTION(hscif1),
4583 SH_PFC_FUNCTION(hscif2),
4584 SH_PFC_FUNCTION(hscif3),
4585 SH_PFC_FUNCTION(hscif4),
4586 SH_PFC_FUNCTION(i2c1),
4587 SH_PFC_FUNCTION(i2c2),
4588 SH_PFC_FUNCTION(i2c6),
4589 SH_PFC_FUNCTION(intc_ex),
4590 SH_PFC_FUNCTION(msiof0),
4591 SH_PFC_FUNCTION(msiof1),
4592 SH_PFC_FUNCTION(msiof2),
4593 SH_PFC_FUNCTION(msiof3),
4594 SH_PFC_FUNCTION(pwm0),
4595 SH_PFC_FUNCTION(pwm1),
4596 SH_PFC_FUNCTION(pwm2),
4597 SH_PFC_FUNCTION(pwm3),
4598 SH_PFC_FUNCTION(pwm4),
4599 SH_PFC_FUNCTION(pwm5),
4600 SH_PFC_FUNCTION(pwm6),
4601 SH_PFC_FUNCTION(qspi0),
4602 SH_PFC_FUNCTION(qspi1),
4603 SH_PFC_FUNCTION(sata0),
4604 SH_PFC_FUNCTION(scif0),
4605 SH_PFC_FUNCTION(scif1),
4606 SH_PFC_FUNCTION(scif2),
4607 SH_PFC_FUNCTION(scif3),
4608 SH_PFC_FUNCTION(scif4),
4609 SH_PFC_FUNCTION(scif5),
4610 SH_PFC_FUNCTION(scif_clk),
4611 SH_PFC_FUNCTION(sdhi0),
4612 SH_PFC_FUNCTION(sdhi1),
4613 SH_PFC_FUNCTION(sdhi2),
4614 SH_PFC_FUNCTION(sdhi3),
4615 SH_PFC_FUNCTION(ssi),
4616 SH_PFC_FUNCTION(usb0),
4617 SH_PFC_FUNCTION(usb1),
4618 SH_PFC_FUNCTION(usb2),
4619 SH_PFC_FUNCTION(usb30),
4620 SH_PFC_FUNCTION(usb31),
4621 };
4622
4623 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4624 #define F_(x, y) FN_##y
4625 #define FM(x) FN_##x
4626 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4627 0, 0,
4628 0, 0,
4629 0, 0,
4630 0, 0,
4631 0, 0,
4632 0, 0,
4633 0, 0,
4634 0, 0,
4635 0, 0,
4636 0, 0,
4637 0, 0,
4638 0, 0,
4639 0, 0,
4640 0, 0,
4641 0, 0,
4642 0, 0,
4643 GP_0_15_FN, GPSR0_15,
4644 GP_0_14_FN, GPSR0_14,
4645 GP_0_13_FN, GPSR0_13,
4646 GP_0_12_FN, GPSR0_12,
4647 GP_0_11_FN, GPSR0_11,
4648 GP_0_10_FN, GPSR0_10,
4649 GP_0_9_FN, GPSR0_9,
4650 GP_0_8_FN, GPSR0_8,
4651 GP_0_7_FN, GPSR0_7,
4652 GP_0_6_FN, GPSR0_6,
4653 GP_0_5_FN, GPSR0_5,
4654 GP_0_4_FN, GPSR0_4,
4655 GP_0_3_FN, GPSR0_3,
4656 GP_0_2_FN, GPSR0_2,
4657 GP_0_1_FN, GPSR0_1,
4658 GP_0_0_FN, GPSR0_0, }
4659 },
4660 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4661 0, 0,
4662 0, 0,
4663 0, 0,
4664 0, 0,
4665 GP_1_27_FN, GPSR1_27,
4666 GP_1_26_FN, GPSR1_26,
4667 GP_1_25_FN, GPSR1_25,
4668 GP_1_24_FN, GPSR1_24,
4669 GP_1_23_FN, GPSR1_23,
4670 GP_1_22_FN, GPSR1_22,
4671 GP_1_21_FN, GPSR1_21,
4672 GP_1_20_FN, GPSR1_20,
4673 GP_1_19_FN, GPSR1_19,
4674 GP_1_18_FN, GPSR1_18,
4675 GP_1_17_FN, GPSR1_17,
4676 GP_1_16_FN, GPSR1_16,
4677 GP_1_15_FN, GPSR1_15,
4678 GP_1_14_FN, GPSR1_14,
4679 GP_1_13_FN, GPSR1_13,
4680 GP_1_12_FN, GPSR1_12,
4681 GP_1_11_FN, GPSR1_11,
4682 GP_1_10_FN, GPSR1_10,
4683 GP_1_9_FN, GPSR1_9,
4684 GP_1_8_FN, GPSR1_8,
4685 GP_1_7_FN, GPSR1_7,
4686 GP_1_6_FN, GPSR1_6,
4687 GP_1_5_FN, GPSR1_5,
4688 GP_1_4_FN, GPSR1_4,
4689 GP_1_3_FN, GPSR1_3,
4690 GP_1_2_FN, GPSR1_2,
4691 GP_1_1_FN, GPSR1_1,
4692 GP_1_0_FN, GPSR1_0, }
4693 },
4694 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4695 0, 0,
4696 0, 0,
4697 0, 0,
4698 0, 0,
4699 0, 0,
4700 0, 0,
4701 0, 0,
4702 0, 0,
4703 0, 0,
4704 0, 0,
4705 0, 0,
4706 0, 0,
4707 0, 0,
4708 0, 0,
4709 0, 0,
4710 0, 0,
4711 0, 0,
4712 GP_2_14_FN, GPSR2_14,
4713 GP_2_13_FN, GPSR2_13,
4714 GP_2_12_FN, GPSR2_12,
4715 GP_2_11_FN, GPSR2_11,
4716 GP_2_10_FN, GPSR2_10,
4717 GP_2_9_FN, GPSR2_9,
4718 GP_2_8_FN, GPSR2_8,
4719 GP_2_7_FN, GPSR2_7,
4720 GP_2_6_FN, GPSR2_6,
4721 GP_2_5_FN, GPSR2_5,
4722 GP_2_4_FN, GPSR2_4,
4723 GP_2_3_FN, GPSR2_3,
4724 GP_2_2_FN, GPSR2_2,
4725 GP_2_1_FN, GPSR2_1,
4726 GP_2_0_FN, GPSR2_0, }
4727 },
4728 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4729 0, 0,
4730 0, 0,
4731 0, 0,
4732 0, 0,
4733 0, 0,
4734 0, 0,
4735 0, 0,
4736 0, 0,
4737 0, 0,
4738 0, 0,
4739 0, 0,
4740 0, 0,
4741 0, 0,
4742 0, 0,
4743 0, 0,
4744 0, 0,
4745 GP_3_15_FN, GPSR3_15,
4746 GP_3_14_FN, GPSR3_14,
4747 GP_3_13_FN, GPSR3_13,
4748 GP_3_12_FN, GPSR3_12,
4749 GP_3_11_FN, GPSR3_11,
4750 GP_3_10_FN, GPSR3_10,
4751 GP_3_9_FN, GPSR3_9,
4752 GP_3_8_FN, GPSR3_8,
4753 GP_3_7_FN, GPSR3_7,
4754 GP_3_6_FN, GPSR3_6,
4755 GP_3_5_FN, GPSR3_5,
4756 GP_3_4_FN, GPSR3_4,
4757 GP_3_3_FN, GPSR3_3,
4758 GP_3_2_FN, GPSR3_2,
4759 GP_3_1_FN, GPSR3_1,
4760 GP_3_0_FN, GPSR3_0, }
4761 },
4762 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4763 0, 0,
4764 0, 0,
4765 0, 0,
4766 0, 0,
4767 0, 0,
4768 0, 0,
4769 0, 0,
4770 0, 0,
4771 0, 0,
4772 0, 0,
4773 0, 0,
4774 0, 0,
4775 0, 0,
4776 0, 0,
4777 GP_4_17_FN, GPSR4_17,
4778 GP_4_16_FN, GPSR4_16,
4779 GP_4_15_FN, GPSR4_15,
4780 GP_4_14_FN, GPSR4_14,
4781 GP_4_13_FN, GPSR4_13,
4782 GP_4_12_FN, GPSR4_12,
4783 GP_4_11_FN, GPSR4_11,
4784 GP_4_10_FN, GPSR4_10,
4785 GP_4_9_FN, GPSR4_9,
4786 GP_4_8_FN, GPSR4_8,
4787 GP_4_7_FN, GPSR4_7,
4788 GP_4_6_FN, GPSR4_6,
4789 GP_4_5_FN, GPSR4_5,
4790 GP_4_4_FN, GPSR4_4,
4791 GP_4_3_FN, GPSR4_3,
4792 GP_4_2_FN, GPSR4_2,
4793 GP_4_1_FN, GPSR4_1,
4794 GP_4_0_FN, GPSR4_0, }
4795 },
4796 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4797 0, 0,
4798 0, 0,
4799 0, 0,
4800 0, 0,
4801 0, 0,
4802 0, 0,
4803 GP_5_25_FN, GPSR5_25,
4804 GP_5_24_FN, GPSR5_24,
4805 GP_5_23_FN, GPSR5_23,
4806 GP_5_22_FN, GPSR5_22,
4807 GP_5_21_FN, GPSR5_21,
4808 GP_5_20_FN, GPSR5_20,
4809 GP_5_19_FN, GPSR5_19,
4810 GP_5_18_FN, GPSR5_18,
4811 GP_5_17_FN, GPSR5_17,
4812 GP_5_16_FN, GPSR5_16,
4813 GP_5_15_FN, GPSR5_15,
4814 GP_5_14_FN, GPSR5_14,
4815 GP_5_13_FN, GPSR5_13,
4816 GP_5_12_FN, GPSR5_12,
4817 GP_5_11_FN, GPSR5_11,
4818 GP_5_10_FN, GPSR5_10,
4819 GP_5_9_FN, GPSR5_9,
4820 GP_5_8_FN, GPSR5_8,
4821 GP_5_7_FN, GPSR5_7,
4822 GP_5_6_FN, GPSR5_6,
4823 GP_5_5_FN, GPSR5_5,
4824 GP_5_4_FN, GPSR5_4,
4825 GP_5_3_FN, GPSR5_3,
4826 GP_5_2_FN, GPSR5_2,
4827 GP_5_1_FN, GPSR5_1,
4828 GP_5_0_FN, GPSR5_0, }
4829 },
4830 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4831 GP_6_31_FN, GPSR6_31,
4832 GP_6_30_FN, GPSR6_30,
4833 GP_6_29_FN, GPSR6_29,
4834 GP_6_28_FN, GPSR6_28,
4835 GP_6_27_FN, GPSR6_27,
4836 GP_6_26_FN, GPSR6_26,
4837 GP_6_25_FN, GPSR6_25,
4838 GP_6_24_FN, GPSR6_24,
4839 GP_6_23_FN, GPSR6_23,
4840 GP_6_22_FN, GPSR6_22,
4841 GP_6_21_FN, GPSR6_21,
4842 GP_6_20_FN, GPSR6_20,
4843 GP_6_19_FN, GPSR6_19,
4844 GP_6_18_FN, GPSR6_18,
4845 GP_6_17_FN, GPSR6_17,
4846 GP_6_16_FN, GPSR6_16,
4847 GP_6_15_FN, GPSR6_15,
4848 GP_6_14_FN, GPSR6_14,
4849 GP_6_13_FN, GPSR6_13,
4850 GP_6_12_FN, GPSR6_12,
4851 GP_6_11_FN, GPSR6_11,
4852 GP_6_10_FN, GPSR6_10,
4853 GP_6_9_FN, GPSR6_9,
4854 GP_6_8_FN, GPSR6_8,
4855 GP_6_7_FN, GPSR6_7,
4856 GP_6_6_FN, GPSR6_6,
4857 GP_6_5_FN, GPSR6_5,
4858 GP_6_4_FN, GPSR6_4,
4859 GP_6_3_FN, GPSR6_3,
4860 GP_6_2_FN, GPSR6_2,
4861 GP_6_1_FN, GPSR6_1,
4862 GP_6_0_FN, GPSR6_0, }
4863 },
4864 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4865 0, 0,
4866 0, 0,
4867 0, 0,
4868 0, 0,
4869 0, 0,
4870 0, 0,
4871 0, 0,
4872 0, 0,
4873 0, 0,
4874 0, 0,
4875 0, 0,
4876 0, 0,
4877 0, 0,
4878 0, 0,
4879 0, 0,
4880 0, 0,
4881 0, 0,
4882 0, 0,
4883 0, 0,
4884 0, 0,
4885 0, 0,
4886 0, 0,
4887 0, 0,
4888 0, 0,
4889 0, 0,
4890 0, 0,
4891 0, 0,
4892 0, 0,
4893 GP_7_3_FN, GPSR7_3,
4894 GP_7_2_FN, GPSR7_2,
4895 GP_7_1_FN, GPSR7_1,
4896 GP_7_0_FN, GPSR7_0, }
4897 },
4898 #undef F_
4899 #undef FM
4900
4901 #define F_(x, y) x,
4902 #define FM(x) FN_##x,
4903 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4904 IP0_31_28
4905 IP0_27_24
4906 IP0_23_20
4907 IP0_19_16
4908 IP0_15_12
4909 IP0_11_8
4910 IP0_7_4
4911 IP0_3_0 }
4912 },
4913 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4914 IP1_31_28
4915 IP1_27_24
4916 IP1_23_20
4917 IP1_19_16
4918 IP1_15_12
4919 IP1_11_8
4920 IP1_7_4
4921 IP1_3_0 }
4922 },
4923 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4924 IP2_31_28
4925 IP2_27_24
4926 IP2_23_20
4927 IP2_19_16
4928 IP2_15_12
4929 IP2_11_8
4930 IP2_7_4
4931 IP2_3_0 }
4932 },
4933 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4934 IP3_31_28
4935 IP3_27_24
4936 IP3_23_20
4937 IP3_19_16
4938 IP3_15_12
4939 IP3_11_8
4940 IP3_7_4
4941 IP3_3_0 }
4942 },
4943 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4944 IP4_31_28
4945 IP4_27_24
4946 IP4_23_20
4947 IP4_19_16
4948 IP4_15_12
4949 IP4_11_8
4950 IP4_7_4
4951 IP4_3_0 }
4952 },
4953 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4954 IP5_31_28
4955 IP5_27_24
4956 IP5_23_20
4957 IP5_19_16
4958 IP5_15_12
4959 IP5_11_8
4960 IP5_7_4
4961 IP5_3_0 }
4962 },
4963 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4964 IP6_31_28
4965 IP6_27_24
4966 IP6_23_20
4967 IP6_19_16
4968 IP6_15_12
4969 IP6_11_8
4970 IP6_7_4
4971 IP6_3_0 }
4972 },
4973 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4974 IP7_31_28
4975 IP7_27_24
4976 IP7_23_20
4977 IP7_19_16
4978 IP7_15_12
4979 IP7_11_8
4980 IP7_7_4
4981 IP7_3_0 }
4982 },
4983 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4984 IP8_31_28
4985 IP8_27_24
4986 IP8_23_20
4987 IP8_19_16
4988 IP8_15_12
4989 IP8_11_8
4990 IP8_7_4
4991 IP8_3_0 }
4992 },
4993 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4994 IP9_31_28
4995 IP9_27_24
4996 IP9_23_20
4997 IP9_19_16
4998 IP9_15_12
4999 IP9_11_8
5000 IP9_7_4
5001 IP9_3_0 }
5002 },
5003 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5004 IP10_31_28
5005 IP10_27_24
5006 IP10_23_20
5007 IP10_19_16
5008 IP10_15_12
5009 IP10_11_8
5010 IP10_7_4
5011 IP10_3_0 }
5012 },
5013 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5014 IP11_31_28
5015 IP11_27_24
5016 IP11_23_20
5017 IP11_19_16
5018 IP11_15_12
5019 IP11_11_8
5020 IP11_7_4
5021 IP11_3_0 }
5022 },
5023 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5024 IP12_31_28
5025 IP12_27_24
5026 IP12_23_20
5027 IP12_19_16
5028 IP12_15_12
5029 IP12_11_8
5030 IP12_7_4
5031 IP12_3_0 }
5032 },
5033 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5034 IP13_31_28
5035 IP13_27_24
5036 IP13_23_20
5037 IP13_19_16
5038 IP13_15_12
5039 IP13_11_8
5040 IP13_7_4
5041 IP13_3_0 }
5042 },
5043 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5044 IP14_31_28
5045 IP14_27_24
5046 IP14_23_20
5047 IP14_19_16
5048 IP14_15_12
5049 IP14_11_8
5050 IP14_7_4
5051 IP14_3_0 }
5052 },
5053 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5054 IP15_31_28
5055 IP15_27_24
5056 IP15_23_20
5057 IP15_19_16
5058 IP15_15_12
5059 IP15_11_8
5060 IP15_7_4
5061 IP15_3_0 }
5062 },
5063 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5064 IP16_31_28
5065 IP16_27_24
5066 IP16_23_20
5067 IP16_19_16
5068 IP16_15_12
5069 IP16_11_8
5070 IP16_7_4
5071 IP16_3_0 }
5072 },
5073 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5074 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5075 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5076 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5077 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5078 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5079 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5080 IP17_7_4
5081 IP17_3_0 }
5082 },
5083 #undef F_
5084 #undef FM
5085
5086 #define F_(x, y) x,
5087 #define FM(x) FN_##x,
5088 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5089 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
5090 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
5091 0, 0, /* RESERVED 31 */
5092 MOD_SEL0_30_29
5093 MOD_SEL0_28_27
5094 MOD_SEL0_26_25_24
5095 MOD_SEL0_23
5096 MOD_SEL0_22
5097 MOD_SEL0_21_20
5098 MOD_SEL0_19
5099 MOD_SEL0_18
5100 MOD_SEL0_17
5101 MOD_SEL0_16_15
5102 MOD_SEL0_14
5103 MOD_SEL0_13
5104 MOD_SEL0_12
5105 MOD_SEL0_11
5106 MOD_SEL0_10
5107 MOD_SEL0_9
5108 MOD_SEL0_8
5109 MOD_SEL0_7_6
5110 MOD_SEL0_5_4
5111 MOD_SEL0_3
5112 MOD_SEL0_2_1
5113 0, 0, /* RESERVED 0 */ }
5114 },
5115 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5116 2, 3, 1, 2, 3, 1, 1, 2, 1,
5117 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5118 MOD_SEL1_31_30
5119 MOD_SEL1_29_28_27
5120 MOD_SEL1_26
5121 MOD_SEL1_25_24
5122 MOD_SEL1_23_22_21
5123 MOD_SEL1_20
5124 MOD_SEL1_19
5125 MOD_SEL1_18_17
5126 MOD_SEL1_16
5127 MOD_SEL1_15_14
5128 MOD_SEL1_13
5129 MOD_SEL1_12
5130 MOD_SEL1_11
5131 MOD_SEL1_10
5132 MOD_SEL1_9
5133 0, 0, 0, 0, /* RESERVED 8, 7 */
5134 MOD_SEL1_6
5135 MOD_SEL1_5
5136 MOD_SEL1_4
5137 MOD_SEL1_3
5138 MOD_SEL1_2
5139 MOD_SEL1_1
5140 MOD_SEL1_0 }
5141 },
5142 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5143 1, 1, 1, 1, 4, 4, 4,
5144 4, 4, 4, 1, 2, 1) {
5145 MOD_SEL2_31
5146 MOD_SEL2_30
5147 MOD_SEL2_29
5148 /* RESERVED 28 */
5149 0, 0,
5150 /* RESERVED 27, 26, 25, 24 */
5151 0, 0, 0, 0, 0, 0, 0, 0,
5152 0, 0, 0, 0, 0, 0, 0, 0,
5153 /* RESERVED 23, 22, 21, 20 */
5154 0, 0, 0, 0, 0, 0, 0, 0,
5155 0, 0, 0, 0, 0, 0, 0, 0,
5156 /* RESERVED 19, 18, 17, 16 */
5157 0, 0, 0, 0, 0, 0, 0, 0,
5158 0, 0, 0, 0, 0, 0, 0, 0,
5159 /* RESERVED 15, 14, 13, 12 */
5160 0, 0, 0, 0, 0, 0, 0, 0,
5161 0, 0, 0, 0, 0, 0, 0, 0,
5162 /* RESERVED 11, 10, 9, 8 */
5163 0, 0, 0, 0, 0, 0, 0, 0,
5164 0, 0, 0, 0, 0, 0, 0, 0,
5165 /* RESERVED 7, 6, 5, 4 */
5166 0, 0, 0, 0, 0, 0, 0, 0,
5167 0, 0, 0, 0, 0, 0, 0, 0,
5168 /* RESERVED 3 */
5169 0, 0,
5170 /* RESERVED 2, 1 */
5171 0, 0, 0, 0,
5172 MOD_SEL2_0 }
5173 },
5174 { },
5175 };
5176
5177 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5178 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5179 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5180 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5181 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5182 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5183 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5184 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5185 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5186 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5187 } },
5188 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5189 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5190 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5191 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5192 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5193 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5194 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5195 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5196 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5197 } },
5198 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5199 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5200 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5201 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5202 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5203 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5204 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5205 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5206 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5207 } },
5208 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5209 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5210 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5211 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5212 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5213 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5214 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5215 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5216 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5217 } },
5218 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5219 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5220 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5221 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5222 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5223 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5224 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5225 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5226 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5227 } },
5228 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5229 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5230 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5231 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5232 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5233 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5234 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5235 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5236 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5237 } },
5238 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5239 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5240 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5241 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5242 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5243 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5244 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5245 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5246 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5247 } },
5248 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5249 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5250 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5251 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5252 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5253 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5254 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5255 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5256 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5257 } },
5258 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5259 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
5260 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5261 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5262 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5263 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5264 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5265 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5266 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5267 } },
5268 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5269 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5270 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5271 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5272 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5273 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5274 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5275 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5276 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5277 } },
5278 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5279 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5280 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5281 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5282 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5283 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5284 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5285 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5286 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5287 } },
5288 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5289 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5290 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5291 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5292 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5293 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5294 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5295 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5296 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5297 } },
5298 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5299 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5300 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5301 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5302 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5303 } },
5304 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5305 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5306 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5307 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5308 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5309 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5310 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5311 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5312 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5313 } },
5314 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5315 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5316 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5317 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5318 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5319 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5320 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5321 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5322 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5323 } },
5324 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5325 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5326 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5327 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5328 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5329 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5330 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5331 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5332 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5333 } },
5334 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5335 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5336 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5337 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5338 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5339 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5340 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5341 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5342 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5343 } },
5344 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5345 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5346 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5347 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5348 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5349 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5350 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5351 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5352 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5353 } },
5354 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5355 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5356 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5357 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5358 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5359 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5360 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5361 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5362 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5363 } },
5364 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5365 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5366 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5367 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5368 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5369 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5370 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5371 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5372 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5373 } },
5374 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5375 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5376 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5377 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5378 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5379 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5380 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5381 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5382 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5383 } },
5384 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5385 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5386 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5387 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5388 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5389 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5390 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5391 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5392 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5393 } },
5394 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5395 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5396 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5397 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5398 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5399 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5400 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5401 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5402 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5403 } },
5404 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5405 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5406 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5407 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5408 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5409 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5410 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5411 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5412 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5413 } },
5414 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5415 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5416 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5417 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5418 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5419 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5420 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
5421 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
5422 } },
5423 { },
5424 };
5425
5426 enum ioctrl_regs {
5427 POCCTRL,
5428 };
5429
5430 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5431 [POCCTRL] = { 0xe6060380, },
5432 { /* sentinel */ },
5433 };
5434
5435 static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5436 u32 *pocctrl)
5437 {
5438 int bit = -EINVAL;
5439
5440 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5441
5442 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5443 bit = pin & 0x1f;
5444
5445 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5446 bit = (pin & 0x1f) + 12;
5447
5448 return bit;
5449 }
5450
5451 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5452 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5453 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5454 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5455 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5456 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5457 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5458 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5459 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5460 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5461 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5462 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5463 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5464 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5465 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5466 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5467 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5468 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5469 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5470 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5471 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5472 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5473 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5474 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5475 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5476 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5477 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5478 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5479 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5480 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5481 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5482 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5483 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5484 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5485 } },
5486 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5487 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5488 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5489 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5490 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5491 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5492 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5493 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5494 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5495 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5496 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5497 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5498 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5499 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5500 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5501 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5502 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5503 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5504 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5505 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5506 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5507 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5508 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5509 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5510 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5511 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5512 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5513 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5514 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5515 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5516 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5517 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5518 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5519 } },
5520 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5521 [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
5522 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5523 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
5524 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5525 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5526 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5527 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5528 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5529 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5530 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5531 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5532 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5533 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5534 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5535 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5536 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5537 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5538 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5539 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5540 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5541 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5542 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5543 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5544 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5545 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5546 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5547 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5548 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5549 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5550 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
5551 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5552 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5553 } },
5554 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5555 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
5556 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
5557 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
5558 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5559 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5560 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5561 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5562 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5563 [ 8] = PIN_NONE,
5564 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5565 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5566 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5567 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5568 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5569 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5570 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5571 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5572 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5573 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5574 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5575 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5576 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5577 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5578 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5579 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5580 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5581 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5582 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5583 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5584 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5585 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5586 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5587 } },
5588 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5589 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5590 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5591 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5592 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5593 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5594 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5595 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5596 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5597 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5598 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5599 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5600 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5601 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5602 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5603 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5604 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5605 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
5606 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5607 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5608 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5609 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
5610 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5611 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5612 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5613 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5614 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5615 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5616 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5617 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5618 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5619 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5620 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5621 } },
5622 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5623 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5624 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5625 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5626 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5627 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5628 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5629 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5630 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5631 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5632 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5633 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5634 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5635 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5636 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5637 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5638 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5639 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5640 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5641 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5642 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5643 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5644 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5645 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5646 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5647 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5648 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5649 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5650 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5651 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5652 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5653 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5654 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5655 } },
5656 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5657 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5658 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5659 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5660 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5661 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5662 [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
5663 [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
5664 [ 7] = PIN_NONE,
5665 [ 8] = PIN_NONE,
5666 [ 9] = PIN_NONE,
5667 [10] = PIN_NONE,
5668 [11] = PIN_NONE,
5669 [12] = PIN_NONE,
5670 [13] = PIN_NONE,
5671 [14] = PIN_NONE,
5672 [15] = PIN_NONE,
5673 [16] = PIN_NONE,
5674 [17] = PIN_NONE,
5675 [18] = PIN_NONE,
5676 [19] = PIN_NONE,
5677 [20] = PIN_NONE,
5678 [21] = PIN_NONE,
5679 [22] = PIN_NONE,
5680 [23] = PIN_NONE,
5681 [24] = PIN_NONE,
5682 [25] = PIN_NONE,
5683 [26] = PIN_NONE,
5684 [27] = PIN_NONE,
5685 [28] = PIN_NONE,
5686 [29] = PIN_NONE,
5687 [30] = PIN_NONE,
5688 [31] = PIN_NONE,
5689 } },
5690 { /* sentinel */ },
5691 };
5692
5693 static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
5694 unsigned int pin)
5695 {
5696 const struct pinmux_bias_reg *reg;
5697 unsigned int bit;
5698
5699 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5700 if (!reg)
5701 return PIN_CONFIG_BIAS_DISABLE;
5702
5703 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5704 return PIN_CONFIG_BIAS_DISABLE;
5705 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5706 return PIN_CONFIG_BIAS_PULL_UP;
5707 else
5708 return PIN_CONFIG_BIAS_PULL_DOWN;
5709 }
5710
5711 static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5712 unsigned int bias)
5713 {
5714 const struct pinmux_bias_reg *reg;
5715 u32 enable, updown;
5716 unsigned int bit;
5717
5718 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5719 if (!reg)
5720 return;
5721
5722 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5723 if (bias != PIN_CONFIG_BIAS_DISABLE)
5724 enable |= BIT(bit);
5725
5726 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5727 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5728 updown |= BIT(bit);
5729
5730 sh_pfc_write(pfc, reg->pud, updown);
5731 sh_pfc_write(pfc, reg->puen, enable);
5732 }
5733
5734 static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
5735 .pin_to_pocctrl = r8a7795es1_pin_to_pocctrl,
5736 .get_bias = r8a7795es1_pinmux_get_bias,
5737 .set_bias = r8a7795es1_pinmux_set_bias,
5738 };
5739
5740 const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
5741 .name = "r8a77950_pfc",
5742 .ops = &r8a7795es1_pinmux_ops,
5743 .unlock_reg = 0xe6060000, /* PMMR */
5744
5745 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5746
5747 .pins = pinmux_pins,
5748 .nr_pins = ARRAY_SIZE(pinmux_pins),
5749 .groups = pinmux_groups,
5750 .nr_groups = ARRAY_SIZE(pinmux_groups),
5751 .functions = pinmux_functions,
5752 .nr_functions = ARRAY_SIZE(pinmux_functions),
5753
5754 .cfg_regs = pinmux_config_regs,
5755 .drive_regs = pinmux_drive_regs,
5756 .bias_regs = pinmux_bias_regs,
5757 .ioctrl_regs = pinmux_ioctrl_regs,
5758
5759 .pinmux_data = pinmux_data,
5760 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5761 };
CRIS linux kernel tree