drivers/thermal/ti-soc-thermal/dra752-bandgap.h

   1 /*
   2  * DRA752 bandgap registers, bitfields and temperature definitions
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   5  * Contact:
   6  *   Eduardo Valentin <eduardo.valentin@ti.com>
   7  *   Tero Kristo <t-kristo@ti.com>
   8  *
   9  * This is an auto generated file.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * version 2 as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23  * 02110-1301 USA
  24  *
  25  */
  26 #ifndef __DRA752_BANDGAP_H
  27 #define __DRA752_BANDGAP_H
  28
  29 /**
  30  * *** DRA752 ***
  31  *
  32  * Below, in sequence, are the Register definitions,
  33  * the bitfields and the temperature definitions for DRA752.
  34  */
  35
  36 /**
  37  * DRA752 register definitions
  38  *
  39  * Registers are defined as offsets. The offsets are
  40  * relative to FUSE_OPP_BGAP_GPU on DRA752.
  41  * DRA752_BANDGAP_BASE          0x4a0021e0
  42  *
  43  * Register below are grouped by domain (not necessarily in offset order)
  44  */
  45
  46
  47 /* DRA752.common register offsets */
  48 #define DRA752_BANDGAP_CTRL_1_OFFSET            0x1a0
  49 #define DRA752_BANDGAP_STATUS_1_OFFSET          0x1c8
  50 #define DRA752_BANDGAP_CTRL_2_OFFSET            0x39c
  51 #define DRA752_BANDGAP_STATUS_2_OFFSET          0x3b8
  52
  53 /* DRA752.core register offsets */
  54 #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET            0x8
  55 #define DRA752_TEMP_SENSOR_CORE_OFFSET                  0x154
  56 #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET            0x1ac
  57 #define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET          0x1c4
  58 #define DRA752_DTEMP_CORE_0_OFFSET                      0x208
  59 #define DRA752_DTEMP_CORE_1_OFFSET                      0x20c
  60 #define DRA752_DTEMP_CORE_2_OFFSET                      0x210
  61 #define DRA752_DTEMP_CORE_3_OFFSET                      0x214
  62 #define DRA752_DTEMP_CORE_4_OFFSET                      0x218
  63
  64 /* DRA752.iva register offsets */
  65 #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET             0x388
  66 #define DRA752_TEMP_SENSOR_IVA_OFFSET                   0x398
  67 #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET             0x3a4
  68 #define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET           0x3b4
  69 #define DRA752_DTEMP_IVA_0_OFFSET                       0x3d0
  70 #define DRA752_DTEMP_IVA_1_OFFSET                       0x3d4
  71 #define DRA752_DTEMP_IVA_2_OFFSET                       0x3d8
  72 #define DRA752_DTEMP_IVA_3_OFFSET                       0x3dc
  73 #define DRA752_DTEMP_IVA_4_OFFSET                       0x3e0
  74
  75 /* DRA752.mpu register offsets */
  76 #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET             0x4
  77 #define DRA752_TEMP_SENSOR_MPU_OFFSET                   0x14c
  78 #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET             0x1a4
  79 #define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET           0x1bc
  80 #define DRA752_DTEMP_MPU_0_OFFSET                       0x1e0
  81 #define DRA752_DTEMP_MPU_1_OFFSET                       0x1e4
  82 #define DRA752_DTEMP_MPU_2_OFFSET                       0x1e8
  83 #define DRA752_DTEMP_MPU_3_OFFSET                       0x1ec
  84 #define DRA752_DTEMP_MPU_4_OFFSET                       0x1f0
  85
  86 /* DRA752.dspeve register offsets */
  87 #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET                  0x384
  88 #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET                        0x394
  89 #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET                  0x3a0
  90 #define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET                0x3b0
  91 #define DRA752_DTEMP_DSPEVE_0_OFFSET                            0x3bc
  92 #define DRA752_DTEMP_DSPEVE_1_OFFSET                            0x3c0
  93 #define DRA752_DTEMP_DSPEVE_2_OFFSET                            0x3c4
  94 #define DRA752_DTEMP_DSPEVE_3_OFFSET                            0x3c8
  95 #define DRA752_DTEMP_DSPEVE_4_OFFSET                            0x3cc
  96
  97 /* DRA752.gpu register offsets */
  98 #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET             0x0
  99 #define DRA752_TEMP_SENSOR_GPU_OFFSET                   0x150
 100 #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET             0x1a8
 101 #define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET           0x1c0
 102 #define DRA752_DTEMP_GPU_0_OFFSET                       0x1f4
 103 #define DRA752_DTEMP_GPU_1_OFFSET                       0x1f8
 104 #define DRA752_DTEMP_GPU_2_OFFSET                       0x1fc
 105 #define DRA752_DTEMP_GPU_3_OFFSET                       0x200
 106 #define DRA752_DTEMP_GPU_4_OFFSET                       0x204
 107
 108 /**
 109  * Register bitfields for DRA752
 110  *
 111  * All the macros bellow define the required bits for
 112  * controlling temperature on DRA752. Bit defines are
 113  * grouped by register.
 114  */
 115
 116 /* DRA752.BANDGAP_STATUS_1 */
 117 #define DRA752_BANDGAP_STATUS_1_ALERT_MASK              BIT(31)
 118 #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK           BIT(5)
 119 #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK          BIT(4)
 120 #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK            BIT(3)
 121 #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK           BIT(2)
 122 #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK            BIT(1)
 123 #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK           BIT(0)
 124
 125 /* DRA752.BANDGAP_CTRL_2 */
 126 #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK                   BIT(22)
 127 #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK                BIT(21)
 128 #define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK                    BIT(19)
 129 #define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK                 BIT(18)
 130 #define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK              BIT(16)
 131 #define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK           BIT(15)
 132 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK                 BIT(3)
 133 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK                BIT(2)
 134 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK              BIT(1)
 135 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK             BIT(0)
 136
 137 /* DRA752.BANDGAP_STATUS_2 */
 138 #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK                    BIT(3)
 139 #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK                   BIT(2)
 140 #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK                 BIT(1)
 141 #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK                BIT(0)
 142
 143 /* DRA752.BANDGAP_CTRL_1 */
 144 #define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK                    (0x3 << 30)
 145 #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK                (0x7 << 27)
 146 #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK                  BIT(23)
 147 #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK                   BIT(22)
 148 #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK                   BIT(21)
 149 #define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK                   BIT(20)
 150 #define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK                    BIT(19)
 151 #define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK                    BIT(18)
 152 #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK             BIT(17)
 153 #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK              BIT(16)
 154 #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK              BIT(15)
 155 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK                BIT(5)
 156 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK               BIT(4)
 157 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK                 BIT(3)
 158 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK                BIT(2)
 159 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK                 BIT(1)
 160 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK                BIT(0)
 161
 162 /* DRA752.TEMP_SENSOR */
 163 #define DRA752_TEMP_SENSOR_TMPSOFF_MASK         BIT(11)
 164 #define DRA752_TEMP_SENSOR_EOCZ_MASK            BIT(10)
 165 #define DRA752_TEMP_SENSOR_DTEMP_MASK           (0x3ff << 0)
 166
 167 /* DRA752.BANDGAP_THRESHOLD */
 168 #define DRA752_BANDGAP_THRESHOLD_HOT_MASK               (0x3ff << 16)
 169 #define DRA752_BANDGAP_THRESHOLD_COLD_MASK              (0x3ff << 0)
 170
 171
 172 /* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
 173 #define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK            (0xffffffff << 0)
 174
 175 /* DRA752.BANDGAP_CUMUL_DTEMP_IVA */
 176 #define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK             (0xffffffff << 0)
 177
 178 /* DRA752.BANDGAP_CUMUL_DTEMP_MPU */
 179 #define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK             (0xffffffff << 0)
 180
 181 /* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */
 182 #define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK          (0xffffffff << 0)
 183
 184 /* DRA752.BANDGAP_CUMUL_DTEMP_GPU */
 185 #define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK             (0xffffffff << 0)
 186
 187 /**
 188  * Temperature limits and thresholds for DRA752
 189  *
 190  * All the macros bellow are definitions for handling the
 191  * ADC conversions and representation of temperature limits
 192  * and thresholds for DRA752. Definitions are grouped
 193  * by temperature domain.
 194  */
 195
 196 /* DRA752.common temperature definitions */
 197 /* ADC conversion table limits */
 198 #define DRA752_ADC_START_VALUE          540
 199 #define DRA752_ADC_END_VALUE            945
 200
 201 /* DRA752.GPU temperature definitions */
 202 /* bandgap clock limits */
 203 #define DRA752_GPU_MAX_FREQ                             1500000
 204 #define DRA752_GPU_MIN_FREQ                             1000000
 205 /* sensor limits */
 206 #define DRA752_GPU_MIN_TEMP                             -40000
 207 #define DRA752_GPU_MAX_TEMP                             125000
 208 #define DRA752_GPU_HYST_VAL                             5000
 209 /* interrupts thresholds */
 210 #define DRA752_GPU_T_HOT                                800
 211 #define DRA752_GPU_T_COLD                               795
 212
 213 /* DRA752.MPU temperature definitions */
 214 /* bandgap clock limits */
 215 #define DRA752_MPU_MAX_FREQ                             1500000
 216 #define DRA752_MPU_MIN_FREQ                             1000000
 217 /* sensor limits */
 218 #define DRA752_MPU_MIN_TEMP                             -40000
 219 #define DRA752_MPU_MAX_TEMP                             125000
 220 #define DRA752_MPU_HYST_VAL                             5000
 221 /* interrupts thresholds */
 222 #define DRA752_MPU_T_HOT                                800
 223 #define DRA752_MPU_T_COLD                               795
 224
 225 /* DRA752.CORE temperature definitions */
 226 /* bandgap clock limits */
 227 #define DRA752_CORE_MAX_FREQ                            1500000
 228 #define DRA752_CORE_MIN_FREQ                            1000000
 229 /* sensor limits */
 230 #define DRA752_CORE_MIN_TEMP                            -40000
 231 #define DRA752_CORE_MAX_TEMP                            125000
 232 #define DRA752_CORE_HYST_VAL                            5000
 233 /* interrupts thresholds */
 234 #define DRA752_CORE_T_HOT                               800
 235 #define DRA752_CORE_T_COLD                              795
 236
 237 /* DRA752.DSPEVE temperature definitions */
 238 /* bandgap clock limits */
 239 #define DRA752_DSPEVE_MAX_FREQ                          1500000
 240 #define DRA752_DSPEVE_MIN_FREQ                          1000000
 241 /* sensor limits */
 242 #define DRA752_DSPEVE_MIN_TEMP                          -40000
 243 #define DRA752_DSPEVE_MAX_TEMP                          125000
 244 #define DRA752_DSPEVE_HYST_VAL                          5000
 245 /* interrupts thresholds */
 246 #define DRA752_DSPEVE_T_HOT                             800
 247 #define DRA752_DSPEVE_T_COLD                            795
 248
 249 /* DRA752.IVA temperature definitions */
 250 /* bandgap clock limits */
 251 #define DRA752_IVA_MAX_FREQ                             1500000
 252 #define DRA752_IVA_MIN_FREQ                             1000000
 253 /* sensor limits */
 254 #define DRA752_IVA_MIN_TEMP                             -40000
 255 #define DRA752_IVA_MAX_TEMP                             125000
 256 #define DRA752_IVA_HYST_VAL                             5000
 257 /* interrupts thresholds */
 258 #define DRA752_IVA_T_HOT                                800
 259 #define DRA752_IVA_T_COLD                               795
 260
 261 #endif /* __DRA752_BANDGAP_H */