| blob | a5d72fcd1603d9c50f9b3c157fabaf4a34653797 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
38 /*
39 * This file contains the core HCD code, and implements the Linux hc_driver
40 * API
41 */
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
49 #include <linux/io.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
61 /*
62 * =========================================================================
63 * Host Core Layer Functions
64 * =========================================================================
65 */
67 /**
68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
69 * used in both device and host modes
70 *
71 * @hsotg: Programming view of the DWC_otg controller
72 */
74 {
75 u32 intmsk;
77 /* Clear any pending OTG Interrupts */
80 /* Clear any pending interrupts */
83 /* Enable the interrupts in the GINTMSK */
92 GINTSTS_SESSREQINT;
95 }
97 /*
98 * Initializes the FSLSPClkSel field of the HCFG register depending on the
99 * PHY type
100 */
102 {
109 /* Full speed PHY */
112 /* High speed PHY running at full speed or high speed */
114 }
121 }
124 {
128 /*
129 * core_init() is now called on every switch so only call the
130 * following for the first time through
131 */
140 /* Reset after a PHY select */
147 }
148 }
154 /*
155 * STM32F4x9 uses the GGPIO register as general
156 * core configuration register.
157 */
160 }
161 }
162 }
164 /*
165 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
166 * do this on HNP Dev/Host mode switches (done in dev_init and
167 * host_init).
168 */
175 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
180 /* Program GI2CCTL.I2CEn */
188 }
191 }
194 {
204 /*
205 * HS PHY parameters. These parameters are preserved during soft reset
206 * so only program the first time. Do a soft reset immediately after
207 * setting phyif.
208 */
211 /* ULPI interface */
218 /* Set external VBUS indicator as needed. */
221 GUSBCFG_INDICATORPASSTHROUGH);
224 /* UTMI+ interface */
233 }
238 /* Reset after setting the PHY parameters */
244 }
245 }
248 }
251 {
252 u32 usbcfg;
258 /* If FS/LS mode with FS/LS PHY */
263 /* High speed PHY */
267 }
282 }
285 }
288 {
302 }
309 }
318 else
323 }
331 }
334 {
335 u32 usbcfg;
343 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
346 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
354 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
363 }
366 }
368 /**
369 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
370 *
371 * @hsotg: Programming view of DWC_otg controller
372 */
374 {
375 u32 intmsk;
379 /* Disable all interrupts */
383 /* Enable the common interrupts */
386 /* Enable host mode interrupts without disturbing common interrupts */
390 }
392 /**
393 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
394 *
395 * @hsotg: Programming view of DWC_otg controller
396 */
398 {
401 /* Disable host mode interrupts without disturbing common interrupts */
405 }
407 /*
408 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
409 * For system that have a total fifo depth that is smaller than the default
410 * RX + TX fifo size.
411 *
412 * @hsotg: Programming view of DWC_otg controller
413 */
415 {
425 /*
426 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
427 * allocation with support for high bandwidth endpoints. Synopsys
428 * defines MPS(Max Packet size) for a periodic EP=1024, and for
429 * non-periodic as 512.
430 */
432 /*
433 * For Buffer DMA mode/Scatter Gather DMA mode
434 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
435 * with n = number of host channel.
436 * 2 * ((1024/4) + 2) = 516
437 */
440 /*
441 * min non-periodic tx fifo depth
442 * 2 * (largest non-periodic USB packet used / 4)
443 * 2 * (512/4) = 256
444 */
447 /*
448 * min periodic tx fifo depth
449 * (largest packet size*MC)/4
450 * (1024 * 3)/4 = 768
451 */
457 }
459 /*
460 * If the summation of RX, NPTX and PTX fifo sizes is still
461 * bigger than the total_fifo_size, then we have a problem.
462 *
463 * We won't be able to allocate as many endpoints. Right now,
464 * we're just printing an error message, but ideally this FIFO
465 * allocation algorithm would be improved in the future.
466 *
467 * FIXME improve this FIFO allocation algorithm.
468 */
471 }
474 {
483 /* Rx FIFO */
493 /* Non-periodic Tx FIFO */
504 /* Periodic Tx FIFO */
518 /*
519 * This feature was implemented in 2.91a version
520 * Global DFIFOCFG calculation for Host mode -
521 * include RxFIFO, NPTXFIFO and HPTXFIFO
522 */
528 GDFIFOCFG_EPINFOBASE_SHIFT &
529 GDFIFOCFG_EPINFOBASE_MASK;
531 }
532 }
534 /**
535 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
536 * the HFIR register according to PHY type and speed
537 *
538 * @hsotg: Programming view of DWC_otg controller
539 *
540 * NOTE: The caller can modify the value of the HFIR register only after the
541 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
542 * has been set
543 */
545 {
546 u32 usbcfg;
547 u32 hprt0;
557 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
576 /* High speed case */
579 /* FS/LS case */
581 }
583 /**
584 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
585 * buffer
586 *
587 * @core_if: Programming view of DWC_otg controller
588 * @dest: Destination buffer for the packet
589 * @bytes: Number of bytes to copy to the destination
590 */
592 {
598 /*
599 * Todo: Account for the case where dest is not dword aligned. This
600 * requires reading data from the FIFO into a u32 temp buffer, then
601 * moving it into the data buffer.
602 */
608 }
610 /**
611 * dwc2_dump_channel_info() - Prints the state of a host channel
612 *
613 * @hsotg: Programming view of DWC_otg controller
614 * @chan: Pointer to the channel to dump
615 *
616 * Must be called with interrupt disabled and spinlock held
617 *
618 * NOTE: This function will be removed once the peripheral controller code
619 * is integrated and the driver is stable
620 */
623 {
624 #ifdef VERBOSE_DEBUG
627 u32 hcchar;
628 u32 hcsplt;
629 u32 hctsiz;
630 u32 hc_dma;
660 qh_list_entry)
664 qh_list_entry)
668 qh_list_entry)
675 }
677 }
682 {
687 }
690 {
694 }
698 {
703 else
706 }
708 /*
709 * =========================================================================
710 * Low Level Host Channel Access Functions
711 * =========================================================================
712 */
716 {
734 }
740 else
742 }
765 else
767 }
780 }
785 }
790 }
794 {
797 /*
798 * For Descriptor DMA mode core halts the channel on AHB error.
799 * Interrupt is not required.
800 */
810 }
821 }
822 }
827 }
831 {
832 u32 intmsk;
842 }
844 /* Enable the top level host channel interrupt */
851 /* Make sure host channel interrupts are enabled */
857 }
859 /**
860 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
861 * a specific endpoint
862 *
863 * @hsotg: Programming view of DWC_otg controller
864 * @chan: Information needed to initialize the host channel
865 *
866 * The HCCHARn register is set up with the characteristics specified in chan.
867 * Host channel interrupts that may need to be serviced while this transfer is
868 * in progress are enabled.
869 */
871 {
873 u32 hcintmsk;
874 u32 hcchar;
880 /* Clear old interrupt conditions for this host channel */
885 /* Enable channel interrupts required for this transfer */
888 /*
889 * Program the HCCHARn register with the endpoint characteristics for
890 * the current transfer
891 */
919 }
921 /* Program the HCSPLT register for SPLITs */
926 hc_num,
931 HCSPLT_XACTPOS_MASK;
933 HCSPLT_HUBADDR_MASK;
935 HCSPLT_PRTADDR_MASK;
951 }
952 }
955 }
957 /**
958 * dwc2_hc_halt() - Attempts to halt a host channel
959 *
960 * @hsotg: Controller register interface
961 * @chan: Host channel to halt
962 * @halt_status: Reason for halting the channel
963 *
964 * This function should only be called in Slave mode or to abort a transfer in
965 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
966 * controller halts the channel when the transfer is complete or a condition
967 * occurs that requires application intervention.
968 *
969 * In slave mode, checks for a free request queue entry, then sets the Channel
970 * Enable and Channel Disable bits of the Host Channel Characteristics
971 * register of the specified channel to intiate the halt. If there is no free
972 * request queue entry, sets only the Channel Disable bit of the HCCHARn
973 * register to flush requests for this channel. In the latter case, sets a
974 * flag to indicate that the host channel needs to be halted when a request
975 * queue slot is open.
976 *
977 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
978 * HCCHARn register. The controller ensures there is space in the request
979 * queue before submitting the halt request.
980 *
981 * Some time may elapse before the core flushes any posted requests for this
982 * host channel and halts. The Channel Halted interrupt handler completes the
983 * deactivation of the host channel.
984 */
987 {
997 /*
998 * Disable all channel interrupts except Ch Halted. The QTD
999 * and QH state associated with this transfer has been cleared
1000 * (in the case of URB_DEQUEUE), so the channel needs to be
1001 * shut down carefully to prevent crashes.
1002 */
1008 /*
1009 * Make sure no other interrupts besides halt are currently
1010 * pending. Handling another interrupt could cause a crash due
1011 * to the QTD and QH state.
1012 */
1015 /*
1016 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1017 * even if the channel was already halted for some other
1018 * reason
1019 */
1024 /*
1025 * The channel is either already halted or it hasn't
1026 * started yet. In DMA mode, the transfer may halt if
1027 * it finishes normally or a condition occurs that
1028 * requires driver intervention. Don't want to halt
1029 * the channel again. In either Slave or DMA mode,
1030 * it's possible that the transfer has been assigned
1031 * to a channel, but not started yet when an URB is
1032 * dequeued. Don't want to halt a channel that hasn't
1033 * started yet.
1034 */
1036 }
1037 }
1039 /*
1040 * A halt has already been issued for this channel. This might
1041 * happen when a transfer is aborted by a higher level in
1042 * the stack.
1043 */
1048 }
1052 /* No need to set the bit in DDMA for disabling the channel */
1053 /* TODO check it everywhere channel is disabled */
1061 }
1069 /* Check for space in the request queue to issue the halt */
1077 }
1087 }
1088 }
1092 }
1106 }
1112 hcchar);
1119 }
1120 }
1122 /**
1123 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1124 *
1125 * @hsotg: Programming view of DWC_otg controller
1126 * @chan: Identifies the host channel to clean up
1127 *
1128 * This function is normally called after a transfer is done and the host
1129 * channel is being released
1130 */
1132 {
1133 u32 hcintmsk;
1139 /*
1140 * Clear channel interrupt enables and any unhandled channel interrupt
1141 * conditions
1142 */
1147 }
1149 /**
1150 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1151 * which frame a periodic transfer should occur
1152 *
1153 * @hsotg: Programming view of DWC_otg controller
1154 * @chan: Identifies the host channel to set up and its properties
1155 * @hcchar: Current value of the HCCHAR register for the specified host channel
1156 *
1157 * This function has no effect on non-periodic transfers
1158 */
1161 {
1168 u16 fifo_space;
1169 u16 frame_number;
1170 u16 wire_frame;
1172 /*
1173 * Try to figure out if we're an even or odd frame. If we set
1174 * even and the current frame number is even the the transfer
1175 * will happen immediately. Similar if both are odd. If one is
1176 * even and the other is odd then the transfer will happen when
1177 * the frame number ticks.
1178 *
1179 * There's a bit of a balancing act to get this right.
1180 * Sometimes we may want to send data in the current frame (AK
1181 * right away). We might want to do this if the frame number
1182 * _just_ ticked, but we might also want to do this in order
1183 * to continue a split transaction that happened late in a
1184 * microframe (so we didn't know to queue the next transfer
1185 * until the frame number had ticked). The problem is that we
1186 * need a lot of knowledge to know if there's actually still
1187 * time to send things or if it would be better to wait until
1188 * the next frame.
1189 *
1190 * We can look at how much time is left in the current frame
1191 * and make a guess about whether we'll have time to transfer.
1192 * We'll do that.
1193 */
1195 /* Get speed host is running at */
1199 /* See how many bytes are in the periodic FIFO right now */
1204 fifo_space);
1206 /*
1207 * Roughly estimate bus time for everything in the periodic
1208 * queue + our new transfer. This is "rough" because we're
1209 * using a function that makes takes into account IN/OUT
1210 * and INT/ISO and we're just slamming in one value for all
1211 * transfers. This should be an over-estimate and that should
1212 * be OK, but we can probably tighten it.
1213 */
1218 /* See what frame number we'll be at by the time we finish */
1221 /* This is when we were scheduled to be on the wire */
1224 /*
1225 * If we'd finish _after_ the frame we're scheduled in then
1226 * it's hopeless. Just schedule right away and hope for the
1227 * best. Note that it _might_ be wise to call back into the
1228 * scheduler to pick a better frame, but this is better than
1229 * nothing.
1230 */
1236 wire_frame));
1239 /*
1240 * We picked a different frame number; communicate this
1241 * back to the scheduler so it doesn't try to schedule
1242 * another in the same frame.
1243 *
1244 * Remember that next_active_frame is 1 before the wire
1245 * frame.
1246 */
1249 }
1253 else
1255 }
1256 }
1259 {
1260 /* Set up the initial PID for the transfer */
1267 else
1272 else
1274 }
1277 }
1278 }
1280 /**
1281 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1282 * the Host Channel
1283 *
1284 * @hsotg: Programming view of DWC_otg controller
1285 * @chan: Information needed to initialize the host channel
1286 *
1287 * This function should only be called in Slave mode. For a channel associated
1288 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1289 * associated with a periodic EP, the periodic Tx FIFO is written.
1290 *
1291 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1292 * the number of bytes written to the Tx FIFO.
1293 */
1296 {
1297 u32 i;
1298 u32 remaining_count;
1299 u32 byte_count;
1300 u32 dword_count;
1312 else
1318 /* xfer_buf is DWORD aligned */
1322 /* xfer_buf is not DWORD aligned */
1327 }
1328 }
1332 }
1334 /**
1335 * dwc2_hc_do_ping() - Starts a PING transfer
1336 *
1337 * @hsotg: Programming view of DWC_otg controller
1338 * @chan: Information needed to initialize the host channel
1339 *
1340 * This function should only be called in Slave mode. The Do Ping bit is set in
1341 * the HCTSIZ register, then the channel is enabled.
1342 */
1345 {
1346 u32 hcchar;
1347 u32 hctsiz;
1361 }
1363 /**
1364 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1365 * channel and starts the transfer
1366 *
1367 * @hsotg: Programming view of DWC_otg controller
1368 * @chan: Information needed to initialize the host channel. The xfer_len value
1369 * may be reduced to accommodate the max widths of the XferSize and
1370 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1371 * changed to reflect the final xfer_len value.
1372 *
1373 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1374 * the caller must ensure that there is sufficient space in the request queue
1375 * and Tx Data FIFO.
1376 *
1377 * For an OUT transfer in Slave mode, it loads a data packet into the
1378 * appropriate FIFO. If necessary, additional data packets are loaded in the
1379 * Host ISR.
1380 *
1381 * For an IN transfer in Slave mode, a data packet is requested. The data
1382 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1383 * additional data packets are requested in the Host ISR.
1384 *
1385 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1386 * register along with a packet count of 1 and the channel is enabled. This
1387 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1388 * simply set to 0 since no data transfer occurs in this case.
1389 *
1390 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1391 * all the information required to perform the subsequent data transfer. In
1392 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1393 * controller performs the entire PING protocol, then starts the data
1394 * transfer.
1395 */
1398 {
1401 u32 hcchar;
1403 u16 num_packets;
1404 u32 ec_mc;
1416 }
1422 }
1430 /*
1431 * For CSPLIT OUT Transfer, set the size to 0 so the
1432 * core doesn't expect any data written to the FIFO
1433 */
1441 TSIZ_XFERSIZE_MASK;
1443 /* For split set ec_mc for immediate retries */
1447 else
1452 /*
1453 * Ensure that the transfer length and packet count will fit
1454 * in the widths allocated for them in the HCTSIZn register
1455 */
1458 /*
1459 * Make sure the transfer size is no larger than one
1460 * (micro)frame's worth of data. (A check was done
1461 * when the periodic transfer was accepted to ensure
1462 * that a (micro)frame's worth of data can be
1463 * programmed into a channel.)
1464 */
1465 u32 max_periodic_len =
1471 /*
1472 * Make sure that xfer_len is a multiple of max packet
1473 * size
1474 */
1477 }
1485 }
1487 /* Need 1 packet for transfer length of 0 */
1489 }
1492 /*
1493 * Always program an integral # of max packets for IN
1494 * transfers
1495 */
1500 /*
1501 * Make sure that the multi_count field matches the
1502 * actual transfer length
1503 */
1510 TSIZ_XFERSIZE_MASK;
1512 /* The ec_mc gets the multi_count for non-split */
1514 }
1519 TSIZ_SC_MC_PID_MASK;
1529 TSIZ_XFERSIZE_SHIFT);
1532 TSIZ_PKTCNT_SHIFT);
1535 TSIZ_SC_MC_PID_SHIFT);
1536 }
1544 }
1546 /* Start the split */
1552 }
1564 /* Set host channel enable after all other setup is complete */
1571 HCCHAR_MULTICNT_SHIFT);
1583 /* Load OUT packet into the appropriate Tx FIFO */
1585 }
1587 /**
1588 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1589 * host channel and starts the transfer in Descriptor DMA mode
1590 *
1591 * @hsotg: Programming view of DWC_otg controller
1592 * @chan: Information needed to initialize the host channel
1593 *
1594 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1595 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1596 * with micro-frame bitmap.
1597 *
1598 * Initializes HCDMA register with descriptor list address and CTD value then
1599 * starts the transfer via enabling the channel.
1600 */
1603 {
1604 u32 hcchar;
1613 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1615 TSIZ_SC_MC_PID_MASK;
1617 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1620 /* Non-zero only for high-speed interrupt endpoints */
1629 }
1645 HCCHAR_MULTICNT_MASK;
1652 /* Set host channel enable after all other setup is complete */
1659 HCCHAR_MULTICNT_SHIFT);
1668 }
1670 /**
1671 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1672 * a previous call to dwc2_hc_start_transfer()
1673 *
1674 * @hsotg: Programming view of DWC_otg controller
1675 * @chan: Information needed to initialize the host channel
1676 *
1677 * The caller must ensure there is sufficient space in the request queue and Tx
1678 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1679 * the controller acts autonomously to complete transfers programmed to a host
1680 * channel.
1681 *
1682 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1683 * if there is any data remaining to be queued. For an IN transfer, another
1684 * data packet is always requested. For the SETUP phase of a control transfer,
1685 * this function does nothing.
1686 *
1687 * Return: 1 if a new request is queued, 0 if no more requests are required
1688 * for this transfer
1689 */
1692 {
1698 /* SPLITs always queue just once per channel */
1702 /* SETUPs are queued only once since they can't be NAK'd */
1706 /*
1707 * Always queue another request for other IN transfers. If
1708 * back-to-back INs are issued and NAKs are received for both,
1709 * the driver may still be processing the first NAK when the
1710 * second NAK is received. When the interrupt handler clears
1711 * the NAK interrupt for the first NAK, the second NAK will
1712 * not be seen. So we can't depend on the NAK interrupt
1713 * handler to requeue a NAK'd request. Instead, IN requests
1714 * are issued each time this function is called. When the
1715 * transfer completes, the extra requests for the channel will
1716 * be flushed.
1717 */
1725 hcchar);
1729 }
1731 /* OUT transfers */
1741 }
1743 /* Load OUT packet into the appropriate Tx FIFO */
1747 }
1750 }
1752 /*
1753 * =========================================================================
1754 * HCD
1755 * =========================================================================
1756 */
1758 /*
1759 * Processes all the URBs in a single list of QHs. Completes them with
1760 * -ETIMEDOUT and frees the QTD.
1761 *
1762 * Must be called with interrupt disabled and spinlock held
1763 */
1766 {
1772 qtd_list_entry) {
1775 }
1776 }
1777 }
1781 {
1787 /* The list hasn't been initialized yet */
1792 /* Ensure there are no QTDs or URBs left */
1798 /* Free each QTD in the QH's QTD list */
1800 qtd_list_entry)
1809 }
1812 }
1814 /*
1815 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1816 * and periodic schedules. The QTD associated with each URB is removed from
1817 * the schedule and freed. This function may be called when a disconnect is
1818 * detected or when the HCD is being stopped.
1819 *
1820 * Must be called with interrupt disabled and spinlock held
1821 */
1823 {
1831 }
1833 /**
1834 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1835 *
1836 * @hsotg: Pointer to struct dwc2_hsotg
1837 */
1839 {
1840 u32 hprt0;
1843 /*
1844 * Reset the port. During a HNP mode switch the reset
1845 * needs to occur within 1ms and have a duration of at
1846 * least 50ms.
1847 */
1851 }
1855 }
1857 /* Must be called with interrupt disabled and spinlock held */
1859 {
1862 u32 hcchar;
1866 /* Flush out any channel requests in slave mode */
1876 }
1877 }
1878 }
1886 /* Halt the channel */
1889 }
1893 /*
1894 * Added for Descriptor DMA to prevent channel double cleanup in
1895 * release_channel_ddma(), which is called from ep_disable when
1896 * device disconnects
1897 */
1899 }
1900 /* All channels have been freed, mark them available */
1907 }
1908 }
1910 /**
1911 * dwc2_hcd_connect() - Handles connect of the HCD
1912 *
1913 * @hsotg: Pointer to struct dwc2_hsotg
1914 *
1915 * Must be called with interrupt disabled and spinlock held
1916 */
1918 {
1924 }
1926 /**
1927 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1928 *
1929 * @hsotg: Pointer to struct dwc2_hsotg
1930 * @force: If true, we won't try to reconnect even if we see device connected.
1931 *
1932 * Must be called with interrupt disabled and spinlock held
1933 */
1935 {
1936 u32 intr;
1937 u32 hprt0;
1939 /* Set status flags for the hub driver */
1943 /*
1944 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1945 * interrupt mask and status bits and disabling subsequent host
1946 * channel interrupts.
1947 */
1954 /*
1955 * Turn off the vbus power only if the core has transitioned to device
1956 * mode. If still in host mode, need to keep power on to detect a
1957 * reconnection.
1958 */
1963 }
1966 }
1968 /* Respond with an error status to all URBs in the schedule */
1972 /* Clean up any host channels that were in use */
1977 /*
1978 * Add an extra check here to see if we're actually connected but
1979 * we don't have a detection interrupt pending. This can happen if:
1980 * 1. hardware sees connect
1981 * 2. hardware sees disconnect
1982 * 3. hardware sees connect
1983 * 4. dwc2_port_intr() - clears connect interrupt
1984 * 5. dwc2_handle_common_intr() - calls here
1985 *
1986 * Without the extra check here we will end calling disconnect
1987 * and won't get any future interrupts to handle the connect.
1988 */
1993 }
1994 }
1996 /**
1997 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1998 *
1999 * @hsotg: Pointer to struct dwc2_hsotg
2000 */
2002 {
2006 }
2010 }
2012 /**
2013 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2014 *
2015 * @hsotg: Pointer to struct dwc2_hsotg
2016 *
2017 * Must be called with interrupt disabled and spinlock held
2018 */
2020 {
2023 /*
2024 * The root hub should be disconnected before this function is called.
2025 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2026 * and the QH lists (via ..._hcd_endpoint_disable).
2027 */
2029 /* Turn off all host-specific interrupts */
2032 /* Turn off the vbus power */
2035 }
2037 /* Caller must hold driver lock */
2041 {
2042 u32 intr_mask;
2047 /* No longer connected */
2050 }
2054 /* Some configurations cannot support LS traffic on a FS root port */
2063 }
2073 retval);
2075 }
2083 /*
2084 * Do not schedule SG transactions until qtd has
2085 * URB_GIVEBACK_ASAP set
2086 */
2092 }
2095 }
2097 /* Must be called with interrupt disabled and spinlock held */
2100 {
2108 }
2114 }
2121 /* The QTD is in process (it has been assigned to a channel) */
2123 /*
2124 * If still connected (i.e. in host mode), halt the
2125 * channel so it can be used for other transfers. If
2126 * no longer connected, the host registers can't be
2127 * written to halt the channel since the core is in
2128 * device mode.
2129 */
2131 DWC2_HC_XFER_URB_DEQUEUE);
2132 }
2134 /*
2135 * Free the QTD and clean up the associated QH. Leave the QH in the
2136 * schedule if it has any remaining QTDs.
2137 */
2147 }
2150 }
2153 }
2155 /* Must NOT be called with interrupt disabled or spinlock held */
2158 {
2170 }
2178 }
2187 }
2188 }
2192 /* Free each QTD in the QH's QTD list */
2207 err:
2212 }
2214 /* Must be called with interrupt disabled and spinlock held */
2217 {
2226 }
2228 /**
2229 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2230 * prepares the core for device mode or host mode operation
2231 *
2232 * @hsotg: Programming view of the DWC_otg controller
2233 * @initial_setup: If true then this is the first init for this instance.
2234 */
2236 {
2244 /* Set ULPI External VBUS bit if needed */
2249 /* Set external TS Dline pulsing bit if needed */
2256 /*
2257 * Reset the Controller
2258 *
2259 * We only need to reset the controller if this is a re-init.
2260 * For the first init we know for sure that earlier code reset us (it
2261 * needed to in order to properly detect various parameters).
2262 */
2267 __func__);
2269 }
2270 }
2272 /*
2273 * This needs to happen in FS mode before any other programming occurs
2274 */
2279 /* Program the GAHBCFG Register */
2284 /* Program the GUSBCFG register */
2287 /* Program the GOTGCTL register */
2292 /* Clear the SRP success bit for FS-I2c */
2295 /* Enable common interrupts */
2298 /*
2299 * Do device or host initialization based on mode during PCD and
2300 * HCD initialization
2301 */
2308 }
2311 }
2313 /**
2314 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2315 * Host mode
2316 *
2317 * @hsotg: Programming view of DWC_otg controller
2318 *
2319 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2320 * request queues. Host channels are reset to ensure that they are ready for
2321 * performing transfers.
2322 */
2324 {
2329 /* Restart the Phy Clock */
2332 /* Initialize Host Configuration Register */
2339 }
2341 /*
2342 * This bit allows dynamic reloading of the HFIR register during
2343 * runtime. This bit needs to be programmed during initial configuration
2344 * and its value must not be changed during runtime.
2345 */
2350 }
2369 }
2370 }
2372 /* Configure data FIFO sizes */
2375 /* TODO - check this */
2376 /* Clear Host Set HNP Enable in the OTG Control Register */
2381 /* Make sure the FIFOs are flushed */
2385 /* Clear Host Set HNP Enable in the OTG Control Register */
2392 u32 hcchar;
2394 /* Flush out any leftover queued requests */
2402 }
2404 /* Halt all channels to put them into a known state */
2419 i);
2421 }
2424 }
2425 }
2427 /* Turn on the vbus power */
2437 }
2438 }
2441 }
2443 /*
2444 * Initializes dynamic portions of the DWC_otg HCD state
2445 *
2446 * Must be called with interrupt disabled and spinlock held
2447 */
2449 {
2463 }
2465 /*
2466 * Put all channels in the free channel list and clean up channel
2467 * states
2468 */
2470 hc_list_entry)
2478 }
2480 /* Initialize the DWC core for host mode operation */
2482 }
2487 {
2496 }
2501 {
2517 else
2528 /*
2529 * Direction is opposite of data direction or IN if no
2530 * data
2531 */
2535 else
2544 else
2547 }
2574 }
2581 else
2583 }
2585 }
2586 }
2588 #define DWC2_USB_DMA_ALIGN 4
2594 };
2597 {
2613 }
2616 {
2625 /* Allocate a buffer with enough padding for alignment */
2633 /* Position our struct dma_aligned_buffer such that data is aligned */
2645 }
2648 gfp_t mem_flags)
2649 {
2652 /* We assume setup_dma is always aligned; warn if not */
2665 }
2668 {
2671 }
2673 /**
2674 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2675 * channel and initializes the host channel to perform the transactions. The
2676 * host channel is removed from the free list.
2677 *
2678 * @hsotg: The HCD state structure
2679 * @qh: Transactions from the first QTD for this QH are selected and assigned
2680 * to a free host channel
2681 */
2683 {
2694 }
2699 }
2702 hc_list_entry);
2704 /* Remove host channel from free list */
2712 /*
2713 * Use usb_pipedevice to determine device address. This address is
2714 * 0 before the SET_ADDRESS command and the correct address afterward.
2715 */
2728 /*
2729 * The following values may be modified in the transfer type section
2730 * below. The xfer_len value may be reduced when the transfer is
2731 * started to accommodate the max widths of the XferSize and PktCnt
2732 * fields in the HCTSIZn register.
2733 */
2738 else
2750 else
2756 /* Set the split attributes if required */
2759 else
2762 /* Set the transfer attributes */
2767 /*
2768 * This value may be modified when the transfer is started
2769 * to reflect the actual transfer length
2770 */
2776 }
2782 }
2784 /**
2785 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2786 * schedule and assigns them to available host channels. Called from the HCD
2787 * interrupt handler functions.
2788 *
2789 * @hsotg: The HCD state structure
2790 *
2791 * Return: The types of new transactions that were assigned to host channels
2792 */
2795 {
2801 #ifdef DWC2_DEBUG_SOF
2803 #endif
2805 /* Process entries in the periodic ready list */
2814 }
2819 /*
2820 * Move the QH from the periodic ready schedule to the
2821 * periodic assigned schedule
2822 */
2827 }
2829 /*
2830 * Process entries in the inactive portion of the non-periodic
2831 * schedule. Some free host channels may not be used if they are
2832 * reserved for periodic transfers.
2833 */
2848 }
2853 /*
2854 * Move the QH from the non-periodic inactive schedule to the
2855 * non-periodic active schedule
2856 */
2863 else
2868 }
2871 }
2873 /**
2874 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2875 * a host channel associated with either a periodic or non-periodic transfer
2876 *
2877 * @hsotg: The HCD state structure
2878 * @chan: Host channel descriptor associated with either a periodic or
2879 * non-periodic transfer
2880 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2881 * for periodic transfers or the non-periodic Tx FIFO
2882 * for non-periodic transfers
2883 *
2884 * Return: 1 if a request is queued and more requests may be needed to
2885 * complete the transfer, 0 if no more requests are required for this
2886 * transfer, -1 if there is insufficient space in the Tx FIFO
2887 *
2888 * This function assumes that there is space available in the appropriate
2889 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2890 * it checks whether space is available in the appropriate Tx FIFO.
2891 *
2892 * Must be called with interrupt disabled and spinlock held
2893 */
2896 u16 fifo_dwords_avail)
2897 {
2901 /* Put ourselves on the list to keep order straight */
2911 }
2915 }
2917 /* Don't queue a request if the channel has been halted */
2931 }
2934 }
2941 }
2942 }
2945 }
2947 /*
2948 * Processes periodic channels for the next frame and queues transactions for
2949 * these channels to the DWC_otg controller. After queueing transactions, the
2950 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2951 * to queue as Periodic Tx FIFO or request queue space becomes available.
2952 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2953 *
2954 * Must be called with interrupt disabled and spinlock held
2955 */
2957 {
2960 u32 tx_status;
2961 u32 fspcavail;
2962 u32 gintmsk;
2966 u32 qspcavail;
2968 /* If empty list then just adjust interrupt enables */
2977 TXSTS_QSPCAVAIL_SHIFT;
2979 TXSTS_FSPCAVAIL_SHIFT;
2983 qspcavail);
2985 fspcavail);
2986 }
2992 TXSTS_QSPCAVAIL_SHIFT;
2996 }
3002 }
3004 /* Make sure EP's TT buffer is clean before queueing qtds */
3008 }
3010 /*
3011 * Set a flag if we're queuing high-bandwidth in slave mode.
3012 * The flag prevents any halts to get into the request queue in
3013 * the middle of multiple high-bandwidth packets getting queued.
3014 */
3020 TXSTS_FSPCAVAIL_SHIFT;
3025 }
3027 /*
3028 * In Slave mode, stay on the current transfer until there is
3029 * nothing more to do or the high-bandwidth request count is
3030 * reached. In DMA mode, only need to queue one request. The
3031 * controller automatically handles multiple packets for
3032 * high-bandwidth transfers.
3033 */
3037 /*
3038 * Move the QH from the periodic assigned schedule to
3039 * the periodic queued schedule
3040 */
3044 /* done queuing high bandwidth */
3046 }
3047 }
3049 exit:
3053 /*
3054 * May need to queue more transactions as the request
3055 * queue or Tx FIFO empties. Enable the periodic Tx
3056 * FIFO empty interrupt. (Always use the half-empty
3057 * level to ensure that new requests are loaded as
3058 * soon as possible.)
3059 */
3064 }
3066 /*
3067 * Disable the Tx FIFO empty interrupt since there are
3068 * no more transactions that need to be queued right
3069 * now. This function is called from interrupt
3070 * handlers to queue more transactions as transfer
3071 * states change.
3072 */
3077 }
3078 }
3079 }
3081 /*
3082 * Processes active non-periodic channels and queues transactions for these
3083 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3084 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3085 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3086 * FIFO Empty interrupt is disabled.
3087 *
3088 * Must be called with interrupt disabled and spinlock held
3089 */
3091 {
3094 u32 tx_status;
3095 u32 qspcavail;
3096 u32 fspcavail;
3097 u32 gintmsk;
3107 TXSTS_QSPCAVAIL_SHIFT;
3109 TXSTS_FSPCAVAIL_SHIFT;
3111 qspcavail);
3113 fspcavail);
3115 /*
3116 * Keep track of the starting point. Skip over the start-of-list
3117 * entry.
3118 */
3123 /*
3124 * Process once through the active list or until no more space is
3125 * available in the request queue or the Tx FIFO
3126 */
3130 TXSTS_QSPCAVAIL_SHIFT;
3134 }
3137 qh_list_entry);
3141 /* Make sure EP's TT buffer is clean before queueing qtds */
3146 TXSTS_FSPCAVAIL_SHIFT;
3154 }
3155 next:
3156 /* Advance to next QH, skipping start-of-list entry */
3167 TXSTS_QSPCAVAIL_SHIFT;
3169 TXSTS_FSPCAVAIL_SHIFT;
3172 qspcavail);
3175 fspcavail);
3178 /*
3179 * May need to queue more transactions as the request
3180 * queue or Tx FIFO empties. Enable the non-periodic
3181 * Tx FIFO empty interrupt. (Always use the half-empty
3182 * level to ensure that new requests are loaded as
3183 * soon as possible.)
3184 */
3189 /*
3190 * Disable the Tx FIFO empty interrupt since there are
3191 * no more transactions that need to be queued right
3192 * now. This function is called from interrupt
3193 * handlers to queue more transactions as transfer
3194 * states change.
3195 */
3199 }
3200 }
3201 }
3203 /**
3204 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3205 * and queues transactions for these channels to the DWC_otg controller. Called
3206 * from the HCD interrupt handler functions.
3207 *
3208 * @hsotg: The HCD state structure
3209 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3210 * or both)
3211 *
3212 * Must be called with interrupt disabled and spinlock held
3213 */
3216 {
3217 #ifdef DWC2_DEBUG_SOF
3219 #endif
3220 /* Process host channels associated with periodic transfers */
3225 /* Process host channels associated with non-periodic transfers */
3231 /*
3232 * Ensure NP Tx FIFO empty interrupt is disabled when
3233 * there are no non-periodic transfers to process
3234 */
3239 }
3240 }
3241 }
3244 {
3246 wf_otg);
3248 u32 gotgctl;
3258 /* B-Device connector (Device Mode) */
3260 /* Wait for switch to device mode */
3266 }
3273 /*
3274 * Sometimes the initial GOTGCTRL read is wrong, so
3275 * check it again and jump to host mode if that was
3276 * the case.
3277 */
3283 }
3295 host:
3296 /* A-Device connector (Host Mode) */
3305 }
3315 /* Initialize the Core for Host mode */
3319 }
3320 }
3323 {
3325 u32 hprt0;
3329 /*
3330 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3331 * so that OPT tests pass with all PHYs.)
3332 */
3343 /* Change to L0 state */
3345 }
3348 {
3352 }
3354 /* Must NOT be called with interrupt disabled or spinlock held */
3356 {
3358 u32 hprt0;
3359 u32 pcgctl;
3360 u32 gotgctl;
3371 }
3379 /*
3380 * If hibernation is supported, Phy clock will be suspended
3381 * after registers are backuped.
3382 */
3384 /* Suspend the Phy Clock */
3389 }
3391 /* For HNP the bus must be suspended for at least 200ms */
3402 }
3403 }
3405 /* Must NOT be called with interrupt disabled or spinlock held */
3407 {
3409 u32 hprt0;
3410 u32 pcgctl;
3414 /*
3415 * If hibernation is supported, Phy clock is already resumed
3416 * after registers restore.
3417 */
3425 }
3441 }
3443 /* Handles hub class-specific requests */
3446 {
3449 u32 hprt0;
3450 u32 port_status;
3451 u32 speed;
3452 u32 pcgctl;
3461 /* Nothing required here */
3468 wvalue);
3469 }
3504 /* Port indicator not supported */
3508 /*
3509 * Clears driver's internal Connect Status Change flag
3510 */
3517 /* Clears driver's internal Port Reset Change flag */
3524 /*
3525 * Clears the driver's internal Port Enable/Disable
3526 * Change flag
3527 */
3534 /*
3535 * Clears the driver's internal Port Suspend Change
3536 * flag, which is set when resume signaling on the host
3537 * port is complete
3538 */
3560 wvalue);
3561 }
3572 HUB_CHAR_INDV_PORT_OCPM);
3605 }
3608 /*
3609 * The port is disconnected, which means the core is
3610 * either in device mode or it soon will be. Just
3611 * return 0's for the remainder of the port status
3612 * since the port register can't be read if the core
3613 * is in device mode.
3614 */
3617 }
3643 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3646 /*
3647 * Enable descriptor DMA only if a full speed
3648 * device is connected.
3649 */
3653 USB_PORT_STAT_HIGH_SPEED |
3654 USB_PORT_STAT_LOW_SPEED)) ==
3655 USB_PORT_STAT_CONNECTION)) {
3656 u32 hcfg;
3664 }
3665 }
3673 /* No HUB features supported */
3682 /*
3683 * The port is disconnected, which means the core is
3684 * either in device mode or it soon will be. Just
3685 * return without doing anything since the port
3686 * register can't be written if the core is in device
3687 * mode.
3688 */
3690 }
3716 /* ??? Original driver does this */
3720 /* Clear suspend bit if resetting from suspend state */
3723 /*
3724 * When B-Host the Port reset bit is set in the Start
3725 * HCD Callback function, so that the reset is started
3726 * within 1ms of the HNP success interrupt
3727 */
3733 }
3735 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3745 /* Not supported */
3761 wvalue);
3763 }
3767 error:
3773 }
3776 }
3779 {
3804 }
3807 }
3810 {
3813 #ifdef DWC2_DEBUG_SOF
3816 #endif
3818 }
3821 {
3831 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3834 /* Extract fields */
3839 /*
3840 * Number of phy clocks since the last tick of the frame number after
3841 * "us" has passed.
3842 */
3847 }
3850 {
3852 }
3856 gfp_t mem_flags)
3857 {
3866 }
3871 {
3883 }
3885 /*
3886 * NOTE: This function will be removed once the peripheral controller code
3887 * is integrated and the driver is stable
3888 */
3890 {
3891 #ifdef DEBUG
3896 u32 np_tx_status;
3897 u32 p_tx_status;
3953 }
3986 }
3987 }
3988 }
4011 #endif
4012 }
4014 /*
4015 * NOTE: This function will be removed once the peripheral controller code
4016 * is integrated and the driver is stable
4017 */
4019 {
4020 #ifdef DWC2_DUMP_FRREM
4080 #endif
4081 }
4085 };
4087 /* Gets the dwc2_hsotg from a usb_hcd */
4089 {
4094 }
4096 /**
4097 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4098 *
4099 * This will get the dwc2_tt structure (and ttport) associated with the given
4100 * context (which is really just a struct urb pointer).
4101 *
4102 * The first time this is called for a given TT we allocate memory for our
4103 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4104 * then the refcount for the structure will go to 0 and we'll free it.
4105 *
4106 * @hsotg: The HCD state structure for the DWC OTG controller.
4107 * @qh: The QH structure.
4108 * @context: The priv pointer from a struct dwc2_hcd_urb.
4109 * @mem_flags: Flags for allocating memory.
4110 * @ttport: We'll return this device's port number here. That's used to
4111 * reference into the bitmap if we're on a multi_tt hub.
4112 *
4113 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4114 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4115 */
4119 {
4130 /*
4131 * For single_tt we need one schedule. For multi_tt
4132 * we need one per port.
4133 */
4140 mem_flags);
4146 }
4149 }
4152 }
4154 /**
4155 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4156 *
4157 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4158 * of the structure are done.
4159 *
4160 * It's OK to call this with NULL.
4161 *
4162 * @hsotg: The HCD state structure for the DWC OTG controller.
4163 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4164 */
4166 {
4167 /* Model kfree and make put of NULL a no-op */
4177 }
4178 }
4181 {
4185 }
4189 {
4196 else
4198 }
4202 {
4209 else
4211 }
4213 /*
4214 * Sets the final status of an URB and returns it to the upper layer. Any
4215 * required cleanup of the URB is performed.
4216 *
4217 * Must be called with interrupt disabled and spinlock held
4218 */
4221 {
4228 }
4233 }
4239 }
4259 }
4260 }
4266 }
4273 }
4282 urb);
4283 }
4291 }
4293 /*
4294 * Work queue function for starting the HCD when A-Cable is connected
4295 */
4297 {
4303 }
4305 /*
4306 * Reset work queue function
4307 */
4309 {
4313 u32 hprt0;
4325 }
4327 /*
4328 * =========================================================================
4329 * Linux HC Driver Functions
4330 * =========================================================================
4331 */
4333 /*
4334 * Initializes the DWC_otg controller and its root hub and prepares it for host
4335 * mode operation. Activates the root port. Returns 0 on success and a negative
4336 * error code on failure.
4337 */
4339 {
4354 }
4358 /* Initialize and connect root hub if one is not already attached */
4361 /* Inform the HUB driver to resume */
4363 }
4367 }
4369 /*
4370 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4371 * stopped.
4372 */
4374 {
4378 /* Turn off all host-specific interrupts */
4381 /* Wait for interrupt processing to finish */
4385 /* Ensure hcd is disconnected */
4394 }
4397 {
4401 u32 hprt0;
4420 /*
4421 * Drive USB suspend and disable port Power
4422 * if usb bus is not suspended.
4423 */
4429 }
4431 /* Enter hibernation */
4438 }
4440 /* Ask phy to be suspended */
4445 }
4447 /* After entering hibernation, hardware is no more accessible */
4450 skip_power_saving:
4452 unlock:
4456 }
4459 {
4475 }
4477 /*
4478 * Set HW accessible bit before powering on the controller
4479 * since an interrupt may rise.
4480 */
4483 /*
4484 * Enable power if not already done.
4485 * This must not be spinlocked since duration
4486 * of this call is unknown.
4487 */
4492 }
4494 /* Exit hibernation */
4509 /* Wait for controller to correctly update D+/D- level */
4512 /*
4513 * Clear Port Enable and Port Status changes.
4514 * Enable Port Power.
4515 */
4518 /* Wait for controller to detect Port Connect */
4520 }
4523 unlock:
4527 }
4529 /* Returns the current frame number */
4531 {
4535 }
4539 {
4540 #ifdef VERBOSE_DEBUG
4565 }
4584 }
4605 }
4606 }
4607 #endif
4608 }
4610 /*
4611 * Starts processing a USB transfer request specified by a USB Request Block
4612 * (URB). mem_flags indicates the type of memory allocation to use while
4613 * processing this URB.
4614 */
4616 gfp_t mem_flags)
4617 {
4635 }
4646 }
4661 }
4664 mem_flags);
4680 __func__);
4683 }
4684 }
4708 /* Create QH for the endpoint if it doesn't exist */
4714 }
4717 }
4723 }
4737 urb);
4738 }
4744 fail3:
4749 fail2:
4754 fail1:
4760 /* Free each QTD in the QH's QTD list */
4762 qtd_list_entry)
4765 }
4766 fail0:
4770 }
4772 /*
4773 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4774 */
4777 {
4794 }
4803 /* Higher layer software sets URB status */
4810 out:
4814 }
4816 /*
4817 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4818 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4819 * must already be dequeued.
4820 */
4823 {
4830 }
4832 /*
4833 * Resets endpoint specific parameter values, in current version used to reset
4834 * the data toggle (as a WA). This function can be called from usb_clear_halt
4835 * routine.
4836 */
4839 {
4850 }
4852 /*
4853 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4854 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4855 * interrupt.
4856 *
4857 * This function is called by the USB core when an interrupt occurs
4858 */
4860 {
4864 }
4866 /*
4867 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4868 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4869 * is the status change indicator for the single root port. Returns 1 if either
4870 * change indicator is 1, otherwise returns 0.
4871 */
4873 {
4878 }
4880 /* Handles hub class-specific requests */
4883 {
4887 }
4889 /* Handles hub TT buffer clear completions */
4892 {
4908 }
4910 /*
4911 * HPRT0_SPD_HIGH_SPEED: high speed
4912 * HPRT0_SPD_FULL_SPEED: full speed
4913 */
4915 {
4923 }
4926 {
4932 /*
4933 * On removal, set speed to default high-speed.
4934 */
4939 }
4940 }
4943 {
4954 /*
4955 * Change speed setting to full-speed if there's
4956 * a full-speed or low-speed device plugged in.
4957 */
4960 }
4963 }
4990 };
4992 /*
4993 * Frees secondary storage associated with the dwc2_hsotg structure contained
4994 * in the struct usb_hcd field
4995 */
4997 {
4998 u32 ahbcfg;
4999 u32 dctl;
5004 /* Free memory for QH/QTD lists */
5013 /* Free memory for the host channels */
5022 }
5023 }
5031 }
5035 }
5039 /* Disable all interrupts */
5048 }
5054 }
5057 }
5060 {
5061 /* Turn off all host-specific interrupts */
5065 }
5067 /*
5068 * Initializes the HCD. This function allocates memory for and initializes the
5069 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5070 * USB bus with the core and calls the hc_driver->start() function. It returns
5071 * a negative error on failure.
5072 */
5074 {
5079 u32 hcfg;
5093 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5103 #endif
5106 /* Check if the bus driver or platform code has setup a dma_mask */
5113 }
5115 /* Set device flags indicating whether the HCD supports DMA */
5121 }
5126 }
5144 /*
5145 * Disable the global interrupt until all the interrupt handlers are
5146 * installed
5147 */
5150 /* Initialize the DWC_otg core, and select the Phy type */
5155 /* Create new workqueue and init work */
5161 }
5166 /* Initialize the non-periodic schedule */
5171 /* Initialize the periodic schedule */
5179 /*
5180 * Create a host channel descriptor for each host channel implemented
5181 * in the controller. Initialize the channel descriptor array.
5182 */
5194 }
5196 /* Initialize hsotg start work */
5199 /* Initialize port reset work */
5202 /*
5203 * Allocate space for storing data on status transactions. Normally no
5204 * data is sent, but this space acts as a bit bucket. This must be
5205 * done after usb_add_hcd since that function allocates the DMA buffer
5206 * pool.
5207 */
5210 DWC2_HCD_STATUS_BUF_SIZE,
5212 else
5214 GFP_KERNEL);
5219 /*
5220 * Create kmem caches to handle descriptor buffers in descriptor
5221 * DMA mode.
5222 * Alignment must be set to 512 bytes.
5223 */
5229 NULL);
5234 /*
5235 * Disable descriptor dma mode since it will not be
5236 * usable.
5237 */
5240 }
5251 /*
5252 * Disable descriptor dma mode since it will not be
5253 * usable.
5254 */
5257 }
5258 }
5265 /* Initiate lx_state to L3 disconnected state */
5270 /* Don't support SG list at this point */
5276 /*
5277 * Finish generic HCD initialization and start the HCD. This function
5278 * allocates the DMA buffer pool, registers the USB bus, requests the
5279 * IRQ line, and calls hcd_start method.
5280 */
5293 error4:
5296 error3:
5298 error2:
5300 error1:
5302 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5305 #endif
5309 }
5311 /*
5312 * Removes the HCD.
5313 * Frees memory and resources associated with the HCD and deregisters the bus.
5314 */
5316 {
5326 __func__);
5328 }
5342 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5345 #endif
5346 }
5348 /**
5349 * dwc2_backup_host_registers() - Backup controller host registers.
5350 * When suspending usb bus, registers needs to be backuped
5351 * if controller power is disabled once suspended.
5352 *
5353 * @hsotg: Programming view of the DWC_otg controller
5354 */
5356 {
5362 /* Backup Host regs */
5374 }
5376 /**
5377 * dwc2_restore_host_registers() - Restore controller host registers.
5378 * When resuming usb bus, device registers needs to be restored
5379 * if controller power were disabled.
5380 *
5381 * @hsotg: Programming view of the DWC_otg controller
5382 */
5384 {
5390 /* Restore host regs */
5394 __func__);
5396 }
5410 }