include/linux/mlx5/driver.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DRIVER_H
  34 #define MLX5_DRIVER_H
  35
  36 #include <linux/kernel.h>
  37 #include <linux/completion.h>
  38 #include <linux/pci.h>
  39 #include <linux/irq.h>
  40 #include <linux/spinlock_types.h>
  41 #include <linux/semaphore.h>
  42 #include <linux/slab.h>
  43 #include <linux/vmalloc.h>
  44 #include <linux/radix-tree.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/mempool.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/idr.h>
  49
  50 #include <linux/mlx5/device.h>
  51 #include <linux/mlx5/doorbell.h>
  52 #include <linux/mlx5/srq.h>
  53 #include <linux/timecounter.h>
  54 #include <linux/ptp_clock_kernel.h>
  55
  56 enum {
  57         MLX5_BOARD_ID_LEN = 64,
  58         MLX5_MAX_NAME_LEN = 16,
  59 };
  60
  61 enum {
  62         /* one minute for the sake of bringup. Generally, commands must always
  63          * complete and we may need to increase this timeout value
  64          */
  65         MLX5_CMD_TIMEOUT_MSEC   = 60 * 1000,
  66         MLX5_CMD_WQ_MAX_NAME    = 32,
  67 };
  68
  69 enum {
  70         CMD_OWNER_SW            = 0x0,
  71         CMD_OWNER_HW            = 0x1,
  72         CMD_STATUS_SUCCESS      = 0,
  73 };
  74
  75 enum mlx5_sqp_t {
  76         MLX5_SQP_SMI            = 0,
  77         MLX5_SQP_GSI            = 1,
  78         MLX5_SQP_IEEE_1588      = 2,
  79         MLX5_SQP_SNIFFER        = 3,
  80         MLX5_SQP_SYNC_UMR       = 4,
  81 };
  82
  83 enum {
  84         MLX5_MAX_PORTS  = 2,
  85 };
  86
  87 enum {
  88         MLX5_EQ_VEC_PAGES        = 0,
  89         MLX5_EQ_VEC_CMD          = 1,
  90         MLX5_EQ_VEC_ASYNC        = 2,
  91         MLX5_EQ_VEC_PFAULT       = 3,
  92         MLX5_EQ_VEC_COMP_BASE,
  93 };
  94
  95 enum {
  96         MLX5_MAX_IRQ_NAME       = 32
  97 };
  98
  99 enum {
 100         MLX5_ATOMIC_MODE_IB_COMP        = 1 << 16,
 101         MLX5_ATOMIC_MODE_CX             = 2 << 16,
 102         MLX5_ATOMIC_MODE_8B             = 3 << 16,
 103         MLX5_ATOMIC_MODE_16B            = 4 << 16,
 104         MLX5_ATOMIC_MODE_32B            = 5 << 16,
 105         MLX5_ATOMIC_MODE_64B            = 6 << 16,
 106         MLX5_ATOMIC_MODE_128B           = 7 << 16,
 107         MLX5_ATOMIC_MODE_256B           = 8 << 16,
 108 };
 109
 110 enum {
 111         MLX5_REG_QPTS            = 0x4002,
 112         MLX5_REG_QETCR           = 0x4005,
 113         MLX5_REG_QTCT            = 0x400a,
 114         MLX5_REG_QPDPM           = 0x4013,
 115         MLX5_REG_QCAM            = 0x4019,
 116         MLX5_REG_DCBX_PARAM      = 0x4020,
 117         MLX5_REG_DCBX_APP        = 0x4021,
 118         MLX5_REG_FPGA_CAP        = 0x4022,
 119         MLX5_REG_FPGA_CTRL       = 0x4023,
 120         MLX5_REG_FPGA_ACCESS_REG = 0x4024,
 121         MLX5_REG_PCAP            = 0x5001,
 122         MLX5_REG_PMTU            = 0x5003,
 123         MLX5_REG_PTYS            = 0x5004,
 124         MLX5_REG_PAOS            = 0x5006,
 125         MLX5_REG_PFCC            = 0x5007,
 126         MLX5_REG_PPCNT           = 0x5008,
 127         MLX5_REG_PMAOS           = 0x5012,
 128         MLX5_REG_PUDE            = 0x5009,
 129         MLX5_REG_PMPE            = 0x5010,
 130         MLX5_REG_PELC            = 0x500e,
 131         MLX5_REG_PVLC            = 0x500f,
 132         MLX5_REG_PCMR            = 0x5041,
 133         MLX5_REG_PMLP            = 0x5002,
 134         MLX5_REG_PCAM            = 0x507f,
 135         MLX5_REG_NODE_DESC       = 0x6001,
 136         MLX5_REG_HOST_ENDIANNESS = 0x7004,
 137         MLX5_REG_MCIA            = 0x9014,
 138         MLX5_REG_MLCR            = 0x902b,
 139         MLX5_REG_MPCNT           = 0x9051,
 140         MLX5_REG_MTPPS           = 0x9053,
 141         MLX5_REG_MTPPSE          = 0x9054,
 142         MLX5_REG_MCQI            = 0x9061,
 143         MLX5_REG_MCC             = 0x9062,
 144         MLX5_REG_MCDA            = 0x9063,
 145         MLX5_REG_MCAM            = 0x907f,
 146 };
 147
 148 enum mlx5_qpts_trust_state {
 149         MLX5_QPTS_TRUST_PCP  = 1,
 150         MLX5_QPTS_TRUST_DSCP = 2,
 151 };
 152
 153 enum mlx5_dcbx_oper_mode {
 154         MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
 155         MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
 156 };
 157
 158 enum mlx5_dct_atomic_mode {
 159         MLX5_ATOMIC_MODE_DCT_OFF        = 20,
 160         MLX5_ATOMIC_MODE_DCT_NONE       = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
 161         MLX5_ATOMIC_MODE_DCT_IB_COMP    = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
 162         MLX5_ATOMIC_MODE_DCT_CX         = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
 163 };
 164
 165 enum {
 166         MLX5_ATOMIC_OPS_CMP_SWAP        = 1 << 0,
 167         MLX5_ATOMIC_OPS_FETCH_ADD       = 1 << 1,
 168 };
 169
 170 enum mlx5_page_fault_resume_flags {
 171         MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
 172         MLX5_PAGE_FAULT_RESUME_WRITE     = 1 << 1,
 173         MLX5_PAGE_FAULT_RESUME_RDMA      = 1 << 2,
 174         MLX5_PAGE_FAULT_RESUME_ERROR     = 1 << 7,
 175 };
 176
 177 enum dbg_rsc_type {
 178         MLX5_DBG_RSC_QP,
 179         MLX5_DBG_RSC_EQ,
 180         MLX5_DBG_RSC_CQ,
 181 };
 182
 183 enum port_state_policy {
 184         MLX5_POLICY_DOWN        = 0,
 185         MLX5_POLICY_UP          = 1,
 186         MLX5_POLICY_FOLLOW      = 2,
 187         MLX5_POLICY_INVALID     = 0xffffffff
 188 };
 189
 190 struct mlx5_field_desc {
 191         struct dentry          *dent;
 192         int                     i;
 193 };
 194
 195 struct mlx5_rsc_debug {
 196         struct mlx5_core_dev   *dev;
 197         void                   *object;
 198         enum dbg_rsc_type       type;
 199         struct dentry          *root;
 200         struct mlx5_field_desc  fields[0];
 201 };
 202
 203 enum mlx5_dev_event {
 204         MLX5_DEV_EVENT_SYS_ERROR,
 205         MLX5_DEV_EVENT_PORT_UP,
 206         MLX5_DEV_EVENT_PORT_DOWN,
 207         MLX5_DEV_EVENT_PORT_INITIALIZED,
 208         MLX5_DEV_EVENT_LID_CHANGE,
 209         MLX5_DEV_EVENT_PKEY_CHANGE,
 210         MLX5_DEV_EVENT_GUID_CHANGE,
 211         MLX5_DEV_EVENT_CLIENT_REREG,
 212         MLX5_DEV_EVENT_PPS,
 213         MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
 214 };
 215
 216 enum mlx5_port_status {
 217         MLX5_PORT_UP        = 1,
 218         MLX5_PORT_DOWN      = 2,
 219 };
 220
 221 enum mlx5_eq_type {
 222         MLX5_EQ_TYPE_COMP,
 223         MLX5_EQ_TYPE_ASYNC,
 224 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 225         MLX5_EQ_TYPE_PF,
 226 #endif
 227 };
 228
 229 struct mlx5_bfreg_info {
 230         u32                    *sys_pages;
 231         int                     num_low_latency_bfregs;
 232         unsigned int           *count;
 233
 234         /*
 235          * protect bfreg allocation data structs
 236          */
 237         struct mutex            lock;
 238         u32                     ver;
 239         bool                    lib_uar_4k;
 240         u32                     num_sys_pages;
 241         u32                     num_static_sys_pages;
 242         u32                     total_num_bfregs;
 243         u32                     num_dyn_bfregs;
 244 };
 245
 246 struct mlx5_cmd_first {
 247         __be32          data[4];
 248 };
 249
 250 struct mlx5_cmd_msg {
 251         struct list_head                list;
 252         struct cmd_msg_cache           *parent;
 253         u32                             len;
 254         struct mlx5_cmd_first           first;
 255         struct mlx5_cmd_mailbox        *next;
 256 };
 257
 258 struct mlx5_cmd_debug {
 259         struct dentry          *dbg_root;
 260         struct dentry          *dbg_in;
 261         struct dentry          *dbg_out;
 262         struct dentry          *dbg_outlen;
 263         struct dentry          *dbg_status;
 264         struct dentry          *dbg_run;
 265         void                   *in_msg;
 266         void                   *out_msg;
 267         u8                      status;
 268         u16                     inlen;
 269         u16                     outlen;
 270 };
 271
 272 struct cmd_msg_cache {
 273         /* protect block chain allocations
 274          */
 275         spinlock_t              lock;
 276         struct list_head        head;
 277         unsigned int            max_inbox_size;
 278         unsigned int            num_ent;
 279 };
 280
 281 enum {
 282         MLX5_NUM_COMMAND_CACHES = 5,
 283 };
 284
 285 struct mlx5_cmd_stats {
 286         u64             sum;
 287         u64             n;
 288         struct dentry  *root;
 289         struct dentry  *avg;
 290         struct dentry  *count;
 291         /* protect command average calculations */
 292         spinlock_t      lock;
 293 };
 294
 295 struct mlx5_cmd {
 296         void           *cmd_alloc_buf;
 297         dma_addr_t      alloc_dma;
 298         int             alloc_size;
 299         void           *cmd_buf;
 300         dma_addr_t      dma;
 301         u16             cmdif_rev;
 302         u8              log_sz;
 303         u8              log_stride;
 304         int             max_reg_cmds;
 305         int             events;
 306         u32 __iomem    *vector;
 307
 308         /* protect command queue allocations
 309          */
 310         spinlock_t      alloc_lock;
 311
 312         /* protect token allocations
 313          */
 314         spinlock_t      token_lock;
 315         u8              token;
 316         unsigned long   bitmask;
 317         char            wq_name[MLX5_CMD_WQ_MAX_NAME];
 318         struct workqueue_struct *wq;
 319         struct semaphore sem;
 320         struct semaphore pages_sem;
 321         int     mode;
 322         struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
 323         struct dma_pool *pool;
 324         struct mlx5_cmd_debug dbg;
 325         struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
 326         int checksum_disabled;
 327         struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
 328 };
 329
 330 struct mlx5_port_caps {
 331         int     gid_table_len;
 332         int     pkey_table_len;
 333         u8      ext_port_cap;
 334         bool    has_smi;
 335 };
 336
 337 struct mlx5_cmd_mailbox {
 338         void           *buf;
 339         dma_addr_t      dma;
 340         struct mlx5_cmd_mailbox *next;
 341 };
 342
 343 struct mlx5_buf_list {
 344         void                   *buf;
 345         dma_addr_t              map;
 346 };
 347
 348 struct mlx5_buf {
 349         struct mlx5_buf_list    direct;
 350         int                     npages;
 351         int                     size;
 352         u8                      page_shift;
 353 };
 354
 355 struct mlx5_frag_buf {
 356         struct mlx5_buf_list    *frags;
 357         int                     npages;
 358         int                     size;
 359         u8                      page_shift;
 360 };
 361
 362 struct mlx5_eq_tasklet {
 363         struct list_head list;
 364         struct list_head process_list;
 365         struct tasklet_struct task;
 366         /* lock on completion tasklet list */
 367         spinlock_t lock;
 368 };
 369
 370 struct mlx5_eq_pagefault {
 371         struct work_struct       work;
 372         /* Pagefaults lock */
 373         spinlock_t               lock;
 374         struct workqueue_struct *wq;
 375         mempool_t               *pool;
 376 };
 377
 378 struct mlx5_eq {
 379         struct mlx5_core_dev   *dev;
 380         __be32 __iomem         *doorbell;
 381         u32                     cons_index;
 382         struct mlx5_buf         buf;
 383         int                     size;
 384         unsigned int            irqn;
 385         u8                      eqn;
 386         int                     nent;
 387         u64                     mask;
 388         struct list_head        list;
 389         int                     index;
 390         struct mlx5_rsc_debug   *dbg;
 391         enum mlx5_eq_type       type;
 392         union {
 393                 struct mlx5_eq_tasklet   tasklet_ctx;
 394 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 395                 struct mlx5_eq_pagefault pf_ctx;
 396 #endif
 397         };
 398 };
 399
 400 struct mlx5_core_psv {
 401         u32     psv_idx;
 402         struct psv_layout {
 403                 u32     pd;
 404                 u16     syndrome;
 405                 u16     reserved;
 406                 u16     bg;
 407                 u16     app_tag;
 408                 u32     ref_tag;
 409         } psv;
 410 };
 411
 412 struct mlx5_core_sig_ctx {
 413         struct mlx5_core_psv    psv_memory;
 414         struct mlx5_core_psv    psv_wire;
 415         struct ib_sig_err       err_item;
 416         bool                    sig_status_checked;
 417         bool                    sig_err_exists;
 418         u32                     sigerr_count;
 419 };
 420
 421 enum {
 422         MLX5_MKEY_MR = 1,
 423         MLX5_MKEY_MW,
 424 };
 425
 426 struct mlx5_core_mkey {
 427         u64                     iova;
 428         u64                     size;
 429         u32                     key;
 430         u32                     pd;
 431         u32                     type;
 432 };
 433
 434 #define MLX5_24BIT_MASK         ((1 << 24) - 1)
 435
 436 enum mlx5_res_type {
 437         MLX5_RES_QP     = MLX5_EVENT_QUEUE_TYPE_QP,
 438         MLX5_RES_RQ     = MLX5_EVENT_QUEUE_TYPE_RQ,
 439         MLX5_RES_SQ     = MLX5_EVENT_QUEUE_TYPE_SQ,
 440         MLX5_RES_SRQ    = 3,
 441         MLX5_RES_XSRQ   = 4,
 442         MLX5_RES_XRQ    = 5,
 443         MLX5_RES_DCT    = MLX5_EVENT_QUEUE_TYPE_DCT,
 444 };
 445
 446 struct mlx5_core_rsc_common {
 447         enum mlx5_res_type      res;
 448         atomic_t                refcount;
 449         struct completion       free;
 450 };
 451
 452 struct mlx5_core_srq {
 453         struct mlx5_core_rsc_common     common; /* must be first */
 454         u32             srqn;
 455         int             max;
 456         int             max_gs;
 457         int             max_avail_gather;
 458         int             wqe_shift;
 459         void (*event)   (struct mlx5_core_srq *, enum mlx5_event);
 460
 461         atomic_t                refcount;
 462         struct completion       free;
 463 };
 464
 465 struct mlx5_eq_table {
 466         void __iomem           *update_ci;
 467         void __iomem           *update_arm_ci;
 468         struct list_head        comp_eqs_list;
 469         struct mlx5_eq          pages_eq;
 470         struct mlx5_eq          async_eq;
 471         struct mlx5_eq          cmd_eq;
 472 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 473         struct mlx5_eq          pfault_eq;
 474 #endif
 475         int                     num_comp_vectors;
 476         /* protect EQs list
 477          */
 478         spinlock_t              lock;
 479 };
 480
 481 struct mlx5_uars_page {
 482         void __iomem           *map;
 483         bool                    wc;
 484         u32                     index;
 485         struct list_head        list;
 486         unsigned int            bfregs;
 487         unsigned long          *reg_bitmap; /* for non fast path bf regs */
 488         unsigned long          *fp_bitmap;
 489         unsigned int            reg_avail;
 490         unsigned int            fp_avail;
 491         struct kref             ref_count;
 492         struct mlx5_core_dev   *mdev;
 493 };
 494
 495 struct mlx5_bfreg_head {
 496         /* protect blue flame registers allocations */
 497         struct mutex            lock;
 498         struct list_head        list;
 499 };
 500
 501 struct mlx5_bfreg_data {
 502         struct mlx5_bfreg_head  reg_head;
 503         struct mlx5_bfreg_head  wc_head;
 504 };
 505
 506 struct mlx5_sq_bfreg {
 507         void __iomem           *map;
 508         struct mlx5_uars_page  *up;
 509         bool                    wc;
 510         u32                     index;
 511         unsigned int            offset;
 512 };
 513
 514 struct mlx5_core_health {
 515         struct health_buffer __iomem   *health;
 516         __be32 __iomem                 *health_counter;
 517         struct timer_list               timer;
 518         u32                             prev;
 519         int                             miss_counter;
 520         bool                            sick;
 521         /* wq spinlock to synchronize draining */
 522         spinlock_t                      wq_lock;
 523         struct workqueue_struct        *wq;
 524         unsigned long                   flags;
 525         struct work_struct              work;
 526         struct delayed_work             recover_work;
 527 };
 528
 529 struct mlx5_cq_table {
 530         /* protect radix tree
 531          */
 532         spinlock_t              lock;
 533         struct radix_tree_root  tree;
 534 };
 535
 536 struct mlx5_qp_table {
 537         /* protect radix tree
 538          */
 539         spinlock_t              lock;
 540         struct radix_tree_root  tree;
 541 };
 542
 543 struct mlx5_srq_table {
 544         /* protect radix tree
 545          */
 546         spinlock_t              lock;
 547         struct radix_tree_root  tree;
 548 };
 549
 550 struct mlx5_mkey_table {
 551         /* protect radix tree
 552          */
 553         rwlock_t                lock;
 554         struct radix_tree_root  tree;
 555 };
 556
 557 struct mlx5_vf_context {
 558         int     enabled;
 559         u64     port_guid;
 560         u64     node_guid;
 561         enum port_state_policy  policy;
 562 };
 563
 564 struct mlx5_core_sriov {
 565         struct mlx5_vf_context  *vfs_ctx;
 566         int                     num_vfs;
 567         int                     enabled_vfs;
 568 };
 569
 570 struct mlx5_irq_info {
 571         cpumask_var_t mask;
 572         char name[MLX5_MAX_IRQ_NAME];
 573 };
 574
 575 struct mlx5_fc_stats {
 576         struct rb_root counters;
 577         struct list_head addlist;
 578         /* protect addlist add/splice operations */
 579         spinlock_t addlist_lock;
 580
 581         struct workqueue_struct *wq;
 582         struct delayed_work work;
 583         unsigned long next_query;
 584         unsigned long sampling_interval; /* jiffies */
 585 };
 586
 587 struct mlx5_mpfs;
 588 struct mlx5_eswitch;
 589 struct mlx5_lag;
 590 struct mlx5_pagefault;
 591
 592 struct mlx5_rl_entry {
 593         u32                     rate;
 594         u16                     index;
 595         u16                     refcount;
 596 };
 597
 598 struct mlx5_rl_table {
 599         /* protect rate limit table */
 600         struct mutex            rl_lock;
 601         u16                     max_size;
 602         u32                     max_rate;
 603         u32                     min_rate;
 604         struct mlx5_rl_entry   *rl_entry;
 605 };
 606
 607 enum port_module_event_status_type {
 608         MLX5_MODULE_STATUS_PLUGGED   = 0x1,
 609         MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
 610         MLX5_MODULE_STATUS_ERROR     = 0x3,
 611         MLX5_MODULE_STATUS_NUM       = 0x3,
 612 };
 613
 614 enum  port_module_event_error_type {
 615         MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
 616         MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
 617         MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
 618         MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
 619         MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
 620         MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
 621         MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
 622         MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
 623         MLX5_MODULE_EVENT_ERROR_UNKNOWN,
 624         MLX5_MODULE_EVENT_ERROR_NUM,
 625 };
 626
 627 struct mlx5_port_module_event_stats {
 628         u64 status_counters[MLX5_MODULE_STATUS_NUM];
 629         u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
 630 };
 631
 632 struct mlx5_priv {
 633         char                    name[MLX5_MAX_NAME_LEN];
 634         struct mlx5_eq_table    eq_table;
 635         struct mlx5_irq_info    *irq_info;
 636
 637         /* pages stuff */
 638         struct workqueue_struct *pg_wq;
 639         struct rb_root          page_root;
 640         int                     fw_pages;
 641         atomic_t                reg_pages;
 642         struct list_head        free_list;
 643         int                     vfs_pages;
 644
 645         struct mlx5_core_health health;
 646
 647         struct mlx5_srq_table   srq_table;
 648
 649         /* start: qp staff */
 650         struct mlx5_qp_table    qp_table;
 651         struct dentry          *qp_debugfs;
 652         struct dentry          *eq_debugfs;
 653         struct dentry          *cq_debugfs;
 654         struct dentry          *cmdif_debugfs;
 655         /* end: qp staff */
 656
 657         /* start: cq staff */
 658         struct mlx5_cq_table    cq_table;
 659         /* end: cq staff */
 660
 661         /* start: mkey staff */
 662         struct mlx5_mkey_table  mkey_table;
 663         /* end: mkey staff */
 664
 665         /* start: alloc staff */
 666         /* protect buffer alocation according to numa node */
 667         struct mutex            alloc_mutex;
 668         int                     numa_node;
 669
 670         struct mutex            pgdir_mutex;
 671         struct list_head        pgdir_list;
 672         /* end: alloc staff */
 673         struct dentry          *dbg_root;
 674
 675         /* protect mkey key part */
 676         spinlock_t              mkey_lock;
 677         u8                      mkey_key;
 678
 679         struct list_head        dev_list;
 680         struct list_head        ctx_list;
 681         spinlock_t              ctx_lock;
 682
 683         struct list_head        waiting_events_list;
 684         bool                    is_accum_events;
 685
 686         struct mlx5_flow_steering *steering;
 687         struct mlx5_mpfs        *mpfs;
 688         struct mlx5_eswitch     *eswitch;
 689         struct mlx5_core_sriov  sriov;
 690         struct mlx5_lag         *lag;
 691         unsigned long           pci_dev_data;
 692         struct mlx5_fc_stats            fc_stats;
 693         struct mlx5_rl_table            rl_table;
 694
 695         struct mlx5_port_module_event_stats  pme_stats;
 696
 697 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 698         void                  (*pfault)(struct mlx5_core_dev *dev,
 699                                         void *context,
 700                                         struct mlx5_pagefault *pfault);
 701         void                   *pfault_ctx;
 702         struct srcu_struct      pfault_srcu;
 703 #endif
 704         struct mlx5_bfreg_data          bfregs;
 705         struct mlx5_uars_page          *uar;
 706 };
 707
 708 enum mlx5_device_state {
 709         MLX5_DEVICE_STATE_UP,
 710         MLX5_DEVICE_STATE_INTERNAL_ERROR,
 711 };
 712
 713 enum mlx5_interface_state {
 714         MLX5_INTERFACE_STATE_UP = BIT(0),
 715 };
 716
 717 enum mlx5_pci_status {
 718         MLX5_PCI_STATUS_DISABLED,
 719         MLX5_PCI_STATUS_ENABLED,
 720 };
 721
 722 enum mlx5_pagefault_type_flags {
 723         MLX5_PFAULT_REQUESTOR = 1 << 0,
 724         MLX5_PFAULT_WRITE     = 1 << 1,
 725         MLX5_PFAULT_RDMA      = 1 << 2,
 726 };
 727
 728 /* Contains the details of a pagefault. */
 729 struct mlx5_pagefault {
 730         u32                     bytes_committed;
 731         u32                     token;
 732         u8                      event_subtype;
 733         u8                      type;
 734         union {
 735                 /* Initiator or send message responder pagefault details. */
 736                 struct {
 737                         /* Received packet size, only valid for responders. */
 738                         u32     packet_size;
 739                         /*
 740                          * Number of resource holding WQE, depends on type.
 741                          */
 742                         u32     wq_num;
 743                         /*
 744                          * WQE index. Refers to either the send queue or
 745                          * receive queue, according to event_subtype.
 746                          */
 747                         u16     wqe_index;
 748                 } wqe;
 749                 /* RDMA responder pagefault details */
 750                 struct {
 751                         u32     r_key;
 752                         /*
 753                          * Received packet size, minimal size page fault
 754                          * resolution required for forward progress.
 755                          */
 756                         u32     packet_size;
 757                         u32     rdma_op_len;
 758                         u64     rdma_va;
 759                 } rdma;
 760         };
 761
 762         struct mlx5_eq         *eq;
 763         struct work_struct      work;
 764 };
 765
 766 struct mlx5_td {
 767         struct list_head tirs_list;
 768         u32              tdn;
 769 };
 770
 771 struct mlx5e_resources {
 772         u32                        pdn;
 773         struct mlx5_td             td;
 774         struct mlx5_core_mkey      mkey;
 775         struct mlx5_sq_bfreg       bfreg;
 776 };
 777
 778 #define MLX5_MAX_RESERVED_GIDS 8
 779
 780 struct mlx5_rsvd_gids {
 781         unsigned int start;
 782         unsigned int count;
 783         struct ida ida;
 784 };
 785
 786 #define MAX_PIN_NUM     8
 787 struct mlx5_pps {
 788         u8                         pin_caps[MAX_PIN_NUM];
 789         struct work_struct         out_work;
 790         u64                        start[MAX_PIN_NUM];
 791         u8                         enabled;
 792 };
 793
 794 struct mlx5_clock {
 795         rwlock_t                   lock;
 796         struct cyclecounter        cycles;
 797         struct timecounter         tc;
 798         struct hwtstamp_config     hwtstamp_config;
 799         u32                        nominal_c_mult;
 800         unsigned long              overflow_period;
 801         struct delayed_work        overflow_work;
 802         struct mlx5_core_dev      *mdev;
 803         struct ptp_clock          *ptp;
 804         struct ptp_clock_info      ptp_info;
 805         struct mlx5_pps            pps_info;
 806 };
 807
 808 struct mlx5_core_dev {
 809         struct pci_dev         *pdev;
 810         /* sync pci state */
 811         struct mutex            pci_status_mutex;
 812         enum mlx5_pci_status    pci_status;
 813         u8                      rev_id;
 814         char                    board_id[MLX5_BOARD_ID_LEN];
 815         struct mlx5_cmd         cmd;
 816         struct mlx5_port_caps   port_caps[MLX5_MAX_PORTS];
 817         struct {
 818                 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 819                 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 820                 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
 821                 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
 822                 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
 823                 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
 824         } caps;
 825         phys_addr_t             iseg_base;
 826         struct mlx5_init_seg __iomem *iseg;
 827         enum mlx5_device_state  state;
 828         /* sync interface state */
 829         struct mutex            intf_state_mutex;
 830         unsigned long           intf_state;
 831         void                    (*event) (struct mlx5_core_dev *dev,
 832                                           enum mlx5_dev_event event,
 833                                           unsigned long param);
 834         struct mlx5_priv        priv;
 835         struct mlx5_profile     *profile;
 836         atomic_t                num_qps;
 837         u32                     issi;
 838         struct mlx5e_resources  mlx5e_res;
 839         struct {
 840                 struct mlx5_rsvd_gids   reserved_gids;
 841                 u32                     roce_en;
 842         } roce;
 843 #ifdef CONFIG_MLX5_FPGA
 844         struct mlx5_fpga_device *fpga;
 845 #endif
 846 #ifdef CONFIG_RFS_ACCEL
 847         struct cpu_rmap         *rmap;
 848 #endif
 849         struct mlx5_clock        clock;
 850         struct mlx5_ib_clock_info  *clock_info;
 851         struct page             *clock_info_page;
 852 };
 853
 854 struct mlx5_db {
 855         __be32                  *db;
 856         union {
 857                 struct mlx5_db_pgdir            *pgdir;
 858                 struct mlx5_ib_user_db_page     *user_page;
 859         }                       u;
 860         dma_addr_t              dma;
 861         int                     index;
 862 };
 863
 864 enum {
 865         MLX5_COMP_EQ_SIZE = 1024,
 866 };
 867
 868 enum {
 869         MLX5_PTYS_IB = 1 << 0,
 870         MLX5_PTYS_EN = 1 << 2,
 871 };
 872
 873 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
 874
 875 enum {
 876         MLX5_CMD_ENT_STATE_PENDING_COMP,
 877 };
 878
 879 struct mlx5_cmd_work_ent {
 880         unsigned long           state;
 881         struct mlx5_cmd_msg    *in;
 882         struct mlx5_cmd_msg    *out;
 883         void                   *uout;
 884         int                     uout_size;
 885         mlx5_cmd_cbk_t          callback;
 886         struct delayed_work     cb_timeout_work;
 887         void                   *context;
 888         int                     idx;
 889         struct completion       done;
 890         struct mlx5_cmd        *cmd;
 891         struct work_struct      work;
 892         struct mlx5_cmd_layout *lay;
 893         int                     ret;
 894         int                     page_queue;
 895         u8                      status;
 896         u8                      token;
 897         u64                     ts1;
 898         u64                     ts2;
 899         u16                     op;
 900         bool                    polling;
 901 };
 902
 903 struct mlx5_pas {
 904         u64     pa;
 905         u8      log_sz;
 906 };
 907
 908 enum phy_port_state {
 909         MLX5_AAA_111
 910 };
 911
 912 struct mlx5_hca_vport_context {
 913         u32                     field_select;
 914         bool                    sm_virt_aware;
 915         bool                    has_smi;
 916         bool                    has_raw;
 917         enum port_state_policy  policy;
 918         enum phy_port_state     phys_state;
 919         enum ib_port_state      vport_state;
 920         u8                      port_physical_state;
 921         u64                     sys_image_guid;
 922         u64                     port_guid;
 923         u64                     node_guid;
 924         u32                     cap_mask1;
 925         u32                     cap_mask1_perm;
 926         u32                     cap_mask2;
 927         u32                     cap_mask2_perm;
 928         u16                     lid;
 929         u8                      init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
 930         u8                      lmc;
 931         u8                      subnet_timeout;
 932         u16                     sm_lid;
 933         u8                      sm_sl;
 934         u16                     qkey_violation_counter;
 935         u16                     pkey_violation_counter;
 936         bool                    grh_required;
 937 };
 938
 939 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
 940 {
 941                 return buf->direct.buf + offset;
 942 }
 943
 944 #define STRUCT_FIELD(header, field) \
 945         .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
 946         .struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
 947
 948 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
 949 {
 950         return pci_get_drvdata(pdev);
 951 }
 952
 953 extern struct dentry *mlx5_debugfs_root;
 954
 955 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
 956 {
 957         return ioread32be(&dev->iseg->fw_rev) & 0xffff;
 958 }
 959
 960 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
 961 {
 962         return ioread32be(&dev->iseg->fw_rev) >> 16;
 963 }
 964
 965 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
 966 {
 967         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
 968 }
 969
 970 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
 971 {
 972         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
 973 }
 974
 975 static inline u32 mlx5_base_mkey(const u32 key)
 976 {
 977         return key & 0xffffff00u;
 978 }
 979
 980 int mlx5_cmd_init(struct mlx5_core_dev *dev);
 981 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
 982 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
 983 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
 984
 985 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 986                   int out_size);
 987 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
 988                      void *out, int out_size, mlx5_cmd_cbk_t callback,
 989                      void *context);
 990 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
 991                           void *out, int out_size);
 992 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
 993
 994 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
 995 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
 996 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
 997 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
 998 int mlx5_health_init(struct mlx5_core_dev *dev);
 999 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1000 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
1001 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1002 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1003 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
1004 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1005                         struct mlx5_buf *buf, int node);
1006 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
1007 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
1008 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1009                              struct mlx5_frag_buf *buf, int node);
1010 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1011 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1012                                                       gfp_t flags, int npages);
1013 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1014                                  struct mlx5_cmd_mailbox *head);
1015 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1016                          struct mlx5_srq_attr *in);
1017 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1018 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1019                         struct mlx5_srq_attr *out);
1020 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1021                       u16 lwm, int is_srq);
1022 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
1023 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
1024 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1025                              struct mlx5_core_mkey *mkey,
1026                              u32 *in, int inlen,
1027                              u32 *out, int outlen,
1028                              mlx5_cmd_cbk_t callback, void *context);
1029 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1030                           struct mlx5_core_mkey *mkey,
1031                           u32 *in, int inlen);
1032 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1033                            struct mlx5_core_mkey *mkey);
1034 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1035                          u32 *out, int outlen);
1036 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
1037                              u32 *mkey);
1038 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1039 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1040 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1041                       u16 opmod, u8 port);
1042 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1043 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1044 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1045 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1046 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1047                                  s32 npages);
1048 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1049 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1050 void mlx5_register_debugfs(void);
1051 void mlx5_unregister_debugfs(void);
1052 int mlx5_eq_init(struct mlx5_core_dev *dev);
1053 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1054 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1055 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1056 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1057 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1058 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1059 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1060 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
1061 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1062 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1063                        int nent, u64 mask, const char *name,
1064                        enum mlx5_eq_type type);
1065 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1066 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1067 void mlx5_stop_eqs(struct mlx5_core_dev *dev);
1068 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1069                     unsigned int *irqn);
1070 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1071 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1072
1073 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1074 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1075 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1076                          int size_in, void *data_out, int size_out,
1077                          u16 reg_num, int arg, int write);
1078
1079 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1080 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1081 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1082                        u32 *out, int outlen);
1083 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1084 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1085 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1086 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1087 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1088 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1089                        int node);
1090 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1091
1092 const char *mlx5_command_str(int command);
1093 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1094 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1095 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1096                          int npsvs, u32 *sig_index);
1097 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1098 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1099 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1100                         struct mlx5_odp_caps *odp_caps);
1101 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1102                              u8 port_num, void *out, size_t sz);
1103 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1104 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1105                                 u32 wq_num, u8 type, int error);
1106 #endif
1107
1108 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1109 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1110 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1111 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1112 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1113 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1114                      bool map_wc, bool fast_path);
1115 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1116
1117 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1118 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1119                            u8 roce_version, u8 roce_l3_type, const u8 *gid,
1120                            const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1121
1122 static inline int fw_initializing(struct mlx5_core_dev *dev)
1123 {
1124         return ioread32be(&dev->iseg->initializing) >> 31;
1125 }
1126
1127 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1128 {
1129         return mkey >> 8;
1130 }
1131
1132 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1133 {
1134         return mkey_idx << 8;
1135 }
1136
1137 static inline u8 mlx5_mkey_variant(u32 mkey)
1138 {
1139         return mkey & 0xff;
1140 }
1141
1142 enum {
1143         MLX5_PROF_MASK_QP_SIZE          = (u64)1 << 0,
1144         MLX5_PROF_MASK_MR_CACHE         = (u64)1 << 1,
1145 };
1146
1147 enum {
1148         MR_CACHE_LAST_STD_ENTRY = 20,
1149         MLX5_IMR_MTT_CACHE_ENTRY,
1150         MLX5_IMR_KSM_CACHE_ENTRY,
1151         MAX_MR_CACHE_ENTRIES
1152 };
1153
1154 enum {
1155         MLX5_INTERFACE_PROTOCOL_IB  = 0,
1156         MLX5_INTERFACE_PROTOCOL_ETH = 1,
1157 };
1158
1159 struct mlx5_interface {
1160         void *                  (*add)(struct mlx5_core_dev *dev);
1161         void                    (*remove)(struct mlx5_core_dev *dev, void *context);
1162         int                     (*attach)(struct mlx5_core_dev *dev, void *context);
1163         void                    (*detach)(struct mlx5_core_dev *dev, void *context);
1164         void                    (*event)(struct mlx5_core_dev *dev, void *context,
1165                                          enum mlx5_dev_event event, unsigned long param);
1166         void                    (*pfault)(struct mlx5_core_dev *dev,
1167                                           void *context,
1168                                           struct mlx5_pagefault *pfault);
1169         void *                  (*get_dev)(void *context);
1170         int                     protocol;
1171         struct list_head        list;
1172 };
1173
1174 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1175 int mlx5_register_interface(struct mlx5_interface *intf);
1176 void mlx5_unregister_interface(struct mlx5_interface *intf);
1177 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1178
1179 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1180 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1181 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1182 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1183 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1184                                  u64 *values,
1185                                  int num_counters,
1186                                  size_t *offsets);
1187 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1188 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1189
1190 #ifndef CONFIG_MLX5_CORE_IPOIB
1191 static inline
1192 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1193                                           struct ib_device *ibdev,
1194                                           const char *name,
1195                                           void (*setup)(struct net_device *))
1196 {
1197         return ERR_PTR(-EOPNOTSUPP);
1198 }
1199
1200 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1201 #else
1202 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1203                                           struct ib_device *ibdev,
1204                                           const char *name,
1205                                           void (*setup)(struct net_device *));
1206 void mlx5_rdma_netdev_free(struct net_device *netdev);
1207 #endif /* CONFIG_MLX5_CORE_IPOIB */
1208
1209 struct mlx5_profile {
1210         u64     mask;
1211         u8      log_max_qp;
1212         struct {
1213                 int     size;
1214                 int     limit;
1215         } mr_cache[MAX_MR_CACHE_ENTRIES];
1216 };
1217
1218 enum {
1219         MLX5_PCI_DEV_IS_VF              = 1 << 0,
1220 };
1221
1222 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1223 {
1224         return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1225 }
1226
1227 static inline int mlx5_get_gid_table_len(u16 param)
1228 {
1229         if (param > 4) {
1230                 pr_warn("gid table length is zero\n");
1231                 return 0;
1232         }
1233
1234         return 8 * (1 << param);
1235 }
1236
1237 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1238 {
1239         return !!(dev->priv.rl_table.max_size);
1240 }
1241
1242 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1243 {
1244         return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1245                MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1246 }
1247
1248 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1249 {
1250         return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1251 }
1252
1253 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1254 {
1255         return mlx5_core_is_mp_slave(dev) ||
1256                mlx5_core_is_mp_master(dev);
1257 }
1258
1259 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1260 {
1261         if (!mlx5_core_mp_enabled(dev))
1262                 return 1;
1263
1264         return MLX5_CAP_GEN(dev, native_port_num);
1265 }
1266
1267 enum {
1268         MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1269 };
1270
1271 static inline const struct cpumask *
1272 mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector)
1273 {
1274         const struct cpumask *mask;
1275         struct irq_desc *desc;
1276         unsigned int irq;
1277         int eqn;
1278         int err;
1279
1280         err = mlx5_vector2eqn(dev, MLX5_EQ_VEC_COMP_BASE + vector, &eqn, &irq);
1281         if (err)
1282                 return NULL;
1283
1284         desc = irq_to_desc(irq);
1285 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
1286         mask = irq_data_get_effective_affinity_mask(&desc->irq_data);
1287 #else
1288         mask = desc->irq_common_data.affinity;
1289 #endif
1290         return mask;
1291 }
1292
1293 #endif /* MLX5_DRIVER_H */