include/linux/sh_dma.h

   1 /*
   2  * Header for the new SH dmaengine driver
   3  *
   4  * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef SH_DMA_H
  11 #define SH_DMA_H
  12
  13 #include <linux/dmaengine.h>
  14 #include <linux/list.h>
  15 #include <linux/shdma-base.h>
  16 #include <linux/types.h>
  17
  18 struct device;
  19
  20 /* Used by slave DMA clients to request DMA to/from a specific peripheral */
  21 struct sh_dmae_slave {
  22         struct shdma_slave              shdma_slave;    /* Set by the platform */
  23 };
  24
  25 /*
  26  * Supplied by platforms to specify, how a DMA channel has to be configured for
  27  * a certain peripheral
  28  */
  29 struct sh_dmae_slave_config {
  30         int             slave_id;
  31         dma_addr_t      addr;
  32         u32             chcr;
  33         char            mid_rid;
  34 };
  35
  36 /**
  37  * struct sh_dmae_channel - DMAC channel platform data
  38  * @offset:             register offset within the main IOMEM resource
  39  * @dmars:              channel DMARS register offset
  40  * @chclr_offset:       channel CHCLR register offset
  41  * @dmars_bit:          channel DMARS field offset within the register
  42  * @chclr_bit:          bit position, to be set to reset the channel
  43  */
  44 struct sh_dmae_channel {
  45         unsigned int    offset;
  46         unsigned int    dmars;
  47         unsigned int    chclr_offset;
  48         unsigned char   dmars_bit;
  49         unsigned char   chclr_bit;
  50 };
  51
  52 /**
  53  * struct sh_dmae_pdata - DMAC platform data
  54  * @slave:              array of slaves
  55  * @slave_num:          number of slaves in the above array
  56  * @channel:            array of DMA channels
  57  * @channel_num:        number of channels in the above array
  58  * @ts_low_shift:       shift of the low part of the TS field
  59  * @ts_low_mask:        low TS field mask
  60  * @ts_high_shift:      additional shift of the high part of the TS field
  61  * @ts_high_mask:       high TS field mask
  62  * @ts_shift:           array of Transfer Size shifts, indexed by TS value
  63  * @ts_shift_num:       number of shifts in the above array
  64  * @dmaor_init:         DMAOR initialisation value
  65  * @chcr_offset:        CHCR address offset
  66  * @chcr_ie_bit:        CHCR Interrupt Enable bit
  67  * @dmaor_is_32bit:     DMAOR is a 32-bit register
  68  * @needs_tend_set:     the TEND register has to be set
  69  * @no_dmars:           DMAC has no DMARS registers
  70  * @chclr_present:      DMAC has one or several CHCLR registers
  71  * @chclr_bitwise:      channel CHCLR registers are bitwise
  72  * @slave_only:         DMAC cannot be used for MEMCPY
  73  */
  74 struct sh_dmae_pdata {
  75         const struct sh_dmae_slave_config *slave;
  76         int slave_num;
  77         const struct sh_dmae_channel *channel;
  78         int channel_num;
  79         unsigned int ts_low_shift;
  80         unsigned int ts_low_mask;
  81         unsigned int ts_high_shift;
  82         unsigned int ts_high_mask;
  83         const unsigned int *ts_shift;
  84         int ts_shift_num;
  85         u16 dmaor_init;
  86         unsigned int chcr_offset;
  87         u32 chcr_ie_bit;
  88
  89         unsigned int dmaor_is_32bit:1;
  90         unsigned int needs_tend_set:1;
  91         unsigned int no_dmars:1;
  92         unsigned int chclr_present:1;
  93         unsigned int chclr_bitwise:1;
  94         unsigned int slave_only:1;
  95 };
  96
  97 /* DMAOR definitions */
  98 #define DMAOR_AE        0x00000004      /* Address Error Flag */
  99 #define DMAOR_NMIF      0x00000002
 100 #define DMAOR_DME       0x00000001      /* DMA Master Enable */
 101
 102 /* Definitions for the SuperH DMAC */
 103 #define DM_INC  0x00004000      /* Destination addresses are incremented */
 104 #define DM_DEC  0x00008000      /* Destination addresses are decremented */
 105 #define DM_FIX  0x0000c000      /* Destination address is fixed */
 106 #define SM_INC  0x00001000      /* Source addresses are incremented */
 107 #define SM_DEC  0x00002000      /* Source addresses are decremented */
 108 #define SM_FIX  0x00003000      /* Source address is fixed */
 109 #define RS_AUTO 0x00000400      /* Auto Request */
 110 #define RS_ERS  0x00000800      /* DMA extended resource selector */
 111 #define CHCR_DE 0x00000001      /* DMA Enable */
 112 #define CHCR_TE 0x00000002      /* Transfer End Flag */
 113 #define CHCR_IE 0x00000004      /* Interrupt Enable */
 114
 115 #endif