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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / sound / pci / emu10k1 / emu10k1_main.c
blobccf4415a1c7b8461dea3ed1c9d69f67408b750e2
1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Creative Labs, Inc.
4 * Routines for control of EMU10K1 chips
5 *
6 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
7 * Added support for Audigy 2 Value.
8 * Added EMU 1010 support.
9 * General bug fixes and enhancements.
10 *
11 *
12 * BUGS:
13 * --
14 *
15 * TODO:
16 * --
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 */
33
34 #include <linux/sched.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/mutex.h>
43
44
45 #include <sound/core.h>
46 #include <sound/emu10k1.h>
47 #include <linux/firmware.h>
48 #include "p16v.h"
49 #include "tina2.h"
50 #include "p17v.h"
51
52
53 #define HANA_FILENAME "emu/hana.fw"
54 #define DOCK_FILENAME "emu/audio_dock.fw"
55 #define EMU1010B_FILENAME "emu/emu1010b.fw"
56 #define MICRO_DOCK_FILENAME "emu/micro_dock.fw"
57 #define EMU0404_FILENAME "emu/emu0404.fw"
58 #define EMU1010_NOTEBOOK_FILENAME "emu/emu1010_notebook.fw"
59
60 MODULE_FIRMWARE(HANA_FILENAME);
61 MODULE_FIRMWARE(DOCK_FILENAME);
62 MODULE_FIRMWARE(EMU1010B_FILENAME);
63 MODULE_FIRMWARE(MICRO_DOCK_FILENAME);
64 MODULE_FIRMWARE(EMU0404_FILENAME);
65 MODULE_FIRMWARE(EMU1010_NOTEBOOK_FILENAME);
66
67
68 /*************************************************************************
69 * EMU10K1 init / done
70 *************************************************************************/
71
72 void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch)
73 {
74 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
75 snd_emu10k1_ptr_write(emu, IP, ch, 0);
76 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
77 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
78 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
79 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
80 snd_emu10k1_ptr_write(emu, CCR, ch, 0);
81
82 snd_emu10k1_ptr_write(emu, PSST, ch, 0);
83 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
84 snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
85 snd_emu10k1_ptr_write(emu, Z1, ch, 0);
86 snd_emu10k1_ptr_write(emu, Z2, ch, 0);
87 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
88
89 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
90 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
91 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
92 snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
93 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
94 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
95 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
96 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
97
98 /*** these are last so OFF prevents writing ***/
99 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
100 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
101 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
102 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
103 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
104
105 /* Audigy extra stuffs */
106 if (emu->audigy) {
107 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
108 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
109 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
110 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
111 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
112 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
113 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
114 }
115 }
116
117 static unsigned int spi_dac_init[] = {
118 0x00ff,
119 0x02ff,
120 0x0400,
121 0x0520,
122 0x0600,
123 0x08ff,
124 0x0aff,
125 0x0cff,
126 0x0eff,
127 0x10ff,
128 0x1200,
129 0x1400,
130 0x1480,
131 0x1800,
132 0x1aff,
133 0x1cff,
134 0x1e00,
135 0x0530,
136 0x0602,
137 0x0622,
138 0x1400,
139 };
140
141 static unsigned int i2c_adc_init[][2] = {
142 { 0x17, 0x00 }, /* Reset */
143 { 0x07, 0x00 }, /* Timeout */
144 { 0x0b, 0x22 }, /* Interface control */
145 { 0x0c, 0x22 }, /* Master mode control */
146 { 0x0d, 0x08 }, /* Powerdown control */
147 { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */
148 { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */
149 { 0x10, 0x7b }, /* ALC Control 1 */
150 { 0x11, 0x00 }, /* ALC Control 2 */
151 { 0x12, 0x32 }, /* ALC Control 3 */
152 { 0x13, 0x00 }, /* Noise gate control */
153 { 0x14, 0xa6 }, /* Limiter control */
154 { 0x15, ADC_MUX_2 }, /* ADC Mixer control. Mic for A2ZS Notebook */
155 };
156
157 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
158 {
159 unsigned int silent_page;
160 int ch;
161 u32 tmp;
162
163 /* disable audio and lock cache */
164 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK |
165 HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
166
167 /* reset recording buffers */
168 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
169 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
170 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
171 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
172 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
173 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
174
175 /* disable channel interrupt */
176 outl(0, emu->port + INTE);
177 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
178 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
179 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
180 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
181
182 if (emu->audigy) {
183 /* set SPDIF bypass mode */
184 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
185 /* enable rear left + rear right AC97 slots */
186 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT |
187 AC97SLOT_REAR_LEFT);
188 }
189
190 /* init envelope engine */
191 for (ch = 0; ch < NUM_G; ch++)
192 snd_emu10k1_voice_init(emu, ch);
193
194 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]);
195 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]);
196 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]);
197
198 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
199 /* Hacks for Alice3 to work independent of haP16V driver */
200 /* Setup SRCMulti_I2S SamplingRate */
201 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
202 tmp &= 0xfffff1ff;
203 tmp |= (0x2<<9);
204 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
205
206 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
207 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
208 /* Setup SRCMulti Input Audio Enable */
209 /* Use 0xFFFFFFFF to enable P16V sounds. */
210 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF);
211
212 /* Enabled Phased (8-channel) P16V playback */
213 outl(0x0201, emu->port + HCFG2);
214 /* Set playback routing. */
215 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
216 }
217 if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */
218 /* Hacks for Alice3 to work independent of haP16V driver */
219 dev_info(emu->card->dev, "Audigy2 value: Special config.\n");
220 /* Setup SRCMulti_I2S SamplingRate */
221 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
222 tmp &= 0xfffff1ff;
223 tmp |= (0x2<<9);
224 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
225
226 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
227 outl(0x600000, emu->port + 0x20);
228 outl(0x14, emu->port + 0x24);
229
230 /* Setup SRCMulti Input Audio Enable */
231 outl(0x7b0000, emu->port + 0x20);
232 outl(0xFF000000, emu->port + 0x24);
233
234 /* Setup SPDIF Out Audio Enable */
235 /* The Audigy 2 Value has a separate SPDIF out,
236 * so no need for a mixer switch
237 */
238 outl(0x7a0000, emu->port + 0x20);
239 outl(0xFF000000, emu->port + 0x24);
240 tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
241 outl(tmp, emu->port + A_IOCFG);
242 }
243 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */
244 int size, n;
245
246 size = ARRAY_SIZE(spi_dac_init);
247 for (n = 0; n < size; n++)
248 snd_emu10k1_spi_write(emu, spi_dac_init[n]);
249
250 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10);
251 /* Enable GPIOs
252 * GPIO0: Unknown
253 * GPIO1: Speakers-enabled.
254 * GPIO2: Unknown
255 * GPIO3: Unknown
256 * GPIO4: IEC958 Output on.
257 * GPIO5: Unknown
258 * GPIO6: Unknown
259 * GPIO7: Unknown
260 */
261 outl(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
262 }
263 if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */
264 int size, n;
265
266 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f);
267 tmp = inl(emu->port + A_IOCFG);
268 outl(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */
269 tmp = inl(emu->port + A_IOCFG);
270 size = ARRAY_SIZE(i2c_adc_init);
271 for (n = 0; n < size; n++)
272 snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]);
273 for (n = 0; n < 4; n++) {
274 emu->i2c_capture_volume[n][0] = 0xcf;
275 emu->i2c_capture_volume[n][1] = 0xcf;
276 }
277 }
278
279
280 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
281 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
282 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
283
284 silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0);
285 for (ch = 0; ch < NUM_G; ch++) {
286 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
287 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
288 }
289
290 if (emu->card_capabilities->emu_model) {
291 outl(HCFG_AUTOMUTE_ASYNC |
292 HCFG_EMU32_SLAVE |
293 HCFG_AUDIOENABLE, emu->port + HCFG);
294 /*
295 * Hokay, setup HCFG
296 * Mute Disable Audio = 0
297 * Lock Tank Memory = 1
298 * Lock Sound Memory = 0
299 * Auto Mute = 1
300 */
301 } else if (emu->audigy) {
302 if (emu->revision == 4) /* audigy2 */
303 outl(HCFG_AUDIOENABLE |
304 HCFG_AC3ENABLE_CDSPDIF |
305 HCFG_AC3ENABLE_GPSPDIF |
306 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
307 else
308 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
309 /* FIXME: Remove all these emu->model and replace it with a card recognition parameter,
310 * e.g. card_capabilities->joystick */
311 } else if (emu->model == 0x20 ||
312 emu->model == 0xc400 ||
313 (emu->model == 0x21 && emu->revision < 6))
314 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
315 else
316 /* With on-chip joystick */
317 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
318
319 if (enable_ir) { /* enable IR for SB Live */
320 if (emu->card_capabilities->emu_model) {
321 ; /* Disable all access to A_IOCFG for the emu1010 */
322 } else if (emu->card_capabilities->i2c_adc) {
323 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
324 } else if (emu->audigy) {
325 unsigned int reg = inl(emu->port + A_IOCFG);
326 outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
327 udelay(500);
328 outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
329 udelay(100);
330 outl(reg, emu->port + A_IOCFG);
331 } else {
332 unsigned int reg = inl(emu->port + HCFG);
333 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
334 udelay(500);
335 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
336 udelay(100);
337 outl(reg, emu->port + HCFG);
338 }
339 }
340
341 if (emu->card_capabilities->emu_model) {
342 ; /* Disable all access to A_IOCFG for the emu1010 */
343 } else if (emu->card_capabilities->i2c_adc) {
344 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
345 } else if (emu->audigy) { /* enable analog output */
346 unsigned int reg = inl(emu->port + A_IOCFG);
347 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
348 }
349
350 if (emu->address_mode == 0) {
351 /* use 16M in 4G */
352 outl(inl(emu->port + HCFG) | HCFG_EXPANDED_MEM, emu->port + HCFG);
353 }
354
355 return 0;
356 }
357
358 static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu)
359 {
360 /*
361 * Enable the audio bit
362 */
363 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
364
365 /* Enable analog/digital outs on audigy */
366 if (emu->card_capabilities->emu_model) {
367 ; /* Disable all access to A_IOCFG for the emu1010 */
368 } else if (emu->card_capabilities->i2c_adc) {
369 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
370 } else if (emu->audigy) {
371 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
372
373 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
374 /* Unmute Analog now. Set GPO6 to 1 for Apollo.
375 * This has to be done after init ALice3 I2SOut beyond 48KHz.
376 * So, sequence is important. */
377 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
378 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
379 /* Unmute Analog now. */
380 outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
381 } else {
382 /* Disable routing from AC97 line out to Front speakers */
383 outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
384 }
385 }
386
387 #if 0
388 {
389 unsigned int tmp;
390 /* FIXME: the following routine disables LiveDrive-II !! */
391 /* TOSLink detection */
392 emu->tos_link = 0;
393 tmp = inl(emu->port + HCFG);
394 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
395 outl(tmp|0x800, emu->port + HCFG);
396 udelay(50);
397 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
398 emu->tos_link = 1;
399 outl(tmp, emu->port + HCFG);
400 }
401 }
402 }
403 #endif
404
405 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
406 }
407
408 int snd_emu10k1_done(struct snd_emu10k1 *emu)
409 {
410 int ch;
411
412 outl(0, emu->port + INTE);
413
414 /*
415 * Shutdown the chip
416 */
417 for (ch = 0; ch < NUM_G; ch++)
418 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
419 for (ch = 0; ch < NUM_G; ch++) {
420 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
421 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
422 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
423 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
424 }
425
426 /* reset recording buffers */
427 snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
428 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
429 snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
430 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
431 snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
432 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
433 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
434 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
435 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
436 if (emu->audigy)
437 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
438 else
439 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
440
441 /* disable channel interrupt */
442 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
443 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
444 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
445 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
446
447 /* disable audio and lock cache */
448 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
449 snd_emu10k1_ptr_write(emu, PTB, 0, 0);
450
451 return 0;
452 }
453
454 /*************************************************************************
455 * ECARD functional implementation
456 *************************************************************************/
457
458 /* In A1 Silicon, these bits are in the HC register */
459 #define HOOKN_BIT (1L << 12)
460 #define HANDN_BIT (1L << 11)
461 #define PULSEN_BIT (1L << 10)
462
463 #define EC_GDI1 (1 << 13)
464 #define EC_GDI0 (1 << 14)
465
466 #define EC_NUM_CONTROL_BITS 20
467
468 #define EC_AC3_DATA_SELN 0x0001L
469 #define EC_EE_DATA_SEL 0x0002L
470 #define EC_EE_CNTRL_SELN 0x0004L
471 #define EC_EECLK 0x0008L
472 #define EC_EECS 0x0010L
473 #define EC_EESDO 0x0020L
474 #define EC_TRIM_CSN 0x0040L
475 #define EC_TRIM_SCLK 0x0080L
476 #define EC_TRIM_SDATA 0x0100L
477 #define EC_TRIM_MUTEN 0x0200L
478 #define EC_ADCCAL 0x0400L
479 #define EC_ADCRSTN 0x0800L
480 #define EC_DACCAL 0x1000L
481 #define EC_DACMUTEN 0x2000L
482 #define EC_LEDN 0x4000L
483
484 #define EC_SPDIF0_SEL_SHIFT 15
485 #define EC_SPDIF1_SEL_SHIFT 17
486 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
487 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
488 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
489 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
490 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
491 * be incremented any time the EEPROM's
492 * format is changed. */
493
494 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
495
496 /* Addresses for special values stored in to EEPROM */
497 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
498 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
499 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
500
501 #define EC_LAST_PROMFILE_ADDR 0x2f
502
503 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
504 * can be up to 30 characters in length
505 * and is stored as a NULL-terminated
506 * ASCII string. Any unused bytes must be
507 * filled with zeros */
508 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
509
510
511 /* Most of this stuff is pretty self-evident. According to the hardware
512 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
513 * offset problem. Weird.
514 */
515 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
516 EC_TRIM_CSN)
517
518
519 #define EC_DEFAULT_ADC_GAIN 0xC4C4
520 #define EC_DEFAULT_SPDIF0_SEL 0x0
521 #define EC_DEFAULT_SPDIF1_SEL 0x4
522
523 /**************************************************************************
524 * @func Clock bits into the Ecard's control latch. The Ecard uses a
525 * control latch will is loaded bit-serially by toggling the Modem control
526 * lines from function 2 on the E8010. This function hides these details
527 * and presents the illusion that we are actually writing to a distinct
528 * register.
529 */
530
531 static void snd_emu10k1_ecard_write(struct snd_emu10k1 *emu, unsigned int value)
532 {
533 unsigned short count;
534 unsigned int data;
535 unsigned long hc_port;
536 unsigned int hc_value;
537
538 hc_port = emu->port + HCFG;
539 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
540 outl(hc_value, hc_port);
541
542 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
543
544 /* Set up the value */
545 data = ((value & 0x1) ? PULSEN_BIT : 0);
546 value >>= 1;
547
548 outl(hc_value | data, hc_port);
549
550 /* Clock the shift register */
551 outl(hc_value | data | HANDN_BIT, hc_port);
552 outl(hc_value | data, hc_port);
553 }
554
555 /* Latch the bits */
556 outl(hc_value | HOOKN_BIT, hc_port);
557 outl(hc_value, hc_port);
558 }
559
560 /**************************************************************************
561 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
562 * trim value consists of a 16bit value which is composed of two
563 * 8 bit gain/trim values, one for the left channel and one for the
564 * right channel. The following table maps from the Gain/Attenuation
565 * value in decibels into the corresponding bit pattern for a single
566 * channel.
567 */
568
569 static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 *emu,
570 unsigned short gain)
571 {
572 unsigned int bit;
573
574 /* Enable writing to the TRIM registers */
575 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
576
577 /* Do it again to insure that we meet hold time requirements */
578 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
579
580 for (bit = (1 << 15); bit; bit >>= 1) {
581 unsigned int value;
582
583 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
584
585 if (gain & bit)
586 value |= EC_TRIM_SDATA;
587
588 /* Clock the bit */
589 snd_emu10k1_ecard_write(emu, value);
590 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
591 snd_emu10k1_ecard_write(emu, value);
592 }
593
594 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
595 }
596
597 static int snd_emu10k1_ecard_init(struct snd_emu10k1 *emu)
598 {
599 unsigned int hc_value;
600
601 /* Set up the initial settings */
602 emu->ecard_ctrl = EC_RAW_RUN_MODE |
603 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
604 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
605
606 /* Step 0: Set the codec type in the hardware control register
607 * and enable audio output */
608 hc_value = inl(emu->port + HCFG);
609 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
610 inl(emu->port + HCFG);
611
612 /* Step 1: Turn off the led and deassert TRIM_CS */
613 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
614
615 /* Step 2: Calibrate the ADC and DAC */
616 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
617
618 /* Step 3: Wait for awhile; XXX We can't get away with this
619 * under a real operating system; we'll need to block and wait that
620 * way. */
621 snd_emu10k1_wait(emu, 48000);
622
623 /* Step 4: Switch off the DAC and ADC calibration. Note
624 * That ADC_CAL is actually an inverted signal, so we assert
625 * it here to stop calibration. */
626 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
627
628 /* Step 4: Switch into run mode */
629 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
630
631 /* Step 5: Set the analog input gain */
632 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
633
634 return 0;
635 }
636
637 static int snd_emu10k1_cardbus_init(struct snd_emu10k1 *emu)
638 {
639 unsigned long special_port;
640 unsigned int value;
641
642 /* Special initialisation routine
643 * before the rest of the IO-Ports become active.
644 */
645 special_port = emu->port + 0x38;
646 value = inl(special_port);
647 outl(0x00d00000, special_port);
648 value = inl(special_port);
649 outl(0x00d00001, special_port);
650 value = inl(special_port);
651 outl(0x00d0005f, special_port);
652 value = inl(special_port);
653 outl(0x00d0007f, special_port);
654 value = inl(special_port);
655 outl(0x0090007f, special_port);
656 value = inl(special_port);
657
658 snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */
659 /* Delay to give time for ADC chip to switch on. It needs 113ms */
660 msleep(200);
661 return 0;
662 }
663
664 static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
665 const struct firmware *fw_entry)
666 {
667 int n, i;
668 int reg;
669 int value;
670 unsigned int write_post;
671 unsigned long flags;
672
673 if (!fw_entry)
674 return -EIO;
675
676 /* The FPGA is a Xilinx Spartan IIE XC2S50E */
677 /* GPIO7 -> FPGA PGMN
678 * GPIO6 -> FPGA CCLK
679 * GPIO5 -> FPGA DIN
680 * FPGA CONFIG OFF -> FPGA PGMN
681 */
682 spin_lock_irqsave(&emu->emu_lock, flags);
683 outl(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */
684 write_post = inl(emu->port + A_IOCFG);
685 udelay(100);
686 outl(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */
687 write_post = inl(emu->port + A_IOCFG);
688 udelay(100); /* Allow FPGA memory to clean */
689 for (n = 0; n < fw_entry->size; n++) {
690 value = fw_entry->data[n];
691 for (i = 0; i < 8; i++) {
692 reg = 0x80;
693 if (value & 0x1)
694 reg = reg | 0x20;
695 value = value >> 1;
696 outl(reg, emu->port + A_IOCFG);
697 write_post = inl(emu->port + A_IOCFG);
698 outl(reg | 0x40, emu->port + A_IOCFG);
699 write_post = inl(emu->port + A_IOCFG);
700 }
701 }
702 /* After programming, set GPIO bit 4 high again. */
703 outl(0x10, emu->port + A_IOCFG);
704 write_post = inl(emu->port + A_IOCFG);
705 spin_unlock_irqrestore(&emu->emu_lock, flags);
706
707 return 0;
708 }
709
710 /* firmware file names, per model, init-fw and dock-fw (optional) */
711 static const char * const firmware_names[5][2] = {
712 [EMU_MODEL_EMU1010] = {
713 HANA_FILENAME, DOCK_FILENAME
714 },
715 [EMU_MODEL_EMU1010B] = {
716 EMU1010B_FILENAME, MICRO_DOCK_FILENAME
717 },
718 [EMU_MODEL_EMU1616] = {
719 EMU1010_NOTEBOOK_FILENAME, MICRO_DOCK_FILENAME
720 },
721 [EMU_MODEL_EMU0404] = {
722 EMU0404_FILENAME, NULL
723 },
724 };
725
726 static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu, int dock,
727 const struct firmware **fw)
728 {
729 const char *filename;
730 int err;
731
732 if (!*fw) {
733 filename = firmware_names[emu->card_capabilities->emu_model][dock];
734 if (!filename)
735 return 0;
736 err = request_firmware(fw, filename, &emu->pci->dev);
737 if (err)
738 return err;
739 }
740
741 return snd_emu1010_load_firmware_entry(emu, *fw);
742 }
743
744 static void emu1010_firmware_work(struct work_struct *work)
745 {
746 struct snd_emu10k1 *emu;
747 u32 tmp, tmp2, reg;
748 int err;
749
750 emu = container_of(work, struct snd_emu10k1,
751 emu1010.firmware_work.work);
752 if (emu->card->shutdown)
753 return;
754 #ifdef CONFIG_PM_SLEEP
755 if (emu->suspend)
756 return;
757 #endif
758 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */
759 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg); /* OPTIONS: Which cards are attached to the EMU */
760 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) {
761 /* Audio Dock attached */
762 /* Return to Audio Dock programming mode */
763 dev_info(emu->card->dev,
764 "emu1010: Loading Audio Dock Firmware\n");
765 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG,
766 EMU_HANA_FPGA_CONFIG_AUDIODOCK);
767 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw);
768 if (err < 0)
769 goto next;
770
771 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0);
772 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp);
773 dev_info(emu->card->dev,
774 "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp);
775 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
776 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp);
777 dev_info(emu->card->dev,
778 "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp);
779 if ((tmp & 0x1f) != 0x15) {
780 /* FPGA failed to be programmed */
781 dev_info(emu->card->dev,
782 "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n",
783 tmp);
784 goto next;
785 }
786 dev_info(emu->card->dev,
787 "emu1010: Audio Dock Firmware loaded\n");
788 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp);
789 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2);
790 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2);
791 /* Sync clocking between 1010 and Dock */
792 /* Allow DLL to settle */
793 msleep(10);
794 /* Unmute all. Default is muted after a firmware load */
795 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
796 } else if (!reg && emu->emu1010.last_reg) {
797 /* Audio Dock removed */
798 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n");
799 /* Unmute all */
800 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
801 }
802
803 next:
804 emu->emu1010.last_reg = reg;
805 if (!emu->card->shutdown)
806 schedule_delayed_work(&emu->emu1010.firmware_work,
807 msecs_to_jiffies(1000));
808 }
809
810 /*
811 * EMU-1010 - details found out from this driver, official MS Win drivers,
812 * testing the card:
813 *
814 * Audigy2 (aka Alice2):
815 * ---------------------
816 * * communication over PCI
817 * * conversion of 32-bit data coming over EMU32 links from HANA FPGA
818 * to 2 x 16-bit, using internal DSP instructions
819 * * slave mode, clock supplied by HANA
820 * * linked to HANA using:
821 * 32 x 32-bit serial EMU32 output channels
822 * 16 x EMU32 input channels
823 * (?) x I2S I/O channels (?)
824 *
825 * FPGA (aka HANA):
826 * ---------------
827 * * provides all (?) physical inputs and outputs of the card
828 * (ADC, DAC, SPDIF I/O, ADAT I/O, etc.)
829 * * provides clock signal for the card and Alice2
830 * * two crystals - for 44.1kHz and 48kHz multiples
831 * * provides internal routing of signal sources to signal destinations
832 * * inputs/outputs to Alice2 - see above
833 *
834 * Current status of the driver:
835 * ----------------------------
836 * * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz)
837 * * PCM device nb. 2:
838 * 16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops
839 * 16 x 32-bit capture - snd_emu10k1_capture_efx_ops
840 */
841 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
842 {
843 unsigned int i;
844 u32 tmp, tmp2, reg;
845 int err;
846
847 dev_info(emu->card->dev, "emu1010: Special config.\n");
848 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
849 * Lock Sound Memory Cache, Lock Tank Memory Cache,
850 * Mute all codecs.
851 */
852 outl(0x0005a00c, emu->port + HCFG);
853 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
854 * Lock Tank Memory Cache,
855 * Mute all codecs.
856 */
857 outl(0x0005a004, emu->port + HCFG);
858 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
859 * Mute all codecs.
860 */
861 outl(0x0005a000, emu->port + HCFG);
862 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
863 * Mute all codecs.
864 */
865 outl(0x0005a000, emu->port + HCFG);
866
867 /* Disable 48Volt power to Audio Dock */
868 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
869
870 /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */
871 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg);
872 dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg);
873 if ((reg & 0x3f) == 0x15) {
874 /* FPGA netlist already present so clear it */
875 /* Return to programming mode */
876
877 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02);
878 }
879 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg);
880 dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg);
881 if ((reg & 0x3f) == 0x15) {
882 /* FPGA failed to return to programming mode */
883 dev_info(emu->card->dev,
884 "emu1010: FPGA failed to return to programming mode\n");
885 return -ENODEV;
886 }
887 dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg);
888
889 err = snd_emu1010_load_firmware(emu, 0, &emu->firmware);
890 if (err < 0) {
891 dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n");
892 return err;
893 }
894
895 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
896 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg);
897 if ((reg & 0x3f) != 0x15) {
898 /* FPGA failed to be programmed */
899 dev_info(emu->card->dev,
900 "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n",
901 reg);
902 return -ENODEV;
903 }
904
905 dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n");
906 snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp);
907 snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2);
908 dev_info(emu->card->dev, "emu1010: Hana version: %u.%u\n", tmp, tmp2);
909 /* Enable 48Volt power to Audio Dock */
910 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON);
911
912 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg);
913 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
914 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg);
915 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
916 snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp);
917 /* Optical -> ADAT I/O */
918 /* 0 : SPDIF
919 * 1 : ADAT
920 */
921 emu->emu1010.optical_in = 1; /* IN_ADAT */
922 emu->emu1010.optical_out = 1; /* IN_ADAT */
923 tmp = 0;
924 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
925 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
926 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
927 snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp);
928 /* Set no attenuation on Audio Dock pads. */
929 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00);
930 emu->emu1010.adc_pads = 0x00;
931 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
932 /* Unmute Audio dock DACs, Headphone source DAC-4. */
933 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
934 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
935 snd_emu1010_fpga_read(emu, EMU_HANA_DAC_PADS, &tmp);
936 /* DAC PADs. */
937 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f);
938 emu->emu1010.dac_pads = 0x0f;
939 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
940 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
941 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
942 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */
943 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10);
944 /* MIDI routing */
945 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19);
946 /* Unknown. */
947 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c);
948 /* IRQ Enable: All on */
949 /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */
950 /* IRQ Enable: All off */
951 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00);
952
953 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg);
954 dev_info(emu->card->dev, "emu1010: Card options3 = 0x%x\n", reg);
955 /* Default WCLK set to 48kHz. */
956 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00);
957 /* Word Clock source, Internal 48kHz x1 */
958 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
959 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
960 /* Audio Dock LEDs. */
961 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
962
963 #if 0
964 /* For 96kHz */
965 snd_emu1010_fpga_link_dst_src_write(emu,
966 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
967 snd_emu1010_fpga_link_dst_src_write(emu,
968 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
969 snd_emu1010_fpga_link_dst_src_write(emu,
970 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2);
971 snd_emu1010_fpga_link_dst_src_write(emu,
972 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2);
973 #endif
974 #if 0
975 /* For 192kHz */
976 snd_emu1010_fpga_link_dst_src_write(emu,
977 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
978 snd_emu1010_fpga_link_dst_src_write(emu,
979 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
980 snd_emu1010_fpga_link_dst_src_write(emu,
981 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
982 snd_emu1010_fpga_link_dst_src_write(emu,
983 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2);
984 snd_emu1010_fpga_link_dst_src_write(emu,
985 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3);
986 snd_emu1010_fpga_link_dst_src_write(emu,
987 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3);
988 snd_emu1010_fpga_link_dst_src_write(emu,
989 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4);
990 snd_emu1010_fpga_link_dst_src_write(emu,
991 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4);
992 #endif
993 #if 1
994 /* For 48kHz */
995 snd_emu1010_fpga_link_dst_src_write(emu,
996 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1);
997 snd_emu1010_fpga_link_dst_src_write(emu,
998 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1);
999 snd_emu1010_fpga_link_dst_src_write(emu,
1000 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
1001 snd_emu1010_fpga_link_dst_src_write(emu,
1002 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2);
1003 snd_emu1010_fpga_link_dst_src_write(emu,
1004 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1);
1005 snd_emu1010_fpga_link_dst_src_write(emu,
1006 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1);
1007 snd_emu1010_fpga_link_dst_src_write(emu,
1008 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1);
1009 snd_emu1010_fpga_link_dst_src_write(emu,
1010 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1);
1011 /* Pavel Hofman - setting defaults for 8 more capture channels
1012 * Defaults only, users will set their own values anyways, let's
1013 * just copy/paste.
1014 */
1015
1016 snd_emu1010_fpga_link_dst_src_write(emu,
1017 EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1);
1018 snd_emu1010_fpga_link_dst_src_write(emu,
1019 EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1);
1020 snd_emu1010_fpga_link_dst_src_write(emu,
1021 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2);
1022 snd_emu1010_fpga_link_dst_src_write(emu,
1023 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2);
1024 snd_emu1010_fpga_link_dst_src_write(emu,
1025 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1);
1026 snd_emu1010_fpga_link_dst_src_write(emu,
1027 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1);
1028 snd_emu1010_fpga_link_dst_src_write(emu,
1029 EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1);
1030 snd_emu1010_fpga_link_dst_src_write(emu,
1031 EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1);
1032 #endif
1033 #if 0
1034 /* Original */
1035 snd_emu1010_fpga_link_dst_src_write(emu,
1036 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT);
1037 snd_emu1010_fpga_link_dst_src_write(emu,
1038 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1);
1039 snd_emu1010_fpga_link_dst_src_write(emu,
1040 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2);
1041 snd_emu1010_fpga_link_dst_src_write(emu,
1042 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3);
1043 snd_emu1010_fpga_link_dst_src_write(emu,
1044 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4);
1045 snd_emu1010_fpga_link_dst_src_write(emu,
1046 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5);
1047 snd_emu1010_fpga_link_dst_src_write(emu,
1048 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6);
1049 snd_emu1010_fpga_link_dst_src_write(emu,
1050 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7);
1051 snd_emu1010_fpga_link_dst_src_write(emu,
1052 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1);
1053 snd_emu1010_fpga_link_dst_src_write(emu,
1054 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1);
1055 snd_emu1010_fpga_link_dst_src_write(emu,
1056 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2);
1057 snd_emu1010_fpga_link_dst_src_write(emu,
1058 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2);
1059 #endif
1060 for (i = 0; i < 0x20; i++) {
1061 /* AudioDock Elink <- Silence */
1062 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE);
1063 }
1064 for (i = 0; i < 4; i++) {
1065 /* Hana SPDIF Out <- Silence */
1066 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE);
1067 }
1068 for (i = 0; i < 7; i++) {
1069 /* Hamoa DAC <- Silence */
1070 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE);
1071 }
1072 for (i = 0; i < 7; i++) {
1073 /* Hana ADAT Out <- Silence */
1074 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE);
1075 }
1076 snd_emu1010_fpga_link_dst_src_write(emu,
1077 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1);
1078 snd_emu1010_fpga_link_dst_src_write(emu,
1079 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1);
1080 snd_emu1010_fpga_link_dst_src_write(emu,
1081 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1);
1082 snd_emu1010_fpga_link_dst_src_write(emu,
1083 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1);
1084 snd_emu1010_fpga_link_dst_src_write(emu,
1085 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1);
1086 snd_emu1010_fpga_link_dst_src_write(emu,
1087 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1);
1088 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */
1089
1090 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
1091
1092 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
1093 * Lock Sound Memory Cache, Lock Tank Memory Cache,
1094 * Mute all codecs.
1095 */
1096 outl(0x0000a000, emu->port + HCFG);
1097 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
1098 * Lock Sound Memory Cache, Lock Tank Memory Cache,
1099 * Un-Mute all codecs.
1100 */
1101 outl(0x0000a001, emu->port + HCFG);
1102
1103 /* Initial boot complete. Now patches */
1104
1105 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
1106 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
1107 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
1108 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
1109 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
1110 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
1111 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); /* SPDIF Format spdif (or 0x11 for aes/ebu) */
1112
1113 #if 0
1114 snd_emu1010_fpga_link_dst_src_write(emu,
1115 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */
1116 snd_emu1010_fpga_link_dst_src_write(emu,
1117 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */
1118 snd_emu1010_fpga_link_dst_src_write(emu,
1119 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */
1120 snd_emu1010_fpga_link_dst_src_write(emu,
1121 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */
1122 #endif
1123 /* Default outputs */
1124 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) {
1125 /* 1616(M) cardbus default outputs */
1126 /* ALICE2 bus 0xa0 */
1127 snd_emu1010_fpga_link_dst_src_write(emu,
1128 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1129 emu->emu1010.output_source[0] = 17;
1130 snd_emu1010_fpga_link_dst_src_write(emu,
1131 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1132 emu->emu1010.output_source[1] = 18;
1133 snd_emu1010_fpga_link_dst_src_write(emu,
1134 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
1135 emu->emu1010.output_source[2] = 19;
1136 snd_emu1010_fpga_link_dst_src_write(emu,
1137 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
1138 emu->emu1010.output_source[3] = 20;
1139 snd_emu1010_fpga_link_dst_src_write(emu,
1140 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
1141 emu->emu1010.output_source[4] = 21;
1142 snd_emu1010_fpga_link_dst_src_write(emu,
1143 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
1144 emu->emu1010.output_source[5] = 22;
1145 /* ALICE2 bus 0xa0 */
1146 snd_emu1010_fpga_link_dst_src_write(emu,
1147 EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0);
1148 emu->emu1010.output_source[16] = 17;
1149 snd_emu1010_fpga_link_dst_src_write(emu,
1150 EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1);
1151 emu->emu1010.output_source[17] = 18;
1152 } else {
1153 /* ALICE2 bus 0xa0 */
1154 snd_emu1010_fpga_link_dst_src_write(emu,
1155 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1156 emu->emu1010.output_source[0] = 21;
1157 snd_emu1010_fpga_link_dst_src_write(emu,
1158 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1159 emu->emu1010.output_source[1] = 22;
1160 snd_emu1010_fpga_link_dst_src_write(emu,
1161 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
1162 emu->emu1010.output_source[2] = 23;
1163 snd_emu1010_fpga_link_dst_src_write(emu,
1164 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
1165 emu->emu1010.output_source[3] = 24;
1166 snd_emu1010_fpga_link_dst_src_write(emu,
1167 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
1168 emu->emu1010.output_source[4] = 25;
1169 snd_emu1010_fpga_link_dst_src_write(emu,
1170 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
1171 emu->emu1010.output_source[5] = 26;
1172 snd_emu1010_fpga_link_dst_src_write(emu,
1173 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6);
1174 emu->emu1010.output_source[6] = 27;
1175 snd_emu1010_fpga_link_dst_src_write(emu,
1176 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7);
1177 emu->emu1010.output_source[7] = 28;
1178 /* ALICE2 bus 0xa0 */
1179 snd_emu1010_fpga_link_dst_src_write(emu,
1180 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1181 emu->emu1010.output_source[8] = 21;
1182 snd_emu1010_fpga_link_dst_src_write(emu,
1183 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1184 emu->emu1010.output_source[9] = 22;
1185 /* ALICE2 bus 0xa0 */
1186 snd_emu1010_fpga_link_dst_src_write(emu,
1187 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1188 emu->emu1010.output_source[10] = 21;
1189 snd_emu1010_fpga_link_dst_src_write(emu,
1190 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1191 emu->emu1010.output_source[11] = 22;
1192 /* ALICE2 bus 0xa0 */
1193 snd_emu1010_fpga_link_dst_src_write(emu,
1194 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1195 emu->emu1010.output_source[12] = 21;
1196 snd_emu1010_fpga_link_dst_src_write(emu,
1197 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1198 emu->emu1010.output_source[13] = 22;
1199 /* ALICE2 bus 0xa0 */
1200 snd_emu1010_fpga_link_dst_src_write(emu,
1201 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1202 emu->emu1010.output_source[14] = 21;
1203 snd_emu1010_fpga_link_dst_src_write(emu,
1204 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1205 emu->emu1010.output_source[15] = 22;
1206 /* ALICE2 bus 0xa0 */
1207 snd_emu1010_fpga_link_dst_src_write(emu,
1208 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0);
1209 emu->emu1010.output_source[16] = 21;
1210 snd_emu1010_fpga_link_dst_src_write(emu,
1211 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1);
1212 emu->emu1010.output_source[17] = 22;
1213 snd_emu1010_fpga_link_dst_src_write(emu,
1214 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2);
1215 emu->emu1010.output_source[18] = 23;
1216 snd_emu1010_fpga_link_dst_src_write(emu,
1217 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3);
1218 emu->emu1010.output_source[19] = 24;
1219 snd_emu1010_fpga_link_dst_src_write(emu,
1220 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4);
1221 emu->emu1010.output_source[20] = 25;
1222 snd_emu1010_fpga_link_dst_src_write(emu,
1223 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5);
1224 emu->emu1010.output_source[21] = 26;
1225 snd_emu1010_fpga_link_dst_src_write(emu,
1226 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6);
1227 emu->emu1010.output_source[22] = 27;
1228 snd_emu1010_fpga_link_dst_src_write(emu,
1229 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7);
1230 emu->emu1010.output_source[23] = 28;
1231 }
1232 /* TEMP: Select SPDIF in/out */
1233 /* snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); */ /* Output spdif */
1234
1235 /* TEMP: Select 48kHz SPDIF out */
1236 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */
1237 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */
1238 /* Word Clock source, Internal 48kHz x1 */
1239 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
1240 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
1241 emu->emu1010.internal_clock = 1; /* 48000 */
1242 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); /* Set LEDs on Audio Dock */
1243 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */
1244 /* snd_emu1010_fpga_write(emu, 0x7, 0x0); */ /* Mute all */
1245 /* snd_emu1010_fpga_write(emu, 0x7, 0x1); */ /* Unmute all */
1246 /* snd_emu1010_fpga_write(emu, 0xe, 0x12); */ /* Set LEDs on Audio Dock */
1247
1248 return 0;
1249 }
1250 /*
1251 * Create the EMU10K1 instance
1252 */
1253
1254 #ifdef CONFIG_PM_SLEEP
1255 static int alloc_pm_buffer(struct snd_emu10k1 *emu);
1256 static void free_pm_buffer(struct snd_emu10k1 *emu);
1257 #endif
1258
1259 static int snd_emu10k1_free(struct snd_emu10k1 *emu)
1260 {
1261 if (emu->port) { /* avoid access to already used hardware */
1262 snd_emu10k1_fx8010_tram_setup(emu, 0);
1263 snd_emu10k1_done(emu);
1264 snd_emu10k1_free_efx(emu);
1265 }
1266 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) {
1267 /* Disable 48Volt power to Audio Dock */
1268 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
1269 }
1270 cancel_delayed_work_sync(&emu->emu1010.firmware_work);
1271 release_firmware(emu->firmware);
1272 release_firmware(emu->dock_fw);
1273 if (emu->irq >= 0)
1274 free_irq(emu->irq, emu);
1275 /* remove reserved page */
1276 if (emu->reserved_page) {
1277 snd_emu10k1_synth_free(emu,
1278 (struct snd_util_memblk *)emu->reserved_page);
1279 emu->reserved_page = NULL;
1280 }
1281 snd_util_memhdr_free(emu->memhdr);
1282 if (emu->silent_page.area)
1283 snd_dma_free_pages(&emu->silent_page);
1284 if (emu->ptb_pages.area)
1285 snd_dma_free_pages(&emu->ptb_pages);
1286 vfree(emu->page_ptr_table);
1287 vfree(emu->page_addr_table);
1288 #ifdef CONFIG_PM_SLEEP
1289 free_pm_buffer(emu);
1290 #endif
1291 if (emu->port)
1292 pci_release_regions(emu->pci);
1293 if (emu->card_capabilities->ca0151_chip) /* P16V */
1294 snd_p16v_free(emu);
1295 pci_disable_device(emu->pci);
1296 kfree(emu);
1297 return 0;
1298 }
1299
1300 static int snd_emu10k1_dev_free(struct snd_device *device)
1301 {
1302 struct snd_emu10k1 *emu = device->device_data;
1303 return snd_emu10k1_free(emu);
1304 }
1305
1306 static struct snd_emu_chip_details emu_chip_details[] = {
1307 /* Audigy 5/Rx SB1550 */
1308 /* Tested by michael@gernoth.net 28 Mar 2015 */
1309 /* DSP: CA10300-IAT LF
1310 * DAC: Cirrus Logic CS4382-KQZ
1311 * ADC: Philips 1361T
1312 * AC97: Sigmatel STAC9750
1313 * CA0151: None
1314 */
1315 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10241102,
1316 .driver = "Audigy2", .name = "SB Audigy 5/Rx [SB1550]",
1317 .id = "Audigy2",
1318 .emu10k2_chip = 1,
1319 .ca0108_chip = 1,
1320 .spk71 = 1,
1321 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1322 .ac97_chip = 1},
1323 /* Audigy4 (Not PRO) SB0610 */
1324 /* Tested by James@superbug.co.uk 4th April 2006 */
1325 /* A_IOCFG bits
1326 * Output
1327 * 0: ?
1328 * 1: ?
1329 * 2: ?
1330 * 3: 0 - Digital Out, 1 - Line in
1331 * 4: ?
1332 * 5: ?
1333 * 6: ?
1334 * 7: ?
1335 * Input
1336 * 8: ?
1337 * 9: ?
1338 * A: Green jack sense (Front)
1339 * B: ?
1340 * C: Black jack sense (Rear/Side Right)
1341 * D: Yellow jack sense (Center/LFE/Side Left)
1342 * E: ?
1343 * F: ?
1344 *
1345 * Digital Out/Line in switch using A_IOCFG bit 3 (0x08)
1346 * 0 - Digital Out
1347 * 1 - Line in
1348 */
1349 /* Mic input not tested.
1350 * Analog CD input not tested
1351 * Digital Out not tested.
1352 * Line in working.
1353 * Audio output 5.1 working. Side outputs not working.
1354 */
1355 /* DSP: CA10300-IAT LF
1356 * DAC: Cirrus Logic CS4382-KQZ
1357 * ADC: Philips 1361T
1358 * AC97: Sigmatel STAC9750
1359 * CA0151: None
1360 */
1361 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102,
1362 .driver = "Audigy2", .name = "SB Audigy 4 [SB0610]",
1363 .id = "Audigy2",
1364 .emu10k2_chip = 1,
1365 .ca0108_chip = 1,
1366 .spk71 = 1,
1367 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1368 .ac97_chip = 1} ,
1369 /* Audigy 2 Value AC3 out does not work yet.
1370 * Need to find out how to turn off interpolators.
1371 */
1372 /* Tested by James@superbug.co.uk 3rd July 2005 */
1373 /* DSP: CA0108-IAT
1374 * DAC: CS4382-KQ
1375 * ADC: Philips 1361T
1376 * AC97: STAC9750
1377 * CA0151: None
1378 */
1379 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
1380 .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]",
1381 .id = "Audigy2",
1382 .emu10k2_chip = 1,
1383 .ca0108_chip = 1,
1384 .spk71 = 1,
1385 .ac97_chip = 1} ,
1386 /* Audigy 2 ZS Notebook Cardbus card.*/
1387 /* Tested by James@superbug.co.uk 6th November 2006 */
1388 /* Audio output 7.1/Headphones working.
1389 * Digital output working. (AC3 not checked, only PCM)
1390 * Audio Mic/Line inputs working.
1391 * Digital input not tested.
1392 */
1393 /* DSP: Tina2
1394 * DAC: Wolfson WM8768/WM8568
1395 * ADC: Wolfson WM8775
1396 * AC97: None
1397 * CA0151: None
1398 */
1399 /* Tested by James@superbug.co.uk 4th April 2006 */
1400 /* A_IOCFG bits
1401 * Output
1402 * 0: Not Used
1403 * 1: 0 = Mute all the 7.1 channel out. 1 = unmute.
1404 * 2: Analog input 0 = line in, 1 = mic in
1405 * 3: Not Used
1406 * 4: Digital output 0 = off, 1 = on.
1407 * 5: Not Used
1408 * 6: Not Used
1409 * 7: Not Used
1410 * Input
1411 * All bits 1 (0x3fxx) means nothing plugged in.
1412 * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing.
1413 * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing.
1414 * C-D: 2 = Front/Rear/etc, 3 = nothing.
1415 * E-F: Always 0
1416 *
1417 */
1418 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102,
1419 .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]",
1420 .id = "Audigy2",
1421 .emu10k2_chip = 1,
1422 .ca0108_chip = 1,
1423 .ca_cardbus_chip = 1,
1424 .spi_dac = 1,
1425 .i2c_adc = 1,
1426 .spk71 = 1} ,
1427 /* Tested by James@superbug.co.uk 4th Nov 2007. */
1428 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102,
1429 .driver = "Audigy2", .name = "E-mu 1010 Notebook [MAEM8950]",
1430 .id = "EMU1010",
1431 .emu10k2_chip = 1,
1432 .ca0108_chip = 1,
1433 .ca_cardbus_chip = 1,
1434 .spk71 = 1 ,
1435 .emu_model = EMU_MODEL_EMU1616},
1436 /* Tested by James@superbug.co.uk 4th Nov 2007. */
1437 /* This is MAEM8960, 0202 is MAEM 8980 */
1438 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102,
1439 .driver = "Audigy2", .name = "E-mu 1010b PCI [MAEM8960]",
1440 .id = "EMU1010",
1441 .emu10k2_chip = 1,
1442 .ca0108_chip = 1,
1443 .spk71 = 1,
1444 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */
1445 /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */
1446 /* This is MAEM8986, 0202 is MAEM8980 */
1447 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102,
1448 .driver = "Audigy2", .name = "E-mu 1010 PCIe [MAEM8986]",
1449 .id = "EMU1010",
1450 .emu10k2_chip = 1,
1451 .ca0108_chip = 1,
1452 .spk71 = 1,
1453 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */
1454 /* Tested by James@superbug.co.uk 8th July 2005. */
1455 /* This is MAEM8810, 0202 is MAEM8820 */
1456 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
1457 .driver = "Audigy2", .name = "E-mu 1010 [MAEM8810]",
1458 .id = "EMU1010",
1459 .emu10k2_chip = 1,
1460 .ca0102_chip = 1,
1461 .spk71 = 1,
1462 .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */
1463 /* EMU0404b */
1464 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102,
1465 .driver = "Audigy2", .name = "E-mu 0404b PCI [MAEM8852]",
1466 .id = "EMU0404",
1467 .emu10k2_chip = 1,
1468 .ca0108_chip = 1,
1469 .spk71 = 1,
1470 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */
1471 /* Tested by James@superbug.co.uk 20-3-2007. */
1472 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102,
1473 .driver = "Audigy2", .name = "E-mu 0404 [MAEM8850]",
1474 .id = "EMU0404",
1475 .emu10k2_chip = 1,
1476 .ca0102_chip = 1,
1477 .spk71 = 1,
1478 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */
1479 /* EMU0404 PCIe */
1480 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102,
1481 .driver = "Audigy2", .name = "E-mu 0404 PCIe [MAEM8984]",
1482 .id = "EMU0404",
1483 .emu10k2_chip = 1,
1484 .ca0108_chip = 1,
1485 .spk71 = 1,
1486 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */
1487 /* Note that all E-mu cards require kernel 2.6 or newer. */
1488 {.vendor = 0x1102, .device = 0x0008,
1489 .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]",
1490 .id = "Audigy2",
1491 .emu10k2_chip = 1,
1492 .ca0108_chip = 1,
1493 .ac97_chip = 1} ,
1494 /* Tested by James@superbug.co.uk 3rd July 2005 */
1495 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
1496 .driver = "Audigy2", .name = "SB Audigy 4 PRO [SB0380]",
1497 .id = "Audigy2",
1498 .emu10k2_chip = 1,
1499 .ca0102_chip = 1,
1500 .ca0151_chip = 1,
1501 .spk71 = 1,
1502 .spdif_bug = 1,
1503 .ac97_chip = 1} ,
1504 /* Tested by shane-alsa@cm.nu 5th Nov 2005 */
1505 /* The 0x20061102 does have SB0350 written on it
1506 * Just like 0x20021102
1507 */
1508 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102,
1509 .driver = "Audigy2", .name = "SB Audigy 2 [SB0350b]",
1510 .id = "Audigy2",
1511 .emu10k2_chip = 1,
1512 .ca0102_chip = 1,
1513 .ca0151_chip = 1,
1514 .spk71 = 1,
1515 .spdif_bug = 1,
1516 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1517 .ac97_chip = 1} ,
1518 /* 0x20051102 also has SB0350 written on it, treated as Audigy 2 ZS by
1519 Creative's Windows driver */
1520 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20051102,
1521 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350a]",
1522 .id = "Audigy2",
1523 .emu10k2_chip = 1,
1524 .ca0102_chip = 1,
1525 .ca0151_chip = 1,
1526 .spk71 = 1,
1527 .spdif_bug = 1,
1528 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1529 .ac97_chip = 1} ,
1530 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102,
1531 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350]",
1532 .id = "Audigy2",
1533 .emu10k2_chip = 1,
1534 .ca0102_chip = 1,
1535 .ca0151_chip = 1,
1536 .spk71 = 1,
1537 .spdif_bug = 1,
1538 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1539 .ac97_chip = 1} ,
1540 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102,
1541 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0360]",
1542 .id = "Audigy2",
1543 .emu10k2_chip = 1,
1544 .ca0102_chip = 1,
1545 .ca0151_chip = 1,
1546 .spk71 = 1,
1547 .spdif_bug = 1,
1548 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1549 .ac97_chip = 1} ,
1550 /* Audigy 2 */
1551 /* Tested by James@superbug.co.uk 3rd July 2005 */
1552 /* DSP: CA0102-IAT
1553 * DAC: CS4382-KQ
1554 * ADC: Philips 1361T
1555 * AC97: STAC9721
1556 * CA0151: Yes
1557 */
1558 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102,
1559 .driver = "Audigy2", .name = "SB Audigy 2 [SB0240]",
1560 .id = "Audigy2",
1561 .emu10k2_chip = 1,
1562 .ca0102_chip = 1,
1563 .ca0151_chip = 1,
1564 .spk71 = 1,
1565 .spdif_bug = 1,
1566 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1567 .ac97_chip = 1} ,
1568 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
1569 .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]",
1570 .id = "Audigy2",
1571 .emu10k2_chip = 1,
1572 .ca0102_chip = 1,
1573 .ca0151_chip = 1,
1574 .spk71 = 1,
1575 .spdif_bug = 1} ,
1576 /* Dell OEM/Creative Labs Audigy 2 ZS */
1577 /* See ALSA bug#1365 */
1578 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102,
1579 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0353]",
1580 .id = "Audigy2",
1581 .emu10k2_chip = 1,
1582 .ca0102_chip = 1,
1583 .ca0151_chip = 1,
1584 .spk71 = 1,
1585 .spdif_bug = 1,
1586 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1587 .ac97_chip = 1} ,
1588 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
1589 .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]",
1590 .id = "Audigy2",
1591 .emu10k2_chip = 1,
1592 .ca0102_chip = 1,
1593 .ca0151_chip = 1,
1594 .spk71 = 1,
1595 .spdif_bug = 1,
1596 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1597 .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */
1598 .ac97_chip = 1} ,
1599 {.vendor = 0x1102, .device = 0x0004, .revision = 0x04,
1600 .driver = "Audigy2", .name = "SB Audigy 2 [Unknown]",
1601 .id = "Audigy2",
1602 .emu10k2_chip = 1,
1603 .ca0102_chip = 1,
1604 .ca0151_chip = 1,
1605 .spdif_bug = 1,
1606 .ac97_chip = 1} ,
1607 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
1608 .driver = "Audigy", .name = "SB Audigy 1 [SB0092]",
1609 .id = "Audigy",
1610 .emu10k2_chip = 1,
1611 .ca0102_chip = 1,
1612 .ac97_chip = 1} ,
1613 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102,
1614 .driver = "Audigy", .name = "SB Audigy 1 ES [SB0160]",
1615 .id = "Audigy",
1616 .emu10k2_chip = 1,
1617 .ca0102_chip = 1,
1618 .spdif_bug = 1,
1619 .ac97_chip = 1} ,
1620 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102,
1621 .driver = "Audigy", .name = "SB Audigy 1 [SB0090]",
1622 .id = "Audigy",
1623 .emu10k2_chip = 1,
1624 .ca0102_chip = 1,
1625 .ac97_chip = 1} ,
1626 {.vendor = 0x1102, .device = 0x0004,
1627 .driver = "Audigy", .name = "Audigy 1 [Unknown]",
1628 .id = "Audigy",
1629 .emu10k2_chip = 1,
1630 .ca0102_chip = 1,
1631 .ac97_chip = 1} ,
1632 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102,
1633 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
1634 .id = "Live",
1635 .emu10k1_chip = 1,
1636 .ac97_chip = 1,
1637 .sblive51 = 1} ,
1638 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806b1102,
1639 .driver = "EMU10K1", .name = "SB Live! [SB0105]",
1640 .id = "Live",
1641 .emu10k1_chip = 1,
1642 .ac97_chip = 1,
1643 .sblive51 = 1} ,
1644 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806a1102,
1645 .driver = "EMU10K1", .name = "SB Live! Value [SB0103]",
1646 .id = "Live",
1647 .emu10k1_chip = 1,
1648 .ac97_chip = 1,
1649 .sblive51 = 1} ,
1650 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
1651 .driver = "EMU10K1", .name = "SB Live! Value [SB0101]",
1652 .id = "Live",
1653 .emu10k1_chip = 1,
1654 .ac97_chip = 1,
1655 .sblive51 = 1} ,
1656 /* Tested by ALSA bug#1680 26th December 2005 */
1657 /* note: It really has SB0220 written on the card, */
1658 /* but it's SB0228 according to kx.inf */
1659 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102,
1660 .driver = "EMU10K1", .name = "SB Live! 5.1 Dell OEM [SB0228]",
1661 .id = "Live",
1662 .emu10k1_chip = 1,
1663 .ac97_chip = 1,
1664 .sblive51 = 1} ,
1665 /* Tested by Thomas Zehetbauer 27th Aug 2005 */
1666 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102,
1667 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
1668 .id = "Live",
1669 .emu10k1_chip = 1,
1670 .ac97_chip = 1,
1671 .sblive51 = 1} ,
1672 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
1673 .driver = "EMU10K1", .name = "SB Live! 5.1",
1674 .id = "Live",
1675 .emu10k1_chip = 1,
1676 .ac97_chip = 1,
1677 .sblive51 = 1} ,
1678 /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */
1679 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
1680 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0060]",
1681 .id = "Live",
1682 .emu10k1_chip = 1,
1683 .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum
1684 * share the same IDs!
1685 */
1686 .sblive51 = 1} ,
1687 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
1688 .driver = "EMU10K1", .name = "SB Live! Value [CT4850]",
1689 .id = "Live",
1690 .emu10k1_chip = 1,
1691 .ac97_chip = 1,
1692 .sblive51 = 1} ,
1693 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
1694 .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]",
1695 .id = "Live",
1696 .emu10k1_chip = 1,
1697 .ac97_chip = 1} ,
1698 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
1699 .driver = "EMU10K1", .name = "SB Live! Value [CT4871]",
1700 .id = "Live",
1701 .emu10k1_chip = 1,
1702 .ac97_chip = 1,
1703 .sblive51 = 1} ,
1704 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102,
1705 .driver = "EMU10K1", .name = "SB Live! Value [CT4831]",
1706 .id = "Live",
1707 .emu10k1_chip = 1,
1708 .ac97_chip = 1,
1709 .sblive51 = 1} ,
1710 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
1711 .driver = "EMU10K1", .name = "SB Live! Value [CT4870]",
1712 .id = "Live",
1713 .emu10k1_chip = 1,
1714 .ac97_chip = 1,
1715 .sblive51 = 1} ,
1716 /* Tested by James@superbug.co.uk 3rd July 2005 */
1717 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
1718 .driver = "EMU10K1", .name = "SB Live! Value [CT4832]",
1719 .id = "Live",
1720 .emu10k1_chip = 1,
1721 .ac97_chip = 1,
1722 .sblive51 = 1} ,
1723 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
1724 .driver = "EMU10K1", .name = "SB Live! Value [CT4830]",
1725 .id = "Live",
1726 .emu10k1_chip = 1,
1727 .ac97_chip = 1,
1728 .sblive51 = 1} ,
1729 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
1730 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]",
1731 .id = "Live",
1732 .emu10k1_chip = 1,
1733 .ac97_chip = 1,
1734 .sblive51 = 1} ,
1735 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
1736 .driver = "EMU10K1", .name = "SB Live! Value [CT4780]",
1737 .id = "Live",
1738 .emu10k1_chip = 1,
1739 .ac97_chip = 1,
1740 .sblive51 = 1} ,
1741 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
1742 .driver = "EMU10K1", .name = "E-mu APS [PC545]",
1743 .id = "APS",
1744 .emu10k1_chip = 1,
1745 .ecard = 1} ,
1746 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
1747 .driver = "EMU10K1", .name = "SB Live! [CT4620]",
1748 .id = "Live",
1749 .emu10k1_chip = 1,
1750 .ac97_chip = 1,
1751 .sblive51 = 1} ,
1752 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
1753 .driver = "EMU10K1", .name = "SB Live! Value [CT4670]",
1754 .id = "Live",
1755 .emu10k1_chip = 1,
1756 .ac97_chip = 1,
1757 .sblive51 = 1} ,
1758 {.vendor = 0x1102, .device = 0x0002,
1759 .driver = "EMU10K1", .name = "SB Live! [Unknown]",
1760 .id = "Live",
1761 .emu10k1_chip = 1,
1762 .ac97_chip = 1,
1763 .sblive51 = 1} ,
1764 { } /* terminator */
1765 };
1766
1767 int snd_emu10k1_create(struct snd_card *card,
1768 struct pci_dev *pci,
1769 unsigned short extin_mask,
1770 unsigned short extout_mask,
1771 long max_cache_bytes,
1772 int enable_ir,
1773 uint subsystem,
1774 struct snd_emu10k1 **remu)
1775 {
1776 struct snd_emu10k1 *emu;
1777 int idx, err;
1778 int is_audigy;
1779 unsigned int silent_page;
1780 const struct snd_emu_chip_details *c;
1781 static struct snd_device_ops ops = {
1782 .dev_free = snd_emu10k1_dev_free,
1783 };
1784
1785 *remu = NULL;
1786
1787 /* enable PCI device */
1788 err = pci_enable_device(pci);
1789 if (err < 0)
1790 return err;
1791
1792 emu = kzalloc(sizeof(*emu), GFP_KERNEL);
1793 if (emu == NULL) {
1794 pci_disable_device(pci);
1795 return -ENOMEM;
1796 }
1797 emu->card = card;
1798 spin_lock_init(&emu->reg_lock);
1799 spin_lock_init(&emu->emu_lock);
1800 spin_lock_init(&emu->spi_lock);
1801 spin_lock_init(&emu->i2c_lock);
1802 spin_lock_init(&emu->voice_lock);
1803 spin_lock_init(&emu->synth_lock);
1804 spin_lock_init(&emu->memblk_lock);
1805 mutex_init(&emu->fx8010.lock);
1806 INIT_LIST_HEAD(&emu->mapped_link_head);
1807 INIT_LIST_HEAD(&emu->mapped_order_link_head);
1808 emu->pci = pci;
1809 emu->irq = -1;
1810 emu->synth = NULL;
1811 emu->get_synth_voice = NULL;
1812 INIT_DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work);
1813 /* read revision & serial */
1814 emu->revision = pci->revision;
1815 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
1816 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
1817 dev_dbg(card->dev,
1818 "vendor = 0x%x, device = 0x%x, subsystem_vendor_id = 0x%x, subsystem_id = 0x%x\n",
1819 pci->vendor, pci->device, emu->serial, emu->model);
1820
1821 for (c = emu_chip_details; c->vendor; c++) {
1822 if (c->vendor == pci->vendor && c->device == pci->device) {
1823 if (subsystem) {
1824 if (c->subsystem && (c->subsystem == subsystem))
1825 break;
1826 else
1827 continue;
1828 } else {
1829 if (c->subsystem && (c->subsystem != emu->serial))
1830 continue;
1831 if (c->revision && c->revision != emu->revision)
1832 continue;
1833 }
1834 break;
1835 }
1836 }
1837 if (c->vendor == 0) {
1838 dev_err(card->dev, "emu10k1: Card not recognised\n");
1839 kfree(emu);
1840 pci_disable_device(pci);
1841 return -ENOENT;
1842 }
1843 emu->card_capabilities = c;
1844 if (c->subsystem && !subsystem)
1845 dev_dbg(card->dev, "Sound card name = %s\n", c->name);
1846 else if (subsystem)
1847 dev_dbg(card->dev, "Sound card name = %s, "
1848 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x. "
1849 "Forced to subsystem = 0x%x\n", c->name,
1850 pci->vendor, pci->device, emu->serial, c->subsystem);
1851 else
1852 dev_dbg(card->dev, "Sound card name = %s, "
1853 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x.\n",
1854 c->name, pci->vendor, pci->device,
1855 emu->serial);
1856
1857 if (!*card->id && c->id) {
1858 int i, n = 0;
1859 strlcpy(card->id, c->id, sizeof(card->id));
1860 for (;;) {
1861 for (i = 0; i < snd_ecards_limit; i++) {
1862 if (snd_cards[i] && !strcmp(snd_cards[i]->id, card->id))
1863 break;
1864 }
1865 if (i >= snd_ecards_limit)
1866 break;
1867 n++;
1868 if (n >= SNDRV_CARDS)
1869 break;
1870 snprintf(card->id, sizeof(card->id), "%s_%d", c->id, n);
1871 }
1872 }
1873
1874 is_audigy = emu->audigy = c->emu10k2_chip;
1875
1876 /* set addressing mode */
1877 emu->address_mode = is_audigy ? 0 : 1;
1878 /* set the DMA transfer mask */
1879 emu->dma_mask = emu->address_mode ? EMU10K1_DMA_MASK : AUDIGY_DMA_MASK;
1880 if (dma_set_mask(&pci->dev, emu->dma_mask) < 0 ||
1881 dma_set_coherent_mask(&pci->dev, emu->dma_mask) < 0) {
1882 dev_err(card->dev,
1883 "architecture does not support PCI busmaster DMA with mask 0x%lx\n",
1884 emu->dma_mask);
1885 kfree(emu);
1886 pci_disable_device(pci);
1887 return -ENXIO;
1888 }
1889 if (is_audigy)
1890 emu->gpr_base = A_FXGPREGBASE;
1891 else
1892 emu->gpr_base = FXGPREGBASE;
1893
1894 err = pci_request_regions(pci, "EMU10K1");
1895 if (err < 0) {
1896 kfree(emu);
1897 pci_disable_device(pci);
1898 return err;
1899 }
1900 emu->port = pci_resource_start(pci, 0);
1901
1902 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
1903 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1904 (emu->address_mode ? 32 : 16) * 1024, &emu->ptb_pages) < 0) {
1905 err = -ENOMEM;
1906 goto error;
1907 }
1908
1909 emu->page_ptr_table = vmalloc(emu->max_cache_pages * sizeof(void *));
1910 emu->page_addr_table = vmalloc(emu->max_cache_pages *
1911 sizeof(unsigned long));
1912 if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
1913 err = -ENOMEM;
1914 goto error;
1915 }
1916
1917 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1918 EMUPAGESIZE, &emu->silent_page) < 0) {
1919 err = -ENOMEM;
1920 goto error;
1921 }
1922 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
1923 if (emu->memhdr == NULL) {
1924 err = -ENOMEM;
1925 goto error;
1926 }
1927 emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) -
1928 sizeof(struct snd_util_memblk);
1929
1930 pci_set_master(pci);
1931
1932 emu->fx8010.fxbus_mask = 0x303f;
1933 if (extin_mask == 0)
1934 extin_mask = 0x3fcf;
1935 if (extout_mask == 0)
1936 extout_mask = 0x7fff;
1937 emu->fx8010.extin_mask = extin_mask;
1938 emu->fx8010.extout_mask = extout_mask;
1939 emu->enable_ir = enable_ir;
1940
1941 if (emu->card_capabilities->ca_cardbus_chip) {
1942 err = snd_emu10k1_cardbus_init(emu);
1943 if (err < 0)
1944 goto error;
1945 }
1946 if (emu->card_capabilities->ecard) {
1947 err = snd_emu10k1_ecard_init(emu);
1948 if (err < 0)
1949 goto error;
1950 } else if (emu->card_capabilities->emu_model) {
1951 err = snd_emu10k1_emu1010_init(emu);
1952 if (err < 0) {
1953 snd_emu10k1_free(emu);
1954 return err;
1955 }
1956 } else {
1957 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
1958 does not support this, it shouldn't do any harm */
1959 snd_emu10k1_ptr_write(emu, AC97SLOT, 0,
1960 AC97SLOT_CNTR|AC97SLOT_LFE);
1961 }
1962
1963 /* initialize TRAM setup */
1964 emu->fx8010.itram_size = (16 * 1024)/2;
1965 emu->fx8010.etram_pages.area = NULL;
1966 emu->fx8010.etram_pages.bytes = 0;
1967
1968 /* irq handler must be registered after I/O ports are activated */
1969 if (request_irq(pci->irq, snd_emu10k1_interrupt, IRQF_SHARED,
1970 KBUILD_MODNAME, emu)) {
1971 err = -EBUSY;
1972 goto error;
1973 }
1974 emu->irq = pci->irq;
1975
1976 /*
1977 * Init to 0x02109204 :
1978 * Clock accuracy = 0 (1000ppm)
1979 * Sample Rate = 2 (48kHz)
1980 * Audio Channel = 1 (Left of 2)
1981 * Source Number = 0 (Unspecified)
1982 * Generation Status = 1 (Original for Cat Code 12)
1983 * Cat Code = 12 (Digital Signal Mixer)
1984 * Mode = 0 (Mode 0)
1985 * Emphasis = 0 (None)
1986 * CP = 1 (Copyright unasserted)
1987 * AN = 0 (Audio data)
1988 * P = 0 (Consumer)
1989 */
1990 emu->spdif_bits[0] = emu->spdif_bits[1] =
1991 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1992 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
1993 SPCS_GENERATIONSTATUS | 0x00001200 |
1994 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
1995
1996 emu->reserved_page = (struct snd_emu10k1_memblk *)
1997 snd_emu10k1_synth_alloc(emu, 4096);
1998 if (emu->reserved_page)
1999 emu->reserved_page->map_locked = 1;
2000
2001 /* Clear silent pages and set up pointers */
2002 memset(emu->silent_page.area, 0, PAGE_SIZE);
2003 silent_page = emu->silent_page.addr << emu->address_mode;
2004 for (idx = 0; idx < (emu->address_mode ? MAXPAGES1 : MAXPAGES0); idx++)
2005 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
2006
2007 /* set up voice indices */
2008 for (idx = 0; idx < NUM_G; idx++) {
2009 emu->voices[idx].emu = emu;
2010 emu->voices[idx].number = idx;
2011 }
2012
2013 err = snd_emu10k1_init(emu, enable_ir, 0);
2014 if (err < 0)
2015 goto error;
2016 #ifdef CONFIG_PM_SLEEP
2017 err = alloc_pm_buffer(emu);
2018 if (err < 0)
2019 goto error;
2020 #endif
2021
2022 /* Initialize the effect engine */
2023 err = snd_emu10k1_init_efx(emu);
2024 if (err < 0)
2025 goto error;
2026 snd_emu10k1_audio_enable(emu);
2027
2028 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops);
2029 if (err < 0)
2030 goto error;
2031
2032 #ifdef CONFIG_SND_PROC_FS
2033 snd_emu10k1_proc_init(emu);
2034 #endif
2035
2036 *remu = emu;
2037 return 0;
2038
2039 error:
2040 snd_emu10k1_free(emu);
2041 return err;
2042 }
2043
2044 #ifdef CONFIG_PM_SLEEP
2045 static unsigned char saved_regs[] = {
2046 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
2047 FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL,
2048 ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2,
2049 TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA,
2050 MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2,
2051 SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX,
2052 0xff /* end */
2053 };
2054 static unsigned char saved_regs_audigy[] = {
2055 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE,
2056 A_FXRT2, A_SENDAMOUNTS, A_FXRT1,
2057 0xff /* end */
2058 };
2059
2060 static int alloc_pm_buffer(struct snd_emu10k1 *emu)
2061 {
2062 int size;
2063
2064 size = ARRAY_SIZE(saved_regs);
2065 if (emu->audigy)
2066 size += ARRAY_SIZE(saved_regs_audigy);
2067 emu->saved_ptr = vmalloc(4 * NUM_G * size);
2068 if (!emu->saved_ptr)
2069 return -ENOMEM;
2070 if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0)
2071 return -ENOMEM;
2072 if (emu->card_capabilities->ca0151_chip &&
2073 snd_p16v_alloc_pm_buffer(emu) < 0)
2074 return -ENOMEM;
2075 return 0;
2076 }
2077
2078 static void free_pm_buffer(struct snd_emu10k1 *emu)
2079 {
2080 vfree(emu->saved_ptr);
2081 snd_emu10k1_efx_free_pm_buffer(emu);
2082 if (emu->card_capabilities->ca0151_chip)
2083 snd_p16v_free_pm_buffer(emu);
2084 }
2085
2086 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu)
2087 {
2088 int i;
2089 unsigned char *reg;
2090 unsigned int *val;
2091
2092 val = emu->saved_ptr;
2093 for (reg = saved_regs; *reg != 0xff; reg++)
2094 for (i = 0; i < NUM_G; i++, val++)
2095 *val = snd_emu10k1_ptr_read(emu, *reg, i);
2096 if (emu->audigy) {
2097 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
2098 for (i = 0; i < NUM_G; i++, val++)
2099 *val = snd_emu10k1_ptr_read(emu, *reg, i);
2100 }
2101 if (emu->audigy)
2102 emu->saved_a_iocfg = inl(emu->port + A_IOCFG);
2103 emu->saved_hcfg = inl(emu->port + HCFG);
2104 }
2105
2106 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu)
2107 {
2108 if (emu->card_capabilities->ca_cardbus_chip)
2109 snd_emu10k1_cardbus_init(emu);
2110 if (emu->card_capabilities->ecard)
2111 snd_emu10k1_ecard_init(emu);
2112 else if (emu->card_capabilities->emu_model)
2113 snd_emu10k1_emu1010_init(emu);
2114 else
2115 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
2116 snd_emu10k1_init(emu, emu->enable_ir, 1);
2117 }
2118
2119 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu)
2120 {
2121 int i;
2122 unsigned char *reg;
2123 unsigned int *val;
2124
2125 snd_emu10k1_audio_enable(emu);
2126
2127 /* resore for spdif */
2128 if (emu->audigy)
2129 outl(emu->saved_a_iocfg, emu->port + A_IOCFG);
2130 outl(emu->saved_hcfg, emu->port + HCFG);
2131
2132 val = emu->saved_ptr;
2133 for (reg = saved_regs; *reg != 0xff; reg++)
2134 for (i = 0; i < NUM_G; i++, val++)
2135 snd_emu10k1_ptr_write(emu, *reg, i, *val);
2136 if (emu->audigy) {
2137 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
2138 for (i = 0; i < NUM_G; i++, val++)
2139 snd_emu10k1_ptr_write(emu, *reg, i, *val);
2140 }
2141 }
2142 #endif
CRIS linux kernel tree