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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / sound / soc / codecs / da732x.c
blob83db4d23c90b9590eef0723562c50f52ce0c3ee2
1 /*
2 * da732x.c --- Dialog DA732X ALSA SoC Audio Driver
3 *
4 * Copyright (C) 2012 Dialog Semiconductor GmbH
5 *
6 * Author: Michal Hajduk <Michal.Hajduk@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/sysfs.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <asm/div64.h>
31
32 #include "da732x.h"
33 #include "da732x_reg.h"
34
35
36 struct da732x_priv {
37 struct regmap *regmap;
38
39 unsigned int sysclk;
40 bool pll_en;
41 };
42
43 /*
44 * da732x register cache - default settings
45 */
46 static const struct reg_default da732x_reg_cache[] = {
47 { DA732X_REG_REF1 , 0x02 },
48 { DA732X_REG_BIAS_EN , 0x80 },
49 { DA732X_REG_BIAS1 , 0x00 },
50 { DA732X_REG_BIAS2 , 0x00 },
51 { DA732X_REG_BIAS3 , 0x00 },
52 { DA732X_REG_BIAS4 , 0x00 },
53 { DA732X_REG_MICBIAS2 , 0x00 },
54 { DA732X_REG_MICBIAS1 , 0x00 },
55 { DA732X_REG_MICDET , 0x00 },
56 { DA732X_REG_MIC1_PRE , 0x01 },
57 { DA732X_REG_MIC1 , 0x40 },
58 { DA732X_REG_MIC2_PRE , 0x01 },
59 { DA732X_REG_MIC2 , 0x40 },
60 { DA732X_REG_AUX1L , 0x75 },
61 { DA732X_REG_AUX1R , 0x75 },
62 { DA732X_REG_MIC3_PRE , 0x01 },
63 { DA732X_REG_MIC3 , 0x40 },
64 { DA732X_REG_INP_PINBIAS , 0x00 },
65 { DA732X_REG_INP_ZC_EN , 0x00 },
66 { DA732X_REG_INP_MUX , 0x50 },
67 { DA732X_REG_HP_DET , 0x00 },
68 { DA732X_REG_HPL_DAC_OFFSET , 0x00 },
69 { DA732X_REG_HPL_DAC_OFF_CNTL , 0x00 },
70 { DA732X_REG_HPL_OUT_OFFSET , 0x00 },
71 { DA732X_REG_HPL , 0x40 },
72 { DA732X_REG_HPL_VOL , 0x0F },
73 { DA732X_REG_HPR_DAC_OFFSET , 0x00 },
74 { DA732X_REG_HPR_DAC_OFF_CNTL , 0x00 },
75 { DA732X_REG_HPR_OUT_OFFSET , 0x00 },
76 { DA732X_REG_HPR , 0x40 },
77 { DA732X_REG_HPR_VOL , 0x0F },
78 { DA732X_REG_LIN2 , 0x4F },
79 { DA732X_REG_LIN3 , 0x4F },
80 { DA732X_REG_LIN4 , 0x4F },
81 { DA732X_REG_OUT_ZC_EN , 0x00 },
82 { DA732X_REG_HP_LIN1_GNDSEL , 0x00 },
83 { DA732X_REG_CP_HP1 , 0x0C },
84 { DA732X_REG_CP_HP2 , 0x03 },
85 { DA732X_REG_CP_CTRL1 , 0x00 },
86 { DA732X_REG_CP_CTRL2 , 0x99 },
87 { DA732X_REG_CP_CTRL3 , 0x25 },
88 { DA732X_REG_CP_LEVEL_MASK , 0x3F },
89 { DA732X_REG_CP_DET , 0x00 },
90 { DA732X_REG_CP_STATUS , 0x00 },
91 { DA732X_REG_CP_THRESH1 , 0x00 },
92 { DA732X_REG_CP_THRESH2 , 0x00 },
93 { DA732X_REG_CP_THRESH3 , 0x00 },
94 { DA732X_REG_CP_THRESH4 , 0x00 },
95 { DA732X_REG_CP_THRESH5 , 0x00 },
96 { DA732X_REG_CP_THRESH6 , 0x00 },
97 { DA732X_REG_CP_THRESH7 , 0x00 },
98 { DA732X_REG_CP_THRESH8 , 0x00 },
99 { DA732X_REG_PLL_DIV_LO , 0x00 },
100 { DA732X_REG_PLL_DIV_MID , 0x00 },
101 { DA732X_REG_PLL_DIV_HI , 0x00 },
102 { DA732X_REG_PLL_CTRL , 0x02 },
103 { DA732X_REG_CLK_CTRL , 0xaa },
104 { DA732X_REG_CLK_DSP , 0x07 },
105 { DA732X_REG_CLK_EN1 , 0x00 },
106 { DA732X_REG_CLK_EN2 , 0x00 },
107 { DA732X_REG_CLK_EN3 , 0x00 },
108 { DA732X_REG_CLK_EN4 , 0x00 },
109 { DA732X_REG_CLK_EN5 , 0x00 },
110 { DA732X_REG_AIF_MCLK , 0x00 },
111 { DA732X_REG_AIFA1 , 0x02 },
112 { DA732X_REG_AIFA2 , 0x00 },
113 { DA732X_REG_AIFA3 , 0x08 },
114 { DA732X_REG_AIFB1 , 0x02 },
115 { DA732X_REG_AIFB2 , 0x00 },
116 { DA732X_REG_AIFB3 , 0x08 },
117 { DA732X_REG_PC_CTRL , 0xC0 },
118 { DA732X_REG_DATA_ROUTE , 0x00 },
119 { DA732X_REG_DSP_CTRL , 0x00 },
120 { DA732X_REG_CIF_CTRL2 , 0x00 },
121 { DA732X_REG_HANDSHAKE , 0x00 },
122 { DA732X_REG_SPARE1_OUT , 0x00 },
123 { DA732X_REG_SPARE2_OUT , 0x00 },
124 { DA732X_REG_SPARE1_IN , 0x00 },
125 { DA732X_REG_ADC1_PD , 0x00 },
126 { DA732X_REG_ADC1_HPF , 0x00 },
127 { DA732X_REG_ADC1_SEL , 0x00 },
128 { DA732X_REG_ADC1_EQ12 , 0x00 },
129 { DA732X_REG_ADC1_EQ34 , 0x00 },
130 { DA732X_REG_ADC1_EQ5 , 0x00 },
131 { DA732X_REG_ADC2_PD , 0x00 },
132 { DA732X_REG_ADC2_HPF , 0x00 },
133 { DA732X_REG_ADC2_SEL , 0x00 },
134 { DA732X_REG_ADC2_EQ12 , 0x00 },
135 { DA732X_REG_ADC2_EQ34 , 0x00 },
136 { DA732X_REG_ADC2_EQ5 , 0x00 },
137 { DA732X_REG_DAC1_HPF , 0x00 },
138 { DA732X_REG_DAC1_L_VOL , 0x00 },
139 { DA732X_REG_DAC1_R_VOL , 0x00 },
140 { DA732X_REG_DAC1_SEL , 0x00 },
141 { DA732X_REG_DAC1_SOFTMUTE , 0x00 },
142 { DA732X_REG_DAC1_EQ12 , 0x00 },
143 { DA732X_REG_DAC1_EQ34 , 0x00 },
144 { DA732X_REG_DAC1_EQ5 , 0x00 },
145 { DA732X_REG_DAC2_HPF , 0x00 },
146 { DA732X_REG_DAC2_L_VOL , 0x00 },
147 { DA732X_REG_DAC2_R_VOL , 0x00 },
148 { DA732X_REG_DAC2_SEL , 0x00 },
149 { DA732X_REG_DAC2_SOFTMUTE , 0x00 },
150 { DA732X_REG_DAC2_EQ12 , 0x00 },
151 { DA732X_REG_DAC2_EQ34 , 0x00 },
152 { DA732X_REG_DAC2_EQ5 , 0x00 },
153 { DA732X_REG_DAC3_HPF , 0x00 },
154 { DA732X_REG_DAC3_VOL , 0x00 },
155 { DA732X_REG_DAC3_SEL , 0x00 },
156 { DA732X_REG_DAC3_SOFTMUTE , 0x00 },
157 { DA732X_REG_DAC3_EQ12 , 0x00 },
158 { DA732X_REG_DAC3_EQ34 , 0x00 },
159 { DA732X_REG_DAC3_EQ5 , 0x00 },
160 { DA732X_REG_BIQ_BYP , 0x00 },
161 { DA732X_REG_DMA_CMD , 0x00 },
162 { DA732X_REG_DMA_ADDR0 , 0x00 },
163 { DA732X_REG_DMA_ADDR1 , 0x00 },
164 { DA732X_REG_DMA_DATA0 , 0x00 },
165 { DA732X_REG_DMA_DATA1 , 0x00 },
166 { DA732X_REG_DMA_DATA2 , 0x00 },
167 { DA732X_REG_DMA_DATA3 , 0x00 },
168 { DA732X_REG_UNLOCK , 0x00 },
169 };
170
171 static inline int da732x_get_input_div(struct snd_soc_codec *codec, int sysclk)
172 {
173 int val;
174 int ret;
175
176 if (sysclk < DA732X_MCLK_10MHZ) {
177 val = DA732X_MCLK_RET_0_10MHZ;
178 ret = DA732X_MCLK_VAL_0_10MHZ;
179 } else if ((sysclk >= DA732X_MCLK_10MHZ) &&
180 (sysclk < DA732X_MCLK_20MHZ)) {
181 val = DA732X_MCLK_RET_10_20MHZ;
182 ret = DA732X_MCLK_VAL_10_20MHZ;
183 } else if ((sysclk >= DA732X_MCLK_20MHZ) &&
184 (sysclk < DA732X_MCLK_40MHZ)) {
185 val = DA732X_MCLK_RET_20_40MHZ;
186 ret = DA732X_MCLK_VAL_20_40MHZ;
187 } else if ((sysclk >= DA732X_MCLK_40MHZ) &&
188 (sysclk <= DA732X_MCLK_54MHZ)) {
189 val = DA732X_MCLK_RET_40_54MHZ;
190 ret = DA732X_MCLK_VAL_40_54MHZ;
191 } else {
192 return -EINVAL;
193 }
194
195 snd_soc_write(codec, DA732X_REG_PLL_CTRL, val);
196
197 return ret;
198 }
199
200 static void da732x_set_charge_pump(struct snd_soc_codec *codec, int state)
201 {
202 switch (state) {
203 case DA732X_ENABLE_CP:
204 snd_soc_write(codec, DA732X_REG_CLK_EN2, DA732X_CP_CLK_EN);
205 snd_soc_write(codec, DA732X_REG_CP_HP2, DA732X_HP_CP_EN |
206 DA732X_HP_CP_REG | DA732X_HP_CP_PULSESKIP);
207 snd_soc_write(codec, DA732X_REG_CP_CTRL1, DA732X_CP_EN |
208 DA732X_CP_CTRL_CPVDD1);
209 snd_soc_write(codec, DA732X_REG_CP_CTRL2,
210 DA732X_CP_MANAGE_MAGNITUDE | DA732X_CP_BOOST);
211 snd_soc_write(codec, DA732X_REG_CP_CTRL3, DA732X_CP_1MHZ);
212 break;
213 case DA732X_DISABLE_CP:
214 snd_soc_write(codec, DA732X_REG_CLK_EN2, DA732X_CP_CLK_DIS);
215 snd_soc_write(codec, DA732X_REG_CP_HP2, DA732X_HP_CP_DIS);
216 snd_soc_write(codec, DA732X_REG_CP_CTRL1, DA723X_CP_DIS);
217 break;
218 default:
219 pr_err("Wrong charge pump state\n");
220 break;
221 }
222 }
223
224 static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, DA732X_MIC_PRE_VOL_DB_MIN,
225 DA732X_MIC_PRE_VOL_DB_INC, 0);
226
227 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, DA732X_MIC_VOL_DB_MIN,
228 DA732X_MIC_VOL_DB_INC, 0);
229
230 static const DECLARE_TLV_DB_SCALE(aux_pga_tlv, DA732X_AUX_VOL_DB_MIN,
231 DA732X_AUX_VOL_DB_INC, 0);
232
233 static const DECLARE_TLV_DB_SCALE(hp_pga_tlv, DA732X_HP_VOL_DB_MIN,
234 DA732X_AUX_VOL_DB_INC, 0);
235
236 static const DECLARE_TLV_DB_SCALE(lin2_pga_tlv, DA732X_LIN2_VOL_DB_MIN,
237 DA732X_LIN2_VOL_DB_INC, 0);
238
239 static const DECLARE_TLV_DB_SCALE(lin3_pga_tlv, DA732X_LIN3_VOL_DB_MIN,
240 DA732X_LIN3_VOL_DB_INC, 0);
241
242 static const DECLARE_TLV_DB_SCALE(lin4_pga_tlv, DA732X_LIN4_VOL_DB_MIN,
243 DA732X_LIN4_VOL_DB_INC, 0);
244
245 static const DECLARE_TLV_DB_SCALE(adc_pga_tlv, DA732X_ADC_VOL_DB_MIN,
246 DA732X_ADC_VOL_DB_INC, 0);
247
248 static const DECLARE_TLV_DB_SCALE(dac_pga_tlv, DA732X_DAC_VOL_DB_MIN,
249 DA732X_DAC_VOL_DB_INC, 0);
250
251 static const DECLARE_TLV_DB_SCALE(eq_band_pga_tlv, DA732X_EQ_BAND_VOL_DB_MIN,
252 DA732X_EQ_BAND_VOL_DB_INC, 0);
253
254 static const DECLARE_TLV_DB_SCALE(eq_overall_tlv, DA732X_EQ_OVERALL_VOL_DB_MIN,
255 DA732X_EQ_OVERALL_VOL_DB_INC, 0);
256
257 /* High Pass Filter */
258 static const char *da732x_hpf_mode[] = {
259 "Disable", "Music", "Voice",
260 };
261
262 static const char *da732x_hpf_music[] = {
263 "1.8Hz", "3.75Hz", "7.5Hz", "15Hz",
264 };
265
266 static const char *da732x_hpf_voice[] = {
267 "2.5Hz", "25Hz", "50Hz", "100Hz",
268 "150Hz", "200Hz", "300Hz", "400Hz"
269 };
270
271 static SOC_ENUM_SINGLE_DECL(da732x_dac1_hpf_mode_enum,
272 DA732X_REG_DAC1_HPF, DA732X_HPF_MODE_SHIFT,
273 da732x_hpf_mode);
274
275 static SOC_ENUM_SINGLE_DECL(da732x_dac2_hpf_mode_enum,
276 DA732X_REG_DAC2_HPF, DA732X_HPF_MODE_SHIFT,
277 da732x_hpf_mode);
278
279 static SOC_ENUM_SINGLE_DECL(da732x_dac3_hpf_mode_enum,
280 DA732X_REG_DAC3_HPF, DA732X_HPF_MODE_SHIFT,
281 da732x_hpf_mode);
282
283 static SOC_ENUM_SINGLE_DECL(da732x_adc1_hpf_mode_enum,
284 DA732X_REG_ADC1_HPF, DA732X_HPF_MODE_SHIFT,
285 da732x_hpf_mode);
286
287 static SOC_ENUM_SINGLE_DECL(da732x_adc2_hpf_mode_enum,
288 DA732X_REG_ADC2_HPF, DA732X_HPF_MODE_SHIFT,
289 da732x_hpf_mode);
290
291 static SOC_ENUM_SINGLE_DECL(da732x_dac1_hp_filter_enum,
292 DA732X_REG_DAC1_HPF, DA732X_HPF_MUSIC_SHIFT,
293 da732x_hpf_music);
294
295 static SOC_ENUM_SINGLE_DECL(da732x_dac2_hp_filter_enum,
296 DA732X_REG_DAC2_HPF, DA732X_HPF_MUSIC_SHIFT,
297 da732x_hpf_music);
298
299 static SOC_ENUM_SINGLE_DECL(da732x_dac3_hp_filter_enum,
300 DA732X_REG_DAC3_HPF, DA732X_HPF_MUSIC_SHIFT,
301 da732x_hpf_music);
302
303 static SOC_ENUM_SINGLE_DECL(da732x_adc1_hp_filter_enum,
304 DA732X_REG_ADC1_HPF, DA732X_HPF_MUSIC_SHIFT,
305 da732x_hpf_music);
306
307 static SOC_ENUM_SINGLE_DECL(da732x_adc2_hp_filter_enum,
308 DA732X_REG_ADC2_HPF, DA732X_HPF_MUSIC_SHIFT,
309 da732x_hpf_music);
310
311 static SOC_ENUM_SINGLE_DECL(da732x_dac1_voice_filter_enum,
312 DA732X_REG_DAC1_HPF, DA732X_HPF_VOICE_SHIFT,
313 da732x_hpf_voice);
314
315 static SOC_ENUM_SINGLE_DECL(da732x_dac2_voice_filter_enum,
316 DA732X_REG_DAC2_HPF, DA732X_HPF_VOICE_SHIFT,
317 da732x_hpf_voice);
318
319 static SOC_ENUM_SINGLE_DECL(da732x_dac3_voice_filter_enum,
320 DA732X_REG_DAC3_HPF, DA732X_HPF_VOICE_SHIFT,
321 da732x_hpf_voice);
322
323 static SOC_ENUM_SINGLE_DECL(da732x_adc1_voice_filter_enum,
324 DA732X_REG_ADC1_HPF, DA732X_HPF_VOICE_SHIFT,
325 da732x_hpf_voice);
326
327 static SOC_ENUM_SINGLE_DECL(da732x_adc2_voice_filter_enum,
328 DA732X_REG_ADC2_HPF, DA732X_HPF_VOICE_SHIFT,
329 da732x_hpf_voice);
330
331 static int da732x_hpf_set(struct snd_kcontrol *kcontrol,
332 struct snd_ctl_elem_value *ucontrol)
333 {
334 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
335 struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
336 unsigned int reg = enum_ctrl->reg;
337 unsigned int sel = ucontrol->value.enumerated.item[0];
338 unsigned int bits;
339
340 switch (sel) {
341 case DA732X_HPF_DISABLED:
342 bits = DA732X_HPF_DIS;
343 break;
344 case DA732X_HPF_VOICE:
345 bits = DA732X_HPF_VOICE_EN;
346 break;
347 case DA732X_HPF_MUSIC:
348 bits = DA732X_HPF_MUSIC_EN;
349 break;
350 default:
351 return -EINVAL;
352 }
353
354 snd_soc_update_bits(codec, reg, DA732X_HPF_MASK, bits);
355
356 return 0;
357 }
358
359 static int da732x_hpf_get(struct snd_kcontrol *kcontrol,
360 struct snd_ctl_elem_value *ucontrol)
361 {
362 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
363 struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
364 unsigned int reg = enum_ctrl->reg;
365 int val;
366
367 val = snd_soc_read(codec, reg) & DA732X_HPF_MASK;
368
369 switch (val) {
370 case DA732X_HPF_VOICE_EN:
371 ucontrol->value.enumerated.item[0] = DA732X_HPF_VOICE;
372 break;
373 case DA732X_HPF_MUSIC_EN:
374 ucontrol->value.enumerated.item[0] = DA732X_HPF_MUSIC;
375 break;
376 default:
377 ucontrol->value.enumerated.item[0] = DA732X_HPF_DISABLED;
378 break;
379 }
380
381 return 0;
382 }
383
384 static const struct snd_kcontrol_new da732x_snd_controls[] = {
385 /* Input PGAs */
386 SOC_SINGLE_RANGE_TLV("MIC1 Boost Volume", DA732X_REG_MIC1_PRE,
387 DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
388 DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
389 SOC_SINGLE_RANGE_TLV("MIC2 Boost Volume", DA732X_REG_MIC2_PRE,
390 DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
391 DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
392 SOC_SINGLE_RANGE_TLV("MIC3 Boost Volume", DA732X_REG_MIC3_PRE,
393 DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
394 DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
395
396 /* MICs */
397 SOC_SINGLE("MIC1 Switch", DA732X_REG_MIC1, DA732X_MIC_MUTE_SHIFT,
398 DA732X_SWITCH_MAX, DA732X_INVERT),
399 SOC_SINGLE_RANGE_TLV("MIC1 Volume", DA732X_REG_MIC1,
400 DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
401 DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
402 SOC_SINGLE("MIC2 Switch", DA732X_REG_MIC2, DA732X_MIC_MUTE_SHIFT,
403 DA732X_SWITCH_MAX, DA732X_INVERT),
404 SOC_SINGLE_RANGE_TLV("MIC2 Volume", DA732X_REG_MIC2,
405 DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
406 DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
407 SOC_SINGLE("MIC3 Switch", DA732X_REG_MIC3, DA732X_MIC_MUTE_SHIFT,
408 DA732X_SWITCH_MAX, DA732X_INVERT),
409 SOC_SINGLE_RANGE_TLV("MIC3 Volume", DA732X_REG_MIC3,
410 DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
411 DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
412
413 /* AUXs */
414 SOC_SINGLE("AUX1L Switch", DA732X_REG_AUX1L, DA732X_AUX_MUTE_SHIFT,
415 DA732X_SWITCH_MAX, DA732X_INVERT),
416 SOC_SINGLE_TLV("AUX1L Volume", DA732X_REG_AUX1L,
417 DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX,
418 DA732X_NO_INVERT, aux_pga_tlv),
419 SOC_SINGLE("AUX1R Switch", DA732X_REG_AUX1R, DA732X_AUX_MUTE_SHIFT,
420 DA732X_SWITCH_MAX, DA732X_INVERT),
421 SOC_SINGLE_TLV("AUX1R Volume", DA732X_REG_AUX1R,
422 DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX,
423 DA732X_NO_INVERT, aux_pga_tlv),
424
425 /* ADCs */
426 SOC_DOUBLE_TLV("ADC1 Volume", DA732X_REG_ADC1_SEL,
427 DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT,
428 DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv),
429
430 SOC_DOUBLE_TLV("ADC2 Volume", DA732X_REG_ADC2_SEL,
431 DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT,
432 DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv),
433
434 /* DACs */
435 SOC_DOUBLE("Digital Playback DAC12 Switch", DA732X_REG_DAC1_SEL,
436 DA732X_DACL_MUTE_SHIFT, DA732X_DACR_MUTE_SHIFT,
437 DA732X_SWITCH_MAX, DA732X_INVERT),
438 SOC_DOUBLE_R_TLV("Digital Playback DAC12 Volume", DA732X_REG_DAC1_L_VOL,
439 DA732X_REG_DAC1_R_VOL, DA732X_DAC_VOL_SHIFT,
440 DA732X_DAC_VOL_VAL_MAX, DA732X_INVERT, dac_pga_tlv),
441 SOC_SINGLE("Digital Playback DAC3 Switch", DA732X_REG_DAC2_SEL,
442 DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
443 SOC_SINGLE_TLV("Digital Playback DAC3 Volume", DA732X_REG_DAC2_L_VOL,
444 DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
445 DA732X_INVERT, dac_pga_tlv),
446 SOC_SINGLE("Digital Playback DAC4 Switch", DA732X_REG_DAC2_SEL,
447 DA732X_DACR_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
448 SOC_SINGLE_TLV("Digital Playback DAC4 Volume", DA732X_REG_DAC2_R_VOL,
449 DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
450 DA732X_INVERT, dac_pga_tlv),
451 SOC_SINGLE("Digital Playback DAC5 Switch", DA732X_REG_DAC3_SEL,
452 DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
453 SOC_SINGLE_TLV("Digital Playback DAC5 Volume", DA732X_REG_DAC3_VOL,
454 DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
455 DA732X_INVERT, dac_pga_tlv),
456
457 /* High Pass Filters */
458 SOC_ENUM_EXT("DAC1 High Pass Filter Mode",
459 da732x_dac1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
460 SOC_ENUM("DAC1 High Pass Filter", da732x_dac1_hp_filter_enum),
461 SOC_ENUM("DAC1 Voice Filter", da732x_dac1_voice_filter_enum),
462
463 SOC_ENUM_EXT("DAC2 High Pass Filter Mode",
464 da732x_dac2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
465 SOC_ENUM("DAC2 High Pass Filter", da732x_dac2_hp_filter_enum),
466 SOC_ENUM("DAC2 Voice Filter", da732x_dac2_voice_filter_enum),
467
468 SOC_ENUM_EXT("DAC3 High Pass Filter Mode",
469 da732x_dac3_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
470 SOC_ENUM("DAC3 High Pass Filter", da732x_dac3_hp_filter_enum),
471 SOC_ENUM("DAC3 Filter Mode", da732x_dac3_voice_filter_enum),
472
473 SOC_ENUM_EXT("ADC1 High Pass Filter Mode",
474 da732x_adc1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
475 SOC_ENUM("ADC1 High Pass Filter", da732x_adc1_hp_filter_enum),
476 SOC_ENUM("ADC1 Voice Filter", da732x_adc1_voice_filter_enum),
477
478 SOC_ENUM_EXT("ADC2 High Pass Filter Mode",
479 da732x_adc2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
480 SOC_ENUM("ADC2 High Pass Filter", da732x_adc2_hp_filter_enum),
481 SOC_ENUM("ADC2 Voice Filter", da732x_adc2_voice_filter_enum),
482
483 /* Equalizers */
484 SOC_SINGLE("ADC1 EQ Switch", DA732X_REG_ADC1_EQ5,
485 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
486 SOC_SINGLE_TLV("ADC1 EQ Band 1 Volume", DA732X_REG_ADC1_EQ12,
487 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
488 DA732X_INVERT, eq_band_pga_tlv),
489 SOC_SINGLE_TLV("ADC1 EQ Band 2 Volume", DA732X_REG_ADC1_EQ12,
490 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
491 DA732X_INVERT, eq_band_pga_tlv),
492 SOC_SINGLE_TLV("ADC1 EQ Band 3 Volume", DA732X_REG_ADC1_EQ34,
493 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
494 DA732X_INVERT, eq_band_pga_tlv),
495 SOC_SINGLE_TLV("ADC1 EQ Band 4 Volume", DA732X_REG_ADC1_EQ34,
496 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
497 DA732X_INVERT, eq_band_pga_tlv),
498 SOC_SINGLE_TLV("ADC1 EQ Band 5 Volume", DA732X_REG_ADC1_EQ5,
499 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
500 DA732X_INVERT, eq_band_pga_tlv),
501 SOC_SINGLE_TLV("ADC1 EQ Overall Volume", DA732X_REG_ADC1_EQ5,
502 DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX,
503 DA732X_INVERT, eq_overall_tlv),
504
505 SOC_SINGLE("ADC2 EQ Switch", DA732X_REG_ADC2_EQ5,
506 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
507 SOC_SINGLE_TLV("ADC2 EQ Band 1 Volume", DA732X_REG_ADC2_EQ12,
508 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
509 DA732X_INVERT, eq_band_pga_tlv),
510 SOC_SINGLE_TLV("ADC2 EQ Band 2 Volume", DA732X_REG_ADC2_EQ12,
511 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
512 DA732X_INVERT, eq_band_pga_tlv),
513 SOC_SINGLE_TLV("ADC2 EQ Band 3 Volume", DA732X_REG_ADC2_EQ34,
514 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
515 DA732X_INVERT, eq_band_pga_tlv),
516 SOC_SINGLE_TLV("ACD2 EQ Band 4 Volume", DA732X_REG_ADC2_EQ34,
517 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
518 DA732X_INVERT, eq_band_pga_tlv),
519 SOC_SINGLE_TLV("ACD2 EQ Band 5 Volume", DA732X_REG_ADC2_EQ5,
520 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
521 DA732X_INVERT, eq_band_pga_tlv),
522 SOC_SINGLE_TLV("ADC2 EQ Overall Volume", DA732X_REG_ADC1_EQ5,
523 DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX,
524 DA732X_INVERT, eq_overall_tlv),
525
526 SOC_SINGLE("DAC1 EQ Switch", DA732X_REG_DAC1_EQ5,
527 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
528 SOC_SINGLE_TLV("DAC1 EQ Band 1 Volume", DA732X_REG_DAC1_EQ12,
529 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
530 DA732X_INVERT, eq_band_pga_tlv),
531 SOC_SINGLE_TLV("DAC1 EQ Band 2 Volume", DA732X_REG_DAC1_EQ12,
532 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
533 DA732X_INVERT, eq_band_pga_tlv),
534 SOC_SINGLE_TLV("DAC1 EQ Band 3 Volume", DA732X_REG_DAC1_EQ34,
535 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
536 DA732X_INVERT, eq_band_pga_tlv),
537 SOC_SINGLE_TLV("DAC1 EQ Band 4 Volume", DA732X_REG_DAC1_EQ34,
538 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
539 DA732X_INVERT, eq_band_pga_tlv),
540 SOC_SINGLE_TLV("DAC1 EQ Band 5 Volume", DA732X_REG_DAC1_EQ5,
541 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
542 DA732X_INVERT, eq_band_pga_tlv),
543
544 SOC_SINGLE("DAC2 EQ Switch", DA732X_REG_DAC2_EQ5,
545 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
546 SOC_SINGLE_TLV("DAC2 EQ Band 1 Volume", DA732X_REG_DAC2_EQ12,
547 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
548 DA732X_INVERT, eq_band_pga_tlv),
549 SOC_SINGLE_TLV("DAC2 EQ Band 2 Volume", DA732X_REG_DAC2_EQ12,
550 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
551 DA732X_INVERT, eq_band_pga_tlv),
552 SOC_SINGLE_TLV("DAC2 EQ Band 3 Volume", DA732X_REG_DAC2_EQ34,
553 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
554 DA732X_INVERT, eq_band_pga_tlv),
555 SOC_SINGLE_TLV("DAC2 EQ Band 4 Volume", DA732X_REG_DAC2_EQ34,
556 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
557 DA732X_INVERT, eq_band_pga_tlv),
558 SOC_SINGLE_TLV("DAC2 EQ Band 5 Volume", DA732X_REG_DAC2_EQ5,
559 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
560 DA732X_INVERT, eq_band_pga_tlv),
561
562 SOC_SINGLE("DAC3 EQ Switch", DA732X_REG_DAC3_EQ5,
563 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
564 SOC_SINGLE_TLV("DAC3 EQ Band 1 Volume", DA732X_REG_DAC3_EQ12,
565 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
566 DA732X_INVERT, eq_band_pga_tlv),
567 SOC_SINGLE_TLV("DAC3 EQ Band 2 Volume", DA732X_REG_DAC3_EQ12,
568 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
569 DA732X_INVERT, eq_band_pga_tlv),
570 SOC_SINGLE_TLV("DAC3 EQ Band 3 Volume", DA732X_REG_DAC3_EQ34,
571 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
572 DA732X_INVERT, eq_band_pga_tlv),
573 SOC_SINGLE_TLV("DAC3 EQ Band 4 Volume", DA732X_REG_DAC3_EQ34,
574 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
575 DA732X_INVERT, eq_band_pga_tlv),
576 SOC_SINGLE_TLV("DAC3 EQ Band 5 Volume", DA732X_REG_DAC3_EQ5,
577 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
578 DA732X_INVERT, eq_band_pga_tlv),
579
580 /* Lineout 2 Reciever*/
581 SOC_SINGLE("Lineout 2 Switch", DA732X_REG_LIN2, DA732X_LOUT_MUTE_SHIFT,
582 DA732X_SWITCH_MAX, DA732X_INVERT),
583 SOC_SINGLE_TLV("Lineout 2 Volume", DA732X_REG_LIN2,
584 DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
585 DA732X_NO_INVERT, lin2_pga_tlv),
586
587 /* Lineout 3 SPEAKER*/
588 SOC_SINGLE("Lineout 3 Switch", DA732X_REG_LIN3, DA732X_LOUT_MUTE_SHIFT,
589 DA732X_SWITCH_MAX, DA732X_INVERT),
590 SOC_SINGLE_TLV("Lineout 3 Volume", DA732X_REG_LIN3,
591 DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
592 DA732X_NO_INVERT, lin3_pga_tlv),
593
594 /* Lineout 4 */
595 SOC_SINGLE("Lineout 4 Switch", DA732X_REG_LIN4, DA732X_LOUT_MUTE_SHIFT,
596 DA732X_SWITCH_MAX, DA732X_INVERT),
597 SOC_SINGLE_TLV("Lineout 4 Volume", DA732X_REG_LIN4,
598 DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
599 DA732X_NO_INVERT, lin4_pga_tlv),
600
601 /* Headphones */
602 SOC_DOUBLE_R("Headphone Switch", DA732X_REG_HPR, DA732X_REG_HPL,
603 DA732X_HP_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
604 SOC_DOUBLE_R_TLV("Headphone Volume", DA732X_REG_HPL_VOL,
605 DA732X_REG_HPR_VOL, DA732X_HP_VOL_SHIFT,
606 DA732X_HP_VOL_VAL_MAX, DA732X_NO_INVERT, hp_pga_tlv),
607 };
608
609 static int da732x_adc_event(struct snd_soc_dapm_widget *w,
610 struct snd_kcontrol *kcontrol, int event)
611 {
612 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
613
614 switch (event) {
615 case SND_SOC_DAPM_POST_PMU:
616 switch (w->reg) {
617 case DA732X_REG_ADC1_PD:
618 snd_soc_update_bits(codec, DA732X_REG_CLK_EN3,
619 DA732X_ADCA_BB_CLK_EN,
620 DA732X_ADCA_BB_CLK_EN);
621 break;
622 case DA732X_REG_ADC2_PD:
623 snd_soc_update_bits(codec, DA732X_REG_CLK_EN3,
624 DA732X_ADCC_BB_CLK_EN,
625 DA732X_ADCC_BB_CLK_EN);
626 break;
627 default:
628 return -EINVAL;
629 }
630
631 snd_soc_update_bits(codec, w->reg, DA732X_ADC_RST_MASK,
632 DA732X_ADC_SET_ACT);
633 snd_soc_update_bits(codec, w->reg, DA732X_ADC_PD_MASK,
634 DA732X_ADC_ON);
635 break;
636 case SND_SOC_DAPM_POST_PMD:
637 snd_soc_update_bits(codec, w->reg, DA732X_ADC_PD_MASK,
638 DA732X_ADC_OFF);
639 snd_soc_update_bits(codec, w->reg, DA732X_ADC_RST_MASK,
640 DA732X_ADC_SET_RST);
641
642 switch (w->reg) {
643 case DA732X_REG_ADC1_PD:
644 snd_soc_update_bits(codec, DA732X_REG_CLK_EN3,
645 DA732X_ADCA_BB_CLK_EN, 0);
646 break;
647 case DA732X_REG_ADC2_PD:
648 snd_soc_update_bits(codec, DA732X_REG_CLK_EN3,
649 DA732X_ADCC_BB_CLK_EN, 0);
650 break;
651 default:
652 return -EINVAL;
653 }
654
655 break;
656 default:
657 return -EINVAL;
658 }
659
660 return 0;
661 }
662
663 static int da732x_out_pga_event(struct snd_soc_dapm_widget *w,
664 struct snd_kcontrol *kcontrol, int event)
665 {
666 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
667
668 switch (event) {
669 case SND_SOC_DAPM_POST_PMU:
670 snd_soc_update_bits(codec, w->reg,
671 (1 << w->shift) | DA732X_OUT_HIZ_EN,
672 (1 << w->shift) | DA732X_OUT_HIZ_EN);
673 break;
674 case SND_SOC_DAPM_POST_PMD:
675 snd_soc_update_bits(codec, w->reg,
676 (1 << w->shift) | DA732X_OUT_HIZ_EN,
677 (1 << w->shift) | DA732X_OUT_HIZ_DIS);
678 break;
679 default:
680 return -EINVAL;
681 }
682
683 return 0;
684 }
685
686 static const char *adcl_text[] = {
687 "AUX1L", "MIC1"
688 };
689
690 static const char *adcr_text[] = {
691 "AUX1R", "MIC2", "MIC3"
692 };
693
694 static const char *enable_text[] = {
695 "Disabled",
696 "Enabled"
697 };
698
699 /* ADC1LMUX */
700 static SOC_ENUM_SINGLE_DECL(adc1l_enum,
701 DA732X_REG_INP_MUX, DA732X_ADC1L_MUX_SEL_SHIFT,
702 adcl_text);
703 static const struct snd_kcontrol_new adc1l_mux =
704 SOC_DAPM_ENUM("ADC Route", adc1l_enum);
705
706 /* ADC1RMUX */
707 static SOC_ENUM_SINGLE_DECL(adc1r_enum,
708 DA732X_REG_INP_MUX, DA732X_ADC1R_MUX_SEL_SHIFT,
709 adcr_text);
710 static const struct snd_kcontrol_new adc1r_mux =
711 SOC_DAPM_ENUM("ADC Route", adc1r_enum);
712
713 /* ADC2LMUX */
714 static SOC_ENUM_SINGLE_DECL(adc2l_enum,
715 DA732X_REG_INP_MUX, DA732X_ADC2L_MUX_SEL_SHIFT,
716 adcl_text);
717 static const struct snd_kcontrol_new adc2l_mux =
718 SOC_DAPM_ENUM("ADC Route", adc2l_enum);
719
720 /* ADC2RMUX */
721 static SOC_ENUM_SINGLE_DECL(adc2r_enum,
722 DA732X_REG_INP_MUX, DA732X_ADC2R_MUX_SEL_SHIFT,
723 adcr_text);
724
725 static const struct snd_kcontrol_new adc2r_mux =
726 SOC_DAPM_ENUM("ADC Route", adc2r_enum);
727
728 static SOC_ENUM_SINGLE_DECL(da732x_hp_left_output,
729 DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN_SHIFT,
730 enable_text);
731
732 static const struct snd_kcontrol_new hpl_mux =
733 SOC_DAPM_ENUM("HPL Switch", da732x_hp_left_output);
734
735 static SOC_ENUM_SINGLE_DECL(da732x_hp_right_output,
736 DA732X_REG_HPR, DA732X_HP_OUT_DAC_EN_SHIFT,
737 enable_text);
738
739 static const struct snd_kcontrol_new hpr_mux =
740 SOC_DAPM_ENUM("HPR Switch", da732x_hp_right_output);
741
742 static SOC_ENUM_SINGLE_DECL(da732x_speaker_output,
743 DA732X_REG_LIN3, DA732X_LOUT_DAC_EN_SHIFT,
744 enable_text);
745
746 static const struct snd_kcontrol_new spk_mux =
747 SOC_DAPM_ENUM("SPK Switch", da732x_speaker_output);
748
749 static SOC_ENUM_SINGLE_DECL(da732x_lout4_output,
750 DA732X_REG_LIN4, DA732X_LOUT_DAC_EN_SHIFT,
751 enable_text);
752
753 static const struct snd_kcontrol_new lout4_mux =
754 SOC_DAPM_ENUM("LOUT4 Switch", da732x_lout4_output);
755
756 static SOC_ENUM_SINGLE_DECL(da732x_lout2_output,
757 DA732X_REG_LIN2, DA732X_LOUT_DAC_EN_SHIFT,
758 enable_text);
759
760 static const struct snd_kcontrol_new lout2_mux =
761 SOC_DAPM_ENUM("LOUT2 Switch", da732x_lout2_output);
762
763 static const struct snd_soc_dapm_widget da732x_dapm_widgets[] = {
764 /* Supplies */
765 SND_SOC_DAPM_SUPPLY("ADC1 Supply", DA732X_REG_ADC1_PD, 0,
766 DA732X_NO_INVERT, da732x_adc_event,
767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
768 SND_SOC_DAPM_SUPPLY("ADC2 Supply", DA732X_REG_ADC2_PD, 0,
769 DA732X_NO_INVERT, da732x_adc_event,
770 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
771 SND_SOC_DAPM_SUPPLY("DAC1 CLK", DA732X_REG_CLK_EN4,
772 DA732X_DACA_BB_CLK_SHIFT, DA732X_NO_INVERT,
773 NULL, 0),
774 SND_SOC_DAPM_SUPPLY("DAC2 CLK", DA732X_REG_CLK_EN4,
775 DA732X_DACC_BB_CLK_SHIFT, DA732X_NO_INVERT,
776 NULL, 0),
777 SND_SOC_DAPM_SUPPLY("DAC3 CLK", DA732X_REG_CLK_EN5,
778 DA732X_DACE_BB_CLK_SHIFT, DA732X_NO_INVERT,
779 NULL, 0),
780
781 /* Micbias */
782 SND_SOC_DAPM_SUPPLY("MICBIAS1", DA732X_REG_MICBIAS1,
783 DA732X_MICBIAS_EN_SHIFT,
784 DA732X_NO_INVERT, NULL, 0),
785 SND_SOC_DAPM_SUPPLY("MICBIAS2", DA732X_REG_MICBIAS2,
786 DA732X_MICBIAS_EN_SHIFT,
787 DA732X_NO_INVERT, NULL, 0),
788
789 /* Inputs */
790 SND_SOC_DAPM_INPUT("MIC1"),
791 SND_SOC_DAPM_INPUT("MIC2"),
792 SND_SOC_DAPM_INPUT("MIC3"),
793 SND_SOC_DAPM_INPUT("AUX1L"),
794 SND_SOC_DAPM_INPUT("AUX1R"),
795
796 /* Outputs */
797 SND_SOC_DAPM_OUTPUT("HPL"),
798 SND_SOC_DAPM_OUTPUT("HPR"),
799 SND_SOC_DAPM_OUTPUT("LOUTL"),
800 SND_SOC_DAPM_OUTPUT("LOUTR"),
801 SND_SOC_DAPM_OUTPUT("ClassD"),
802
803 /* ADCs */
804 SND_SOC_DAPM_ADC("ADC1L", NULL, DA732X_REG_ADC1_SEL,
805 DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT),
806 SND_SOC_DAPM_ADC("ADC1R", NULL, DA732X_REG_ADC1_SEL,
807 DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT),
808 SND_SOC_DAPM_ADC("ADC2L", NULL, DA732X_REG_ADC2_SEL,
809 DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT),
810 SND_SOC_DAPM_ADC("ADC2R", NULL, DA732X_REG_ADC2_SEL,
811 DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT),
812
813 /* DACs */
814 SND_SOC_DAPM_DAC("DAC1L", NULL, DA732X_REG_DAC1_SEL,
815 DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
816 SND_SOC_DAPM_DAC("DAC1R", NULL, DA732X_REG_DAC1_SEL,
817 DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT),
818 SND_SOC_DAPM_DAC("DAC2L", NULL, DA732X_REG_DAC2_SEL,
819 DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
820 SND_SOC_DAPM_DAC("DAC2R", NULL, DA732X_REG_DAC2_SEL,
821 DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT),
822 SND_SOC_DAPM_DAC("DAC3", NULL, DA732X_REG_DAC3_SEL,
823 DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
824
825 /* Input Pgas */
826 SND_SOC_DAPM_PGA("MIC1 PGA", DA732X_REG_MIC1, DA732X_MIC_EN_SHIFT,
827 0, NULL, 0),
828 SND_SOC_DAPM_PGA("MIC2 PGA", DA732X_REG_MIC2, DA732X_MIC_EN_SHIFT,
829 0, NULL, 0),
830 SND_SOC_DAPM_PGA("MIC3 PGA", DA732X_REG_MIC3, DA732X_MIC_EN_SHIFT,
831 0, NULL, 0),
832 SND_SOC_DAPM_PGA("AUX1L PGA", DA732X_REG_AUX1L, DA732X_AUX_EN_SHIFT,
833 0, NULL, 0),
834 SND_SOC_DAPM_PGA("AUX1R PGA", DA732X_REG_AUX1R, DA732X_AUX_EN_SHIFT,
835 0, NULL, 0),
836
837 SND_SOC_DAPM_PGA_E("HP Left", DA732X_REG_HPL, DA732X_HP_OUT_EN_SHIFT,
838 0, NULL, 0, da732x_out_pga_event,
839 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
840 SND_SOC_DAPM_PGA_E("HP Right", DA732X_REG_HPR, DA732X_HP_OUT_EN_SHIFT,
841 0, NULL, 0, da732x_out_pga_event,
842 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
843 SND_SOC_DAPM_PGA_E("LIN2", DA732X_REG_LIN2, DA732X_LIN_OUT_EN_SHIFT,
844 0, NULL, 0, da732x_out_pga_event,
845 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
846 SND_SOC_DAPM_PGA_E("LIN3", DA732X_REG_LIN3, DA732X_LIN_OUT_EN_SHIFT,
847 0, NULL, 0, da732x_out_pga_event,
848 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
849 SND_SOC_DAPM_PGA_E("LIN4", DA732X_REG_LIN4, DA732X_LIN_OUT_EN_SHIFT,
850 0, NULL, 0, da732x_out_pga_event,
851 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
852
853 /* MUXs */
854 SND_SOC_DAPM_MUX("ADC1 Left MUX", SND_SOC_NOPM, 0, 0, &adc1l_mux),
855 SND_SOC_DAPM_MUX("ADC1 Right MUX", SND_SOC_NOPM, 0, 0, &adc1r_mux),
856 SND_SOC_DAPM_MUX("ADC2 Left MUX", SND_SOC_NOPM, 0, 0, &adc2l_mux),
857 SND_SOC_DAPM_MUX("ADC2 Right MUX", SND_SOC_NOPM, 0, 0, &adc2r_mux),
858
859 SND_SOC_DAPM_MUX("HP Left MUX", SND_SOC_NOPM, 0, 0, &hpl_mux),
860 SND_SOC_DAPM_MUX("HP Right MUX", SND_SOC_NOPM, 0, 0, &hpr_mux),
861 SND_SOC_DAPM_MUX("Speaker MUX", SND_SOC_NOPM, 0, 0, &spk_mux),
862 SND_SOC_DAPM_MUX("LOUT2 MUX", SND_SOC_NOPM, 0, 0, &lout2_mux),
863 SND_SOC_DAPM_MUX("LOUT4 MUX", SND_SOC_NOPM, 0, 0, &lout4_mux),
864
865 /* AIF interfaces */
866 SND_SOC_DAPM_AIF_OUT("AIFA Output", "AIFA Capture", 0, DA732X_REG_AIFA3,
867 DA732X_AIF_EN_SHIFT, 0),
868 SND_SOC_DAPM_AIF_IN("AIFA Input", "AIFA Playback", 0, DA732X_REG_AIFA3,
869 DA732X_AIF_EN_SHIFT, 0),
870
871 SND_SOC_DAPM_AIF_OUT("AIFB Output", "AIFB Capture", 0, DA732X_REG_AIFB3,
872 DA732X_AIF_EN_SHIFT, 0),
873 SND_SOC_DAPM_AIF_IN("AIFB Input", "AIFB Playback", 0, DA732X_REG_AIFB3,
874 DA732X_AIF_EN_SHIFT, 0),
875 };
876
877 static const struct snd_soc_dapm_route da732x_dapm_routes[] = {
878 /* Inputs */
879 {"AUX1L PGA", NULL, "AUX1L"},
880 {"AUX1R PGA", NULL, "AUX1R"},
881 {"MIC1 PGA", NULL, "MIC1"},
882 {"MIC2 PGA", NULL, "MIC2"},
883 {"MIC3 PGA", NULL, "MIC3"},
884
885 /* Capture Path */
886 {"ADC1 Left MUX", "MIC1", "MIC1 PGA"},
887 {"ADC1 Left MUX", "AUX1L", "AUX1L PGA"},
888
889 {"ADC1 Right MUX", "AUX1R", "AUX1R PGA"},
890 {"ADC1 Right MUX", "MIC2", "MIC2 PGA"},
891 {"ADC1 Right MUX", "MIC3", "MIC3 PGA"},
892
893 {"ADC2 Left MUX", "AUX1L", "AUX1L PGA"},
894 {"ADC2 Left MUX", "MIC1", "MIC1 PGA"},
895
896 {"ADC2 Right MUX", "AUX1R", "AUX1R PGA"},
897 {"ADC2 Right MUX", "MIC2", "MIC2 PGA"},
898 {"ADC2 Right MUX", "MIC3", "MIC3 PGA"},
899
900 {"ADC1L", NULL, "ADC1 Supply"},
901 {"ADC1R", NULL, "ADC1 Supply"},
902 {"ADC2L", NULL, "ADC2 Supply"},
903 {"ADC2R", NULL, "ADC2 Supply"},
904
905 {"ADC1L", NULL, "ADC1 Left MUX"},
906 {"ADC1R", NULL, "ADC1 Right MUX"},
907 {"ADC2L", NULL, "ADC2 Left MUX"},
908 {"ADC2R", NULL, "ADC2 Right MUX"},
909
910 {"AIFA Output", NULL, "ADC1L"},
911 {"AIFA Output", NULL, "ADC1R"},
912 {"AIFB Output", NULL, "ADC2L"},
913 {"AIFB Output", NULL, "ADC2R"},
914
915 {"HP Left MUX", "Enabled", "AIFA Input"},
916 {"HP Right MUX", "Enabled", "AIFA Input"},
917 {"Speaker MUX", "Enabled", "AIFB Input"},
918 {"LOUT2 MUX", "Enabled", "AIFB Input"},
919 {"LOUT4 MUX", "Enabled", "AIFB Input"},
920
921 {"DAC1L", NULL, "DAC1 CLK"},
922 {"DAC1R", NULL, "DAC1 CLK"},
923 {"DAC2L", NULL, "DAC2 CLK"},
924 {"DAC2R", NULL, "DAC2 CLK"},
925 {"DAC3", NULL, "DAC3 CLK"},
926
927 {"DAC1L", NULL, "HP Left MUX"},
928 {"DAC1R", NULL, "HP Right MUX"},
929 {"DAC2L", NULL, "Speaker MUX"},
930 {"DAC2R", NULL, "LOUT4 MUX"},
931 {"DAC3", NULL, "LOUT2 MUX"},
932
933 /* Output Pgas */
934 {"HP Left", NULL, "DAC1L"},
935 {"HP Right", NULL, "DAC1R"},
936 {"LIN3", NULL, "DAC2L"},
937 {"LIN4", NULL, "DAC2R"},
938 {"LIN2", NULL, "DAC3"},
939
940 /* Outputs */
941 {"ClassD", NULL, "LIN3"},
942 {"LOUTL", NULL, "LIN2"},
943 {"LOUTR", NULL, "LIN4"},
944 {"HPL", NULL, "HP Left"},
945 {"HPR", NULL, "HP Right"},
946 };
947
948 static int da732x_hw_params(struct snd_pcm_substream *substream,
949 struct snd_pcm_hw_params *params,
950 struct snd_soc_dai *dai)
951 {
952 struct snd_soc_codec *codec = dai->codec;
953 u32 aif = 0;
954 u32 reg_aif;
955 u32 fs;
956
957 reg_aif = dai->driver->base;
958
959 switch (params_width(params)) {
960 case 16:
961 aif |= DA732X_AIF_WORD_16;
962 break;
963 case 20:
964 aif |= DA732X_AIF_WORD_20;
965 break;
966 case 24:
967 aif |= DA732X_AIF_WORD_24;
968 break;
969 case 32:
970 aif |= DA732X_AIF_WORD_32;
971 break;
972 default:
973 return -EINVAL;
974 }
975
976 switch (params_rate(params)) {
977 case 8000:
978 fs = DA732X_SR_8KHZ;
979 break;
980 case 11025:
981 fs = DA732X_SR_11_025KHZ;
982 break;
983 case 12000:
984 fs = DA732X_SR_12KHZ;
985 break;
986 case 16000:
987 fs = DA732X_SR_16KHZ;
988 break;
989 case 22050:
990 fs = DA732X_SR_22_05KHZ;
991 break;
992 case 24000:
993 fs = DA732X_SR_24KHZ;
994 break;
995 case 32000:
996 fs = DA732X_SR_32KHZ;
997 break;
998 case 44100:
999 fs = DA732X_SR_44_1KHZ;
1000 break;
1001 case 48000:
1002 fs = DA732X_SR_48KHZ;
1003 break;
1004 case 88100:
1005 fs = DA732X_SR_88_1KHZ;
1006 break;
1007 case 96000:
1008 fs = DA732X_SR_96KHZ;
1009 break;
1010 default:
1011 return -EINVAL;
1012 }
1013
1014 snd_soc_update_bits(codec, reg_aif, DA732X_AIF_WORD_MASK, aif);
1015 snd_soc_update_bits(codec, DA732X_REG_CLK_CTRL, DA732X_SR1_MASK, fs);
1016
1017 return 0;
1018 }
1019
1020 static int da732x_set_dai_fmt(struct snd_soc_dai *dai, u32 fmt)
1021 {
1022 struct snd_soc_codec *codec = dai->codec;
1023 u32 aif_mclk, pc_count;
1024 u32 reg_aif1, aif1;
1025 u32 reg_aif3, aif3;
1026
1027 switch (dai->id) {
1028 case DA732X_DAI_ID1:
1029 reg_aif1 = DA732X_REG_AIFA1;
1030 reg_aif3 = DA732X_REG_AIFA3;
1031 pc_count = DA732X_PC_PULSE_AIFA | DA732X_PC_RESYNC_NOT_AUT |
1032 DA732X_PC_SAME;
1033 break;
1034 case DA732X_DAI_ID2:
1035 reg_aif1 = DA732X_REG_AIFB1;
1036 reg_aif3 = DA732X_REG_AIFB3;
1037 pc_count = DA732X_PC_PULSE_AIFB | DA732X_PC_RESYNC_NOT_AUT |
1038 DA732X_PC_SAME;
1039 break;
1040 default:
1041 return -EINVAL;
1042 }
1043
1044 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1045 case SND_SOC_DAIFMT_CBS_CFS:
1046 aif1 = DA732X_AIF_SLAVE;
1047 aif_mclk = DA732X_AIFM_FRAME_64 | DA732X_AIFM_SRC_SEL_AIFA;
1048 break;
1049 case SND_SOC_DAIFMT_CBM_CFM:
1050 aif1 = DA732X_AIF_CLK_FROM_SRC;
1051 aif_mclk = DA732X_CLK_GENERATION_AIF_A;
1052 break;
1053 default:
1054 return -EINVAL;
1055 }
1056
1057 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1058 case SND_SOC_DAIFMT_I2S:
1059 aif3 = DA732X_AIF_I2S_MODE;
1060 break;
1061 case SND_SOC_DAIFMT_RIGHT_J:
1062 aif3 = DA732X_AIF_RIGHT_J_MODE;
1063 break;
1064 case SND_SOC_DAIFMT_LEFT_J:
1065 aif3 = DA732X_AIF_LEFT_J_MODE;
1066 break;
1067 case SND_SOC_DAIFMT_DSP_B:
1068 aif3 = DA732X_AIF_DSP_MODE;
1069 break;
1070 default:
1071 return -EINVAL;
1072 }
1073
1074 /* Clock inversion */
1075 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1076 case SND_SOC_DAIFMT_DSP_B:
1077 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1078 case SND_SOC_DAIFMT_NB_NF:
1079 break;
1080 case SND_SOC_DAIFMT_IB_NF:
1081 aif3 |= DA732X_AIF_BCLK_INV;
1082 break;
1083 default:
1084 return -EINVAL;
1085 }
1086 break;
1087 case SND_SOC_DAIFMT_I2S:
1088 case SND_SOC_DAIFMT_RIGHT_J:
1089 case SND_SOC_DAIFMT_LEFT_J:
1090 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1091 case SND_SOC_DAIFMT_NB_NF:
1092 break;
1093 case SND_SOC_DAIFMT_IB_IF:
1094 aif3 |= DA732X_AIF_BCLK_INV | DA732X_AIF_WCLK_INV;
1095 break;
1096 case SND_SOC_DAIFMT_IB_NF:
1097 aif3 |= DA732X_AIF_BCLK_INV;
1098 break;
1099 case SND_SOC_DAIFMT_NB_IF:
1100 aif3 |= DA732X_AIF_WCLK_INV;
1101 break;
1102 default:
1103 return -EINVAL;
1104 }
1105 break;
1106 default:
1107 return -EINVAL;
1108 }
1109
1110 snd_soc_write(codec, DA732X_REG_AIF_MCLK, aif_mclk);
1111 snd_soc_update_bits(codec, reg_aif1, DA732X_AIF1_CLK_MASK, aif1);
1112 snd_soc_update_bits(codec, reg_aif3, DA732X_AIF_BCLK_INV |
1113 DA732X_AIF_WCLK_INV | DA732X_AIF_MODE_MASK, aif3);
1114 snd_soc_write(codec, DA732X_REG_PC_CTRL, pc_count);
1115
1116 return 0;
1117 }
1118
1119
1120
1121 static int da732x_set_dai_pll(struct snd_soc_codec *codec, int pll_id,
1122 int source, unsigned int freq_in,
1123 unsigned int freq_out)
1124 {
1125 struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec);
1126 int fref, indiv;
1127 u8 div_lo, div_mid, div_hi;
1128 u64 frac_div;
1129
1130 /* Disable PLL */
1131 if (freq_out == 0) {
1132 snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL,
1133 DA732X_PLL_EN, 0);
1134 da732x->pll_en = false;
1135 return 0;
1136 }
1137
1138 if (da732x->pll_en)
1139 return -EBUSY;
1140
1141 if (source == DA732X_SRCCLK_MCLK) {
1142 /* Validate Sysclk rate */
1143 switch (da732x->sysclk) {
1144 case 11290000:
1145 case 12288000:
1146 case 22580000:
1147 case 24576000:
1148 case 45160000:
1149 case 49152000:
1150 snd_soc_write(codec, DA732X_REG_PLL_CTRL,
1151 DA732X_PLL_BYPASS);
1152 return 0;
1153 default:
1154 dev_err(codec->dev,
1155 "Cannot use PLL Bypass, invalid SYSCLK rate\n");
1156 return -EINVAL;
1157 }
1158 }
1159
1160 indiv = da732x_get_input_div(codec, da732x->sysclk);
1161 if (indiv < 0)
1162 return indiv;
1163
1164 fref = (da732x->sysclk / indiv);
1165 div_hi = freq_out / fref;
1166 frac_div = (u64)(freq_out % fref) * 8192ULL;
1167 do_div(frac_div, fref);
1168 div_mid = (frac_div >> DA732X_1BYTE_SHIFT) & DA732X_U8_MASK;
1169 div_lo = (frac_div) & DA732X_U8_MASK;
1170
1171 snd_soc_write(codec, DA732X_REG_PLL_DIV_LO, div_lo);
1172 snd_soc_write(codec, DA732X_REG_PLL_DIV_MID, div_mid);
1173 snd_soc_write(codec, DA732X_REG_PLL_DIV_HI, div_hi);
1174
1175 snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL, DA732X_PLL_EN,
1176 DA732X_PLL_EN);
1177
1178 da732x->pll_en = true;
1179
1180 return 0;
1181 }
1182
1183 static int da732x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1184 unsigned int freq, int dir)
1185 {
1186 struct snd_soc_codec *codec = dai->codec;
1187 struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec);
1188
1189 da732x->sysclk = freq;
1190
1191 return 0;
1192 }
1193
1194 #define DA732X_RATES SNDRV_PCM_RATE_8000_96000
1195
1196 #define DA732X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1197 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1198
1199 static const struct snd_soc_dai_ops da732x_dai_ops = {
1200 .hw_params = da732x_hw_params,
1201 .set_fmt = da732x_set_dai_fmt,
1202 .set_sysclk = da732x_set_dai_sysclk,
1203 };
1204
1205 static struct snd_soc_dai_driver da732x_dai[] = {
1206 {
1207 .name = "DA732X_AIFA",
1208 .id = DA732X_DAI_ID1,
1209 .base = DA732X_REG_AIFA1,
1210 .playback = {
1211 .stream_name = "AIFA Playback",
1212 .channels_min = 1,
1213 .channels_max = 2,
1214 .rates = DA732X_RATES,
1215 .formats = DA732X_FORMATS,
1216 },
1217 .capture = {
1218 .stream_name = "AIFA Capture",
1219 .channels_min = 1,
1220 .channels_max = 2,
1221 .rates = DA732X_RATES,
1222 .formats = DA732X_FORMATS,
1223 },
1224 .ops = &da732x_dai_ops,
1225 },
1226 {
1227 .name = "DA732X_AIFB",
1228 .id = DA732X_DAI_ID2,
1229 .base = DA732X_REG_AIFB1,
1230 .playback = {
1231 .stream_name = "AIFB Playback",
1232 .channels_min = 1,
1233 .channels_max = 2,
1234 .rates = DA732X_RATES,
1235 .formats = DA732X_FORMATS,
1236 },
1237 .capture = {
1238 .stream_name = "AIFB Capture",
1239 .channels_min = 1,
1240 .channels_max = 2,
1241 .rates = DA732X_RATES,
1242 .formats = DA732X_FORMATS,
1243 },
1244 .ops = &da732x_dai_ops,
1245 },
1246 };
1247
1248 static bool da732x_volatile(struct device *dev, unsigned int reg)
1249 {
1250 switch (reg) {
1251 case DA732X_REG_HPL_DAC_OFF_CNTL:
1252 case DA732X_REG_HPR_DAC_OFF_CNTL:
1253 return true;
1254 default:
1255 return false;
1256 }
1257 }
1258
1259 static const struct regmap_config da732x_regmap = {
1260 .reg_bits = 8,
1261 .val_bits = 8,
1262
1263 .max_register = DA732X_MAX_REG,
1264 .volatile_reg = da732x_volatile,
1265 .reg_defaults = da732x_reg_cache,
1266 .num_reg_defaults = ARRAY_SIZE(da732x_reg_cache),
1267 .cache_type = REGCACHE_RBTREE,
1268 };
1269
1270
1271 static void da732x_dac_offset_adjust(struct snd_soc_codec *codec)
1272 {
1273 u8 offset[DA732X_HP_DACS];
1274 u8 sign[DA732X_HP_DACS];
1275 u8 step = DA732X_DAC_OFFSET_STEP;
1276
1277 /* Initialize DAC offset calibration circuits and registers */
1278 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET,
1279 DA732X_HP_DAC_OFFSET_TRIM_VAL);
1280 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET,
1281 DA732X_HP_DAC_OFFSET_TRIM_VAL);
1282 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFF_CNTL,
1283 DA732X_HP_DAC_OFF_CALIBRATION |
1284 DA732X_HP_DAC_OFF_SCALE_STEPS);
1285 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFF_CNTL,
1286 DA732X_HP_DAC_OFF_CALIBRATION |
1287 DA732X_HP_DAC_OFF_SCALE_STEPS);
1288
1289 /* Wait for voltage stabilization */
1290 msleep(DA732X_WAIT_FOR_STABILIZATION);
1291
1292 /* Check DAC offset sign */
1293 sign[DA732X_HPL_DAC] = (snd_soc_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) &
1294 DA732X_HP_DAC_OFF_CNTL_COMPO);
1295 sign[DA732X_HPR_DAC] = (snd_soc_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) &
1296 DA732X_HP_DAC_OFF_CNTL_COMPO);
1297
1298 /* Binary search DAC offset values (both channels at once) */
1299 offset[DA732X_HPL_DAC] = sign[DA732X_HPL_DAC] << DA732X_HP_DAC_COMPO_SHIFT;
1300 offset[DA732X_HPR_DAC] = sign[DA732X_HPR_DAC] << DA732X_HP_DAC_COMPO_SHIFT;
1301
1302 do {
1303 offset[DA732X_HPL_DAC] |= step;
1304 offset[DA732X_HPR_DAC] |= step;
1305 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET,
1306 ~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK);
1307 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET,
1308 ~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK);
1309
1310 msleep(DA732X_WAIT_FOR_STABILIZATION);
1311
1312 if ((snd_soc_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) &
1313 DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPL_DAC])
1314 offset[DA732X_HPL_DAC] &= ~step;
1315 if ((snd_soc_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) &
1316 DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPR_DAC])
1317 offset[DA732X_HPR_DAC] &= ~step;
1318
1319 step >>= 1;
1320 } while (step);
1321
1322 /* Write final DAC offsets to registers */
1323 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET,
1324 ~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK);
1325 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET,
1326 ~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK);
1327
1328 /* End DAC calibration mode */
1329 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFF_CNTL,
1330 DA732X_HP_DAC_OFF_SCALE_STEPS);
1331 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFF_CNTL,
1332 DA732X_HP_DAC_OFF_SCALE_STEPS);
1333 }
1334
1335 static void da732x_output_offset_adjust(struct snd_soc_codec *codec)
1336 {
1337 u8 offset[DA732X_HP_AMPS];
1338 u8 sign[DA732X_HP_AMPS];
1339 u8 step = DA732X_OUTPUT_OFFSET_STEP;
1340
1341 offset[DA732X_HPL_AMP] = DA732X_HP_OUT_TRIM_VAL;
1342 offset[DA732X_HPR_AMP] = DA732X_HP_OUT_TRIM_VAL;
1343
1344 /* Initialize output offset calibration circuits and registers */
1345 snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL);
1346 snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL);
1347 snd_soc_write(codec, DA732X_REG_HPL,
1348 DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN);
1349 snd_soc_write(codec, DA732X_REG_HPR,
1350 DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN);
1351
1352 /* Wait for voltage stabilization */
1353 msleep(DA732X_WAIT_FOR_STABILIZATION);
1354
1355 /* Check output offset sign */
1356 sign[DA732X_HPL_AMP] = snd_soc_read(codec, DA732X_REG_HPL) &
1357 DA732X_HP_OUT_COMPO;
1358 sign[DA732X_HPR_AMP] = snd_soc_read(codec, DA732X_REG_HPR) &
1359 DA732X_HP_OUT_COMPO;
1360
1361 snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_OUT_COMP |
1362 (sign[DA732X_HPL_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) |
1363 DA732X_HP_OUT_EN);
1364 snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_OUT_COMP |
1365 (sign[DA732X_HPR_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) |
1366 DA732X_HP_OUT_EN);
1367
1368 /* Binary search output offset values (both channels at once) */
1369 do {
1370 offset[DA732X_HPL_AMP] |= step;
1371 offset[DA732X_HPR_AMP] |= step;
1372 snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET,
1373 offset[DA732X_HPL_AMP]);
1374 snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET,
1375 offset[DA732X_HPR_AMP]);
1376
1377 msleep(DA732X_WAIT_FOR_STABILIZATION);
1378
1379 if ((snd_soc_read(codec, DA732X_REG_HPL) &
1380 DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPL_AMP])
1381 offset[DA732X_HPL_AMP] &= ~step;
1382 if ((snd_soc_read(codec, DA732X_REG_HPR) &
1383 DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPR_AMP])
1384 offset[DA732X_HPR_AMP] &= ~step;
1385
1386 step >>= 1;
1387 } while (step);
1388
1389 /* Write final DAC offsets to registers */
1390 snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET, offset[DA732X_HPL_AMP]);
1391 snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET, offset[DA732X_HPR_AMP]);
1392 }
1393
1394 static void da732x_hp_dc_offset_cancellation(struct snd_soc_codec *codec)
1395 {
1396 /* Make sure that we have Soft Mute enabled */
1397 snd_soc_write(codec, DA732X_REG_DAC1_SOFTMUTE, DA732X_SOFTMUTE_EN |
1398 DA732X_GAIN_RAMPED | DA732X_16_SAMPLES);
1399 snd_soc_write(codec, DA732X_REG_DAC1_SEL, DA732X_DACL_EN |
1400 DA732X_DACR_EN | DA732X_DACL_SDM | DA732X_DACR_SDM |
1401 DA732X_DACL_MUTE | DA732X_DACR_MUTE);
1402 snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN |
1403 DA732X_HP_OUT_MUTE | DA732X_HP_OUT_EN);
1404 snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_OUT_EN |
1405 DA732X_HP_OUT_MUTE | DA732X_HP_OUT_DAC_EN);
1406
1407 da732x_dac_offset_adjust(codec);
1408 da732x_output_offset_adjust(codec);
1409
1410 snd_soc_write(codec, DA732X_REG_DAC1_SEL, DA732X_DACS_DIS);
1411 snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_DIS);
1412 snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_DIS);
1413 }
1414
1415 static int da732x_set_bias_level(struct snd_soc_codec *codec,
1416 enum snd_soc_bias_level level)
1417 {
1418 struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec);
1419
1420 switch (level) {
1421 case SND_SOC_BIAS_ON:
1422 snd_soc_update_bits(codec, DA732X_REG_BIAS_EN,
1423 DA732X_BIAS_BOOST_MASK,
1424 DA732X_BIAS_BOOST_100PC);
1425 break;
1426 case SND_SOC_BIAS_PREPARE:
1427 break;
1428 case SND_SOC_BIAS_STANDBY:
1429 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1430 /* Init Codec */
1431 snd_soc_write(codec, DA732X_REG_REF1,
1432 DA732X_VMID_FASTCHG);
1433 snd_soc_write(codec, DA732X_REG_BIAS_EN,
1434 DA732X_BIAS_EN);
1435
1436 mdelay(DA732X_STARTUP_DELAY);
1437
1438 /* Disable Fast Charge and enable DAC ref voltage */
1439 snd_soc_write(codec, DA732X_REG_REF1,
1440 DA732X_REFBUFX2_EN);
1441
1442 /* Enable bypass DSP routing */
1443 snd_soc_write(codec, DA732X_REG_DATA_ROUTE,
1444 DA732X_BYPASS_DSP);
1445
1446 /* Enable Digital subsystem */
1447 snd_soc_write(codec, DA732X_REG_DSP_CTRL,
1448 DA732X_DIGITAL_EN);
1449
1450 snd_soc_write(codec, DA732X_REG_SPARE1_OUT,
1451 DA732X_HP_DRIVER_EN |
1452 DA732X_HP_GATE_LOW |
1453 DA732X_HP_LOOP_GAIN_CTRL);
1454 snd_soc_write(codec, DA732X_REG_HP_LIN1_GNDSEL,
1455 DA732X_HP_OUT_GNDSEL);
1456
1457 da732x_set_charge_pump(codec, DA732X_ENABLE_CP);
1458
1459 snd_soc_write(codec, DA732X_REG_CLK_EN1,
1460 DA732X_SYS3_CLK_EN | DA732X_PC_CLK_EN);
1461
1462 /* Enable Zero Crossing */
1463 snd_soc_write(codec, DA732X_REG_INP_ZC_EN,
1464 DA732X_MIC1_PRE_ZC_EN |
1465 DA732X_MIC1_ZC_EN |
1466 DA732X_MIC2_PRE_ZC_EN |
1467 DA732X_MIC2_ZC_EN |
1468 DA732X_AUXL_ZC_EN |
1469 DA732X_AUXR_ZC_EN |
1470 DA732X_MIC3_PRE_ZC_EN |
1471 DA732X_MIC3_ZC_EN);
1472 snd_soc_write(codec, DA732X_REG_OUT_ZC_EN,
1473 DA732X_HPL_ZC_EN | DA732X_HPR_ZC_EN |
1474 DA732X_LIN2_ZC_EN | DA732X_LIN3_ZC_EN |
1475 DA732X_LIN4_ZC_EN);
1476
1477 da732x_hp_dc_offset_cancellation(codec);
1478
1479 regcache_cache_only(da732x->regmap, false);
1480 regcache_sync(da732x->regmap);
1481 } else {
1482 snd_soc_update_bits(codec, DA732X_REG_BIAS_EN,
1483 DA732X_BIAS_BOOST_MASK,
1484 DA732X_BIAS_BOOST_50PC);
1485 snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL,
1486 DA732X_PLL_EN, 0);
1487 da732x->pll_en = false;
1488 }
1489 break;
1490 case SND_SOC_BIAS_OFF:
1491 regcache_cache_only(da732x->regmap, true);
1492 da732x_set_charge_pump(codec, DA732X_DISABLE_CP);
1493 snd_soc_update_bits(codec, DA732X_REG_BIAS_EN, DA732X_BIAS_EN,
1494 DA732X_BIAS_DIS);
1495 da732x->pll_en = false;
1496 break;
1497 }
1498
1499 return 0;
1500 }
1501
1502 static const struct snd_soc_codec_driver soc_codec_dev_da732x = {
1503 .set_bias_level = da732x_set_bias_level,
1504 .component_driver = {
1505 .controls = da732x_snd_controls,
1506 .num_controls = ARRAY_SIZE(da732x_snd_controls),
1507 .dapm_widgets = da732x_dapm_widgets,
1508 .num_dapm_widgets = ARRAY_SIZE(da732x_dapm_widgets),
1509 .dapm_routes = da732x_dapm_routes,
1510 .num_dapm_routes = ARRAY_SIZE(da732x_dapm_routes),
1511 },
1512 .set_pll = da732x_set_dai_pll,
1513 };
1514
1515 static int da732x_i2c_probe(struct i2c_client *i2c,
1516 const struct i2c_device_id *id)
1517 {
1518 struct da732x_priv *da732x;
1519 unsigned int reg;
1520 int ret;
1521
1522 da732x = devm_kzalloc(&i2c->dev, sizeof(struct da732x_priv),
1523 GFP_KERNEL);
1524 if (!da732x)
1525 return -ENOMEM;
1526
1527 i2c_set_clientdata(i2c, da732x);
1528
1529 da732x->regmap = devm_regmap_init_i2c(i2c, &da732x_regmap);
1530 if (IS_ERR(da732x->regmap)) {
1531 ret = PTR_ERR(da732x->regmap);
1532 dev_err(&i2c->dev, "Failed to initialize regmap\n");
1533 goto err;
1534 }
1535
1536 ret = regmap_read(da732x->regmap, DA732X_REG_ID, &reg);
1537 if (ret < 0) {
1538 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
1539 goto err;
1540 }
1541
1542 dev_info(&i2c->dev, "Revision: %d.%d\n",
1543 (reg & DA732X_ID_MAJOR_MASK) >> 4,
1544 (reg & DA732X_ID_MINOR_MASK));
1545
1546 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_da732x,
1547 da732x_dai, ARRAY_SIZE(da732x_dai));
1548 if (ret != 0)
1549 dev_err(&i2c->dev, "Failed to register codec.\n");
1550
1551 err:
1552 return ret;
1553 }
1554
1555 static int da732x_i2c_remove(struct i2c_client *client)
1556 {
1557 snd_soc_unregister_codec(&client->dev);
1558
1559 return 0;
1560 }
1561
1562 static const struct i2c_device_id da732x_i2c_id[] = {
1563 { "da7320", 0},
1564 { }
1565 };
1566 MODULE_DEVICE_TABLE(i2c, da732x_i2c_id);
1567
1568 static struct i2c_driver da732x_i2c_driver = {
1569 .driver = {
1570 .name = "da7320",
1571 },
1572 .probe = da732x_i2c_probe,
1573 .remove = da732x_i2c_remove,
1574 .id_table = da732x_i2c_id,
1575 };
1576
1577 module_i2c_driver(da732x_i2c_driver);
1578
1579
1580 MODULE_DESCRIPTION("ASoC DA732X driver");
1581 MODULE_AUTHOR("Michal Hajduk <michal.hajduk@diasemi.com>");
1582 MODULE_LICENSE("GPL");
CRIS linux kernel tree