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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / sound / soc / codecs / wm8903.c
blobcba90f21161fbd2553f39d6aac9756350015a186
1 /*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008-12 Wolfson Microelectronics
5 * Copyright 2011-2012 NVIDIA, Inc.
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
15 * - Digital microphone support.
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/pm.h>
25 #include <linux/i2c.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/slab.h>
29 #include <linux/irq.h>
30 #include <linux/mutex.h>
31 #include <sound/core.h>
32 #include <sound/jack.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/tlv.h>
36 #include <sound/soc.h>
37 #include <sound/initval.h>
38 #include <sound/wm8903.h>
39 #include <trace/events/asoc.h>
40
41 #include "wm8903.h"
42
43 /* Register defaults at reset */
44 static const struct reg_default wm8903_reg_defaults[] = {
45 { 4, 0x0018 }, /* R4 - Bias Control 0 */
46 { 5, 0x0000 }, /* R5 - VMID Control 0 */
47 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
48 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
49 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
50 { 12, 0x0000 }, /* R12 - Power Management 0 */
51 { 13, 0x0000 }, /* R13 - Power Management 1 */
52 { 14, 0x0000 }, /* R14 - Power Management 2 */
53 { 15, 0x0000 }, /* R15 - Power Management 3 */
54 { 16, 0x0000 }, /* R16 - Power Management 4 */
55 { 17, 0x0000 }, /* R17 - Power Management 5 */
56 { 18, 0x0000 }, /* R18 - Power Management 6 */
57 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
58 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
59 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
60 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
61 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
62 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
63 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
64 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
65 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
66 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
67 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
68 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
69 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
70 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
71 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
72 { 40, 0x09BF }, /* R40 - DRC 0 */
73 { 41, 0x3241 }, /* R41 - DRC 1 */
74 { 42, 0x0020 }, /* R42 - DRC 2 */
75 { 43, 0x0000 }, /* R43 - DRC 3 */
76 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
77 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
78 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
79 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
80 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
81 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
82 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
83 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
84 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
85 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
86 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
87 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
88 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
89 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
90 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
91 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
92 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
93 { 67, 0x0010 }, /* R67 - DC Servo 0 */
94 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
95 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
96 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
97 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
98 { 104, 0x0000 }, /* R104 - Class W 0 */
99 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
100 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
101 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
102 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
103 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
104 { 114, 0x0000 }, /* R114 - Control Interface */
105 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
106 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
107 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
108 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
109 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
110 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
111 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
112 { 126, 0x0000 }, /* R126 - Interrupt Control */
113 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
114 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
115 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
116 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
117 };
118
119 #define WM8903_NUM_SUPPLIES 4
120 static const char *wm8903_supply_names[WM8903_NUM_SUPPLIES] = {
121 "AVDD",
122 "CPVDD",
123 "DBVDD",
124 "DCVDD",
125 };
126
127 struct wm8903_priv {
128 struct wm8903_platform_data *pdata;
129 struct device *dev;
130 struct regmap *regmap;
131 struct regulator_bulk_data supplies[WM8903_NUM_SUPPLIES];
132
133 int sysclk;
134 int irq;
135
136 struct mutex lock;
137 int fs;
138 int deemph;
139
140 int dcs_pending;
141 int dcs_cache[4];
142
143 /* Reference count */
144 int class_w_users;
145
146 struct snd_soc_jack *mic_jack;
147 int mic_det;
148 int mic_short;
149 int mic_last_report;
150 int mic_delay;
151
152 #ifdef CONFIG_GPIOLIB
153 struct gpio_chip gpio_chip;
154 #endif
155 };
156
157 static bool wm8903_readable_register(struct device *dev, unsigned int reg)
158 {
159 switch (reg) {
160 case WM8903_SW_RESET_AND_ID:
161 case WM8903_REVISION_NUMBER:
162 case WM8903_BIAS_CONTROL_0:
163 case WM8903_VMID_CONTROL_0:
164 case WM8903_MIC_BIAS_CONTROL_0:
165 case WM8903_ANALOGUE_DAC_0:
166 case WM8903_ANALOGUE_ADC_0:
167 case WM8903_POWER_MANAGEMENT_0:
168 case WM8903_POWER_MANAGEMENT_1:
169 case WM8903_POWER_MANAGEMENT_2:
170 case WM8903_POWER_MANAGEMENT_3:
171 case WM8903_POWER_MANAGEMENT_4:
172 case WM8903_POWER_MANAGEMENT_5:
173 case WM8903_POWER_MANAGEMENT_6:
174 case WM8903_CLOCK_RATES_0:
175 case WM8903_CLOCK_RATES_1:
176 case WM8903_CLOCK_RATES_2:
177 case WM8903_AUDIO_INTERFACE_0:
178 case WM8903_AUDIO_INTERFACE_1:
179 case WM8903_AUDIO_INTERFACE_2:
180 case WM8903_AUDIO_INTERFACE_3:
181 case WM8903_DAC_DIGITAL_VOLUME_LEFT:
182 case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
183 case WM8903_DAC_DIGITAL_0:
184 case WM8903_DAC_DIGITAL_1:
185 case WM8903_ADC_DIGITAL_VOLUME_LEFT:
186 case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
187 case WM8903_ADC_DIGITAL_0:
188 case WM8903_DIGITAL_MICROPHONE_0:
189 case WM8903_DRC_0:
190 case WM8903_DRC_1:
191 case WM8903_DRC_2:
192 case WM8903_DRC_3:
193 case WM8903_ANALOGUE_LEFT_INPUT_0:
194 case WM8903_ANALOGUE_RIGHT_INPUT_0:
195 case WM8903_ANALOGUE_LEFT_INPUT_1:
196 case WM8903_ANALOGUE_RIGHT_INPUT_1:
197 case WM8903_ANALOGUE_LEFT_MIX_0:
198 case WM8903_ANALOGUE_RIGHT_MIX_0:
199 case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
200 case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
201 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
202 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
203 case WM8903_ANALOGUE_OUT1_LEFT:
204 case WM8903_ANALOGUE_OUT1_RIGHT:
205 case WM8903_ANALOGUE_OUT2_LEFT:
206 case WM8903_ANALOGUE_OUT2_RIGHT:
207 case WM8903_ANALOGUE_OUT3_LEFT:
208 case WM8903_ANALOGUE_OUT3_RIGHT:
209 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
210 case WM8903_DC_SERVO_0:
211 case WM8903_DC_SERVO_2:
212 case WM8903_DC_SERVO_READBACK_1:
213 case WM8903_DC_SERVO_READBACK_2:
214 case WM8903_DC_SERVO_READBACK_3:
215 case WM8903_DC_SERVO_READBACK_4:
216 case WM8903_ANALOGUE_HP_0:
217 case WM8903_ANALOGUE_LINEOUT_0:
218 case WM8903_CHARGE_PUMP_0:
219 case WM8903_CLASS_W_0:
220 case WM8903_WRITE_SEQUENCER_0:
221 case WM8903_WRITE_SEQUENCER_1:
222 case WM8903_WRITE_SEQUENCER_2:
223 case WM8903_WRITE_SEQUENCER_3:
224 case WM8903_WRITE_SEQUENCER_4:
225 case WM8903_CONTROL_INTERFACE:
226 case WM8903_GPIO_CONTROL_1:
227 case WM8903_GPIO_CONTROL_2:
228 case WM8903_GPIO_CONTROL_3:
229 case WM8903_GPIO_CONTROL_4:
230 case WM8903_GPIO_CONTROL_5:
231 case WM8903_INTERRUPT_STATUS_1:
232 case WM8903_INTERRUPT_STATUS_1_MASK:
233 case WM8903_INTERRUPT_POLARITY_1:
234 case WM8903_INTERRUPT_CONTROL:
235 case WM8903_CLOCK_RATE_TEST_4:
236 case WM8903_ANALOGUE_OUTPUT_BIAS_0:
237 return true;
238 default:
239 return false;
240 }
241 }
242
243 static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
244 {
245 switch (reg) {
246 case WM8903_SW_RESET_AND_ID:
247 case WM8903_REVISION_NUMBER:
248 case WM8903_INTERRUPT_STATUS_1:
249 case WM8903_WRITE_SEQUENCER_4:
250 case WM8903_DC_SERVO_READBACK_1:
251 case WM8903_DC_SERVO_READBACK_2:
252 case WM8903_DC_SERVO_READBACK_3:
253 case WM8903_DC_SERVO_READBACK_4:
254 return 1;
255
256 default:
257 return 0;
258 }
259 }
260
261 static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
262 struct snd_kcontrol *kcontrol, int event)
263 {
264 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
265 mdelay(4);
266
267 return 0;
268 }
269
270 static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
271 struct snd_kcontrol *kcontrol, int event)
272 {
273 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
274 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
275
276 switch (event) {
277 case SND_SOC_DAPM_POST_PMU:
278 wm8903->dcs_pending |= 1 << w->shift;
279 break;
280 case SND_SOC_DAPM_PRE_PMD:
281 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
282 1 << w->shift, 0);
283 break;
284 }
285
286 return 0;
287 }
288
289 #define WM8903_DCS_MODE_WRITE_STOP 0
290 #define WM8903_DCS_MODE_START_STOP 2
291
292 static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
293 enum snd_soc_dapm_type event, int subseq)
294 {
295 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
296 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
297 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
298 int i, val;
299
300 /* Complete any pending DC servo starts */
301 if (wm8903->dcs_pending) {
302 dev_dbg(codec->dev, "Starting DC servo for %x\n",
303 wm8903->dcs_pending);
304
305 /* If we've no cached values then we need to do startup */
306 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
307 if (!(wm8903->dcs_pending & (1 << i)))
308 continue;
309
310 if (wm8903->dcs_cache[i]) {
311 dev_dbg(codec->dev,
312 "Restore DC servo %d value %x\n",
313 3 - i, wm8903->dcs_cache[i]);
314
315 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
316 wm8903->dcs_cache[i] & 0xff);
317 } else {
318 dev_dbg(codec->dev,
319 "Calibrate DC servo %d\n", 3 - i);
320 dcs_mode = WM8903_DCS_MODE_START_STOP;
321 }
322 }
323
324 /* Don't trust the cache for analogue */
325 if (wm8903->class_w_users)
326 dcs_mode = WM8903_DCS_MODE_START_STOP;
327
328 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
329 WM8903_DCS_MODE_MASK, dcs_mode);
330
331 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
332 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
333
334 switch (dcs_mode) {
335 case WM8903_DCS_MODE_WRITE_STOP:
336 break;
337
338 case WM8903_DCS_MODE_START_STOP:
339 msleep(270);
340
341 /* Cache the measured offsets for digital */
342 if (wm8903->class_w_users)
343 break;
344
345 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
346 if (!(wm8903->dcs_pending & (1 << i)))
347 continue;
348
349 val = snd_soc_read(codec,
350 WM8903_DC_SERVO_READBACK_1 + i);
351 dev_dbg(codec->dev, "DC servo %d: %x\n",
352 3 - i, val);
353 wm8903->dcs_cache[i] = val;
354 }
355 break;
356
357 default:
358 pr_warn("DCS mode %d delay not set\n", dcs_mode);
359 break;
360 }
361
362 wm8903->dcs_pending = 0;
363 }
364 }
365
366 /*
367 * When used with DAC outputs only the WM8903 charge pump supports
368 * operation in class W mode, providing very low power consumption
369 * when used with digital sources. Enable and disable this mode
370 * automatically depending on the mixer configuration.
371 *
372 * All the relevant controls are simple switches.
373 */
374 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol)
376 {
377 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
378 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
379 u16 reg;
380 int ret;
381
382 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
383
384 /* Turn it off if we're about to enable bypass */
385 if (ucontrol->value.integer.value[0]) {
386 if (wm8903->class_w_users == 0) {
387 dev_dbg(codec->dev, "Disabling Class W\n");
388 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
389 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
390 }
391 wm8903->class_w_users++;
392 }
393
394 /* Implement the change */
395 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
396
397 /* If we've just disabled the last bypass path turn Class W on */
398 if (!ucontrol->value.integer.value[0]) {
399 if (wm8903->class_w_users == 1) {
400 dev_dbg(codec->dev, "Enabling Class W\n");
401 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
402 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
403 }
404 wm8903->class_w_users--;
405 }
406
407 dev_dbg(codec->dev, "Bypass use count now %d\n",
408 wm8903->class_w_users);
409
410 return ret;
411 }
412
413 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
414 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
415 snd_soc_dapm_get_volsw, wm8903_class_w_put)
416
417
418 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
419
420 static int wm8903_set_deemph(struct snd_soc_codec *codec)
421 {
422 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
423 int val, i, best;
424
425 /* If we're using deemphasis select the nearest available sample
426 * rate.
427 */
428 if (wm8903->deemph) {
429 best = 1;
430 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
431 if (abs(wm8903_deemph[i] - wm8903->fs) <
432 abs(wm8903_deemph[best] - wm8903->fs))
433 best = i;
434 }
435
436 val = best << WM8903_DEEMPH_SHIFT;
437 } else {
438 best = 0;
439 val = 0;
440 }
441
442 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
443 best, wm8903_deemph[best]);
444
445 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
446 WM8903_DEEMPH_MASK, val);
447 }
448
449 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
450 struct snd_ctl_elem_value *ucontrol)
451 {
452 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
453 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
454
455 ucontrol->value.integer.value[0] = wm8903->deemph;
456
457 return 0;
458 }
459
460 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
461 struct snd_ctl_elem_value *ucontrol)
462 {
463 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
464 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
465 unsigned int deemph = ucontrol->value.integer.value[0];
466 int ret = 0;
467
468 if (deemph > 1)
469 return -EINVAL;
470
471 mutex_lock(&wm8903->lock);
472 if (wm8903->deemph != deemph) {
473 wm8903->deemph = deemph;
474
475 wm8903_set_deemph(codec);
476
477 ret = 1;
478 }
479 mutex_unlock(&wm8903->lock);
480
481 return ret;
482 }
483
484 /* ALSA can only do steps of .01dB */
485 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
486
487 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
488
489 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
490 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
491
492 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
493 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
494 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
495 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
496 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
497
498 static const char *hpf_mode_text[] = {
499 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
500 };
501
502 static SOC_ENUM_SINGLE_DECL(hpf_mode,
503 WM8903_ADC_DIGITAL_0, 5, hpf_mode_text);
504
505 static const char *osr_text[] = {
506 "Low power", "High performance"
507 };
508
509 static SOC_ENUM_SINGLE_DECL(adc_osr,
510 WM8903_ANALOGUE_ADC_0, 0, osr_text);
511
512 static SOC_ENUM_SINGLE_DECL(dac_osr,
513 WM8903_DAC_DIGITAL_1, 0, osr_text);
514
515 static const char *drc_slope_text[] = {
516 "1", "1/2", "1/4", "1/8", "1/16", "0"
517 };
518
519 static SOC_ENUM_SINGLE_DECL(drc_slope_r0,
520 WM8903_DRC_2, 3, drc_slope_text);
521
522 static SOC_ENUM_SINGLE_DECL(drc_slope_r1,
523 WM8903_DRC_2, 0, drc_slope_text);
524
525 static const char *drc_attack_text[] = {
526 "instantaneous",
527 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
528 "46.4ms", "92.8ms", "185.6ms"
529 };
530
531 static SOC_ENUM_SINGLE_DECL(drc_attack,
532 WM8903_DRC_1, 12, drc_attack_text);
533
534 static const char *drc_decay_text[] = {
535 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
536 "23.87s", "47.56s"
537 };
538
539 static SOC_ENUM_SINGLE_DECL(drc_decay,
540 WM8903_DRC_1, 8, drc_decay_text);
541
542 static const char *drc_ff_delay_text[] = {
543 "5 samples", "9 samples"
544 };
545
546 static SOC_ENUM_SINGLE_DECL(drc_ff_delay,
547 WM8903_DRC_0, 5, drc_ff_delay_text);
548
549 static const char *drc_qr_decay_text[] = {
550 "0.725ms", "1.45ms", "5.8ms"
551 };
552
553 static SOC_ENUM_SINGLE_DECL(drc_qr_decay,
554 WM8903_DRC_1, 4, drc_qr_decay_text);
555
556 static const char *drc_smoothing_text[] = {
557 "Low", "Medium", "High"
558 };
559
560 static SOC_ENUM_SINGLE_DECL(drc_smoothing,
561 WM8903_DRC_0, 11, drc_smoothing_text);
562
563 static const char *soft_mute_text[] = {
564 "Fast (fs/2)", "Slow (fs/32)"
565 };
566
567 static SOC_ENUM_SINGLE_DECL(soft_mute,
568 WM8903_DAC_DIGITAL_1, 10, soft_mute_text);
569
570 static const char *mute_mode_text[] = {
571 "Hard", "Soft"
572 };
573
574 static SOC_ENUM_SINGLE_DECL(mute_mode,
575 WM8903_DAC_DIGITAL_1, 9, mute_mode_text);
576
577 static const char *companding_text[] = {
578 "ulaw", "alaw"
579 };
580
581 static SOC_ENUM_SINGLE_DECL(dac_companding,
582 WM8903_AUDIO_INTERFACE_0, 0, companding_text);
583
584 static SOC_ENUM_SINGLE_DECL(adc_companding,
585 WM8903_AUDIO_INTERFACE_0, 2, companding_text);
586
587 static const char *input_mode_text[] = {
588 "Single-Ended", "Differential Line", "Differential Mic"
589 };
590
591 static SOC_ENUM_SINGLE_DECL(linput_mode_enum,
592 WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text);
593
594 static SOC_ENUM_SINGLE_DECL(rinput_mode_enum,
595 WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text);
596
597 static const char *linput_mux_text[] = {
598 "IN1L", "IN2L", "IN3L"
599 };
600
601 static SOC_ENUM_SINGLE_DECL(linput_enum,
602 WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text);
603
604 static SOC_ENUM_SINGLE_DECL(linput_inv_enum,
605 WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text);
606
607 static const char *rinput_mux_text[] = {
608 "IN1R", "IN2R", "IN3R"
609 };
610
611 static SOC_ENUM_SINGLE_DECL(rinput_enum,
612 WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text);
613
614 static SOC_ENUM_SINGLE_DECL(rinput_inv_enum,
615 WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text);
616
617
618 static const char *sidetone_text[] = {
619 "None", "Left", "Right"
620 };
621
622 static SOC_ENUM_SINGLE_DECL(lsidetone_enum,
623 WM8903_DAC_DIGITAL_0, 2, sidetone_text);
624
625 static SOC_ENUM_SINGLE_DECL(rsidetone_enum,
626 WM8903_DAC_DIGITAL_0, 0, sidetone_text);
627
628 static const char *adcinput_text[] = {
629 "ADC", "DMIC"
630 };
631
632 static SOC_ENUM_SINGLE_DECL(adcinput_enum,
633 WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text);
634
635 static const char *aif_text[] = {
636 "Left", "Right"
637 };
638
639 static SOC_ENUM_SINGLE_DECL(lcapture_enum,
640 WM8903_AUDIO_INTERFACE_0, 7, aif_text);
641
642 static SOC_ENUM_SINGLE_DECL(rcapture_enum,
643 WM8903_AUDIO_INTERFACE_0, 6, aif_text);
644
645 static SOC_ENUM_SINGLE_DECL(lplay_enum,
646 WM8903_AUDIO_INTERFACE_0, 5, aif_text);
647
648 static SOC_ENUM_SINGLE_DECL(rplay_enum,
649 WM8903_AUDIO_INTERFACE_0, 4, aif_text);
650
651 static const struct snd_kcontrol_new wm8903_snd_controls[] = {
652
653 /* Input PGAs - No TLV since the scale depends on PGA mode */
654 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
655 7, 1, 1),
656 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
657 0, 31, 0),
658 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
659 6, 1, 0),
660
661 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
662 7, 1, 1),
663 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
664 0, 31, 0),
665 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
666 6, 1, 0),
667
668 /* ADCs */
669 SOC_ENUM("ADC OSR", adc_osr),
670 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
671 SOC_ENUM("HPF Mode", hpf_mode),
672 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
673 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
674 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
675 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
676 drc_tlv_thresh),
677 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
678 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
679 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
680 SOC_ENUM("DRC Attack Rate", drc_attack),
681 SOC_ENUM("DRC Decay Rate", drc_decay),
682 SOC_ENUM("DRC FF Delay", drc_ff_delay),
683 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
684 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
685 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
686 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
687 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
688 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
689 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
690 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
691
692 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
693 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
694 SOC_ENUM("ADC Companding Mode", adc_companding),
695 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
696
697 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
698 12, 0, digital_sidetone_tlv),
699
700 /* DAC */
701 SOC_ENUM("DAC OSR", dac_osr),
702 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
703 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
704 SOC_ENUM("DAC Soft Mute Rate", soft_mute),
705 SOC_ENUM("DAC Mute Mode", mute_mode),
706 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
707 SOC_ENUM("DAC Companding Mode", dac_companding),
708 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
709 SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0,
710 dac_boost_tlv),
711 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
712 wm8903_get_deemph, wm8903_put_deemph),
713
714 /* Headphones */
715 SOC_DOUBLE_R("Headphone Switch",
716 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
717 8, 1, 1),
718 SOC_DOUBLE_R("Headphone ZC Switch",
719 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
720 6, 1, 0),
721 SOC_DOUBLE_R_TLV("Headphone Volume",
722 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
723 0, 63, 0, out_tlv),
724
725 /* Line out */
726 SOC_DOUBLE_R("Line Out Switch",
727 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
728 8, 1, 1),
729 SOC_DOUBLE_R("Line Out ZC Switch",
730 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
731 6, 1, 0),
732 SOC_DOUBLE_R_TLV("Line Out Volume",
733 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
734 0, 63, 0, out_tlv),
735
736 /* Speaker */
737 SOC_DOUBLE_R("Speaker Switch",
738 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
739 SOC_DOUBLE_R("Speaker ZC Switch",
740 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
741 SOC_DOUBLE_R_TLV("Speaker Volume",
742 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
743 0, 63, 0, out_tlv),
744 };
745
746 static const struct snd_kcontrol_new linput_mode_mux =
747 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
748
749 static const struct snd_kcontrol_new rinput_mode_mux =
750 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
751
752 static const struct snd_kcontrol_new linput_mux =
753 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
754
755 static const struct snd_kcontrol_new linput_inv_mux =
756 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
757
758 static const struct snd_kcontrol_new rinput_mux =
759 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
760
761 static const struct snd_kcontrol_new rinput_inv_mux =
762 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
763
764 static const struct snd_kcontrol_new lsidetone_mux =
765 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
766
767 static const struct snd_kcontrol_new rsidetone_mux =
768 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
769
770 static const struct snd_kcontrol_new adcinput_mux =
771 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
772
773 static const struct snd_kcontrol_new lcapture_mux =
774 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
775
776 static const struct snd_kcontrol_new rcapture_mux =
777 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
778
779 static const struct snd_kcontrol_new lplay_mux =
780 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
781
782 static const struct snd_kcontrol_new rplay_mux =
783 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
784
785 static const struct snd_kcontrol_new left_output_mixer[] = {
786 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
787 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
788 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
789 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
790 };
791
792 static const struct snd_kcontrol_new right_output_mixer[] = {
793 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
794 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
795 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
796 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
797 };
798
799 static const struct snd_kcontrol_new left_speaker_mixer[] = {
800 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
801 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
802 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
803 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
804 0, 1, 0),
805 };
806
807 static const struct snd_kcontrol_new right_speaker_mixer[] = {
808 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
809 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
810 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
811 1, 1, 0),
812 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
813 0, 1, 0),
814 };
815
816 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
817 SND_SOC_DAPM_INPUT("IN1L"),
818 SND_SOC_DAPM_INPUT("IN1R"),
819 SND_SOC_DAPM_INPUT("IN2L"),
820 SND_SOC_DAPM_INPUT("IN2R"),
821 SND_SOC_DAPM_INPUT("IN3L"),
822 SND_SOC_DAPM_INPUT("IN3R"),
823 SND_SOC_DAPM_INPUT("DMICDAT"),
824
825 SND_SOC_DAPM_OUTPUT("HPOUTL"),
826 SND_SOC_DAPM_OUTPUT("HPOUTR"),
827 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
828 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
829 SND_SOC_DAPM_OUTPUT("LOP"),
830 SND_SOC_DAPM_OUTPUT("LON"),
831 SND_SOC_DAPM_OUTPUT("ROP"),
832 SND_SOC_DAPM_OUTPUT("RON"),
833
834 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
835
836 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
837 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
838 &linput_inv_mux),
839 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
840
841 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
842 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
843 &rinput_inv_mux),
844 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
845
846 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
847 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
848
849 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
850 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
851
852 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
853 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
854
855 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
856 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
857
858 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
859 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
860
861 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
862 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
863
864 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
865 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
866
867 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
868 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
869
870 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
871 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
872
873 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
874 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
875 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
876 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
877
878 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
879 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
880 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
881 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
882
883 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
884 1, 0, NULL, 0),
885 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
886 0, 0, NULL, 0),
887
888 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
889 NULL, 0),
890 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
891 NULL, 0),
892
893 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
894 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
895 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
896 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
897 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
898 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
899 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
900 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
901
902 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
903 NULL, 0),
904 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
905 NULL, 0),
906 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
907 NULL, 0),
908 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
909 NULL, 0),
910 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
911 NULL, 0),
912 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
913 NULL, 0),
914 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
915 NULL, 0),
916 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
917 NULL, 0),
918
919 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
920 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
921 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
922 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
923 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
924 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
925 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
926 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
927 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
928
929 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
930 NULL, 0),
931 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
932 NULL, 0),
933
934 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
935 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
936 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
937 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
938 };
939
940 static const struct snd_soc_dapm_route wm8903_intercon[] = {
941
942 { "CLK_DSP", NULL, "CLK_SYS" },
943 { "MICBIAS", NULL, "CLK_SYS" },
944 { "HPL_DCS", NULL, "CLK_SYS" },
945 { "HPR_DCS", NULL, "CLK_SYS" },
946 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
947 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
948
949 { "Left Input Mux", "IN1L", "IN1L" },
950 { "Left Input Mux", "IN2L", "IN2L" },
951 { "Left Input Mux", "IN3L", "IN3L" },
952
953 { "Left Input Inverting Mux", "IN1L", "IN1L" },
954 { "Left Input Inverting Mux", "IN2L", "IN2L" },
955 { "Left Input Inverting Mux", "IN3L", "IN3L" },
956
957 { "Right Input Mux", "IN1R", "IN1R" },
958 { "Right Input Mux", "IN2R", "IN2R" },
959 { "Right Input Mux", "IN3R", "IN3R" },
960
961 { "Right Input Inverting Mux", "IN1R", "IN1R" },
962 { "Right Input Inverting Mux", "IN2R", "IN2R" },
963 { "Right Input Inverting Mux", "IN3R", "IN3R" },
964
965 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
966 { "Left Input Mode Mux", "Differential Line",
967 "Left Input Mux" },
968 { "Left Input Mode Mux", "Differential Line",
969 "Left Input Inverting Mux" },
970 { "Left Input Mode Mux", "Differential Mic",
971 "Left Input Mux" },
972 { "Left Input Mode Mux", "Differential Mic",
973 "Left Input Inverting Mux" },
974
975 { "Right Input Mode Mux", "Single-Ended",
976 "Right Input Inverting Mux" },
977 { "Right Input Mode Mux", "Differential Line",
978 "Right Input Mux" },
979 { "Right Input Mode Mux", "Differential Line",
980 "Right Input Inverting Mux" },
981 { "Right Input Mode Mux", "Differential Mic",
982 "Right Input Mux" },
983 { "Right Input Mode Mux", "Differential Mic",
984 "Right Input Inverting Mux" },
985
986 { "Left Input PGA", NULL, "Left Input Mode Mux" },
987 { "Right Input PGA", NULL, "Right Input Mode Mux" },
988
989 { "Left ADC Input", "ADC", "Left Input PGA" },
990 { "Left ADC Input", "DMIC", "DMICDAT" },
991 { "Right ADC Input", "ADC", "Right Input PGA" },
992 { "Right ADC Input", "DMIC", "DMICDAT" },
993
994 { "Left Capture Mux", "Left", "ADCL" },
995 { "Left Capture Mux", "Right", "ADCR" },
996
997 { "Right Capture Mux", "Left", "ADCL" },
998 { "Right Capture Mux", "Right", "ADCR" },
999
1000 { "AIFTXL", NULL, "Left Capture Mux" },
1001 { "AIFTXR", NULL, "Right Capture Mux" },
1002
1003 { "ADCL", NULL, "Left ADC Input" },
1004 { "ADCL", NULL, "CLK_DSP" },
1005 { "ADCR", NULL, "Right ADC Input" },
1006 { "ADCR", NULL, "CLK_DSP" },
1007
1008 { "Left Playback Mux", "Left", "AIFRXL" },
1009 { "Left Playback Mux", "Right", "AIFRXR" },
1010
1011 { "Right Playback Mux", "Left", "AIFRXL" },
1012 { "Right Playback Mux", "Right", "AIFRXR" },
1013
1014 { "DACL Sidetone", "Left", "ADCL" },
1015 { "DACL Sidetone", "Right", "ADCR" },
1016 { "DACR Sidetone", "Left", "ADCL" },
1017 { "DACR Sidetone", "Right", "ADCR" },
1018
1019 { "DACL", NULL, "Left Playback Mux" },
1020 { "DACL", NULL, "DACL Sidetone" },
1021 { "DACL", NULL, "CLK_DSP" },
1022
1023 { "DACR", NULL, "Right Playback Mux" },
1024 { "DACR", NULL, "DACR Sidetone" },
1025 { "DACR", NULL, "CLK_DSP" },
1026
1027 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1028 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1029 { "Left Output Mixer", "DACL Switch", "DACL" },
1030 { "Left Output Mixer", "DACR Switch", "DACR" },
1031
1032 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1033 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1034 { "Right Output Mixer", "DACL Switch", "DACL" },
1035 { "Right Output Mixer", "DACR Switch", "DACR" },
1036
1037 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1038 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1039 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1040 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1041
1042 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1043 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1044 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1045 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1046
1047 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1048 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1049
1050 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1051 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1052
1053 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1054 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1055
1056 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1057 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1058 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1059 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1060 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1061 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1062 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1063 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
1064
1065 { "HPL_DCS", NULL, "DCS Master" },
1066 { "HPR_DCS", NULL, "DCS Master" },
1067 { "LINEOUTL_DCS", NULL, "DCS Master" },
1068 { "LINEOUTR_DCS", NULL, "DCS Master" },
1069
1070 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1071 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1072 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1073 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1074
1075 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1076 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1077 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1078 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1079
1080 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1081 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1082 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1083 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1084
1085 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1086 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1087 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1088 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
1089
1090 { "LOP", NULL, "Left Speaker PGA" },
1091 { "LON", NULL, "Left Speaker PGA" },
1092
1093 { "ROP", NULL, "Right Speaker PGA" },
1094 { "RON", NULL, "Right Speaker PGA" },
1095
1096 { "Charge Pump", NULL, "CLK_DSP" },
1097
1098 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1099 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1100 { "Left Line Output PGA", NULL, "Charge Pump" },
1101 { "Right Line Output PGA", NULL, "Charge Pump" },
1102 };
1103
1104 static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1105 enum snd_soc_bias_level level)
1106 {
1107 switch (level) {
1108 case SND_SOC_BIAS_ON:
1109 break;
1110
1111 case SND_SOC_BIAS_PREPARE:
1112 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1113 WM8903_VMID_RES_MASK,
1114 WM8903_VMID_RES_50K);
1115 break;
1116
1117 case SND_SOC_BIAS_STANDBY:
1118 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1119 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1120 WM8903_POBCTRL | WM8903_ISEL_MASK |
1121 WM8903_STARTUP_BIAS_ENA |
1122 WM8903_BIAS_ENA,
1123 WM8903_POBCTRL |
1124 (2 << WM8903_ISEL_SHIFT) |
1125 WM8903_STARTUP_BIAS_ENA);
1126
1127 snd_soc_update_bits(codec,
1128 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1129 WM8903_SPK_DISCHARGE,
1130 WM8903_SPK_DISCHARGE);
1131
1132 msleep(33);
1133
1134 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1135 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1136 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1137
1138 snd_soc_update_bits(codec,
1139 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1140 WM8903_SPK_DISCHARGE, 0);
1141
1142 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1143 WM8903_VMID_TIE_ENA |
1144 WM8903_BUFIO_ENA |
1145 WM8903_VMID_IO_ENA |
1146 WM8903_VMID_SOFT_MASK |
1147 WM8903_VMID_RES_MASK |
1148 WM8903_VMID_BUF_ENA,
1149 WM8903_VMID_TIE_ENA |
1150 WM8903_BUFIO_ENA |
1151 WM8903_VMID_IO_ENA |
1152 (2 << WM8903_VMID_SOFT_SHIFT) |
1153 WM8903_VMID_RES_250K |
1154 WM8903_VMID_BUF_ENA);
1155
1156 msleep(129);
1157
1158 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1159 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1160 0);
1161
1162 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1163 WM8903_VMID_SOFT_MASK, 0);
1164
1165 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1166 WM8903_VMID_RES_MASK,
1167 WM8903_VMID_RES_50K);
1168
1169 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1170 WM8903_BIAS_ENA | WM8903_POBCTRL,
1171 WM8903_BIAS_ENA);
1172
1173 /* By default no bypass paths are enabled so
1174 * enable Class W support.
1175 */
1176 dev_dbg(codec->dev, "Enabling Class W\n");
1177 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1178 WM8903_CP_DYN_FREQ |
1179 WM8903_CP_DYN_V,
1180 WM8903_CP_DYN_FREQ |
1181 WM8903_CP_DYN_V);
1182 }
1183
1184 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1185 WM8903_VMID_RES_MASK,
1186 WM8903_VMID_RES_250K);
1187 break;
1188
1189 case SND_SOC_BIAS_OFF:
1190 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1191 WM8903_BIAS_ENA, 0);
1192
1193 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1194 WM8903_VMID_SOFT_MASK,
1195 2 << WM8903_VMID_SOFT_SHIFT);
1196
1197 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1198 WM8903_VMID_BUF_ENA, 0);
1199
1200 msleep(290);
1201
1202 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1203 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1204 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1205 WM8903_VMID_SOFT_MASK |
1206 WM8903_VMID_BUF_ENA, 0);
1207
1208 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1209 WM8903_STARTUP_BIAS_ENA, 0);
1210 break;
1211 }
1212
1213 return 0;
1214 }
1215
1216 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1217 int clk_id, unsigned int freq, int dir)
1218 {
1219 struct snd_soc_codec *codec = codec_dai->codec;
1220 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1221
1222 wm8903->sysclk = freq;
1223
1224 return 0;
1225 }
1226
1227 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1228 unsigned int fmt)
1229 {
1230 struct snd_soc_codec *codec = codec_dai->codec;
1231 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1232
1233 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1234 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1235
1236 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1237 case SND_SOC_DAIFMT_CBS_CFS:
1238 break;
1239 case SND_SOC_DAIFMT_CBS_CFM:
1240 aif1 |= WM8903_LRCLK_DIR;
1241 break;
1242 case SND_SOC_DAIFMT_CBM_CFM:
1243 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1244 break;
1245 case SND_SOC_DAIFMT_CBM_CFS:
1246 aif1 |= WM8903_BCLK_DIR;
1247 break;
1248 default:
1249 return -EINVAL;
1250 }
1251
1252 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1253 case SND_SOC_DAIFMT_DSP_A:
1254 aif1 |= 0x3;
1255 break;
1256 case SND_SOC_DAIFMT_DSP_B:
1257 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1258 break;
1259 case SND_SOC_DAIFMT_I2S:
1260 aif1 |= 0x2;
1261 break;
1262 case SND_SOC_DAIFMT_RIGHT_J:
1263 aif1 |= 0x1;
1264 break;
1265 case SND_SOC_DAIFMT_LEFT_J:
1266 break;
1267 default:
1268 return -EINVAL;
1269 }
1270
1271 /* Clock inversion */
1272 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1273 case SND_SOC_DAIFMT_DSP_A:
1274 case SND_SOC_DAIFMT_DSP_B:
1275 /* frame inversion not valid for DSP modes */
1276 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1277 case SND_SOC_DAIFMT_NB_NF:
1278 break;
1279 case SND_SOC_DAIFMT_IB_NF:
1280 aif1 |= WM8903_AIF_BCLK_INV;
1281 break;
1282 default:
1283 return -EINVAL;
1284 }
1285 break;
1286 case SND_SOC_DAIFMT_I2S:
1287 case SND_SOC_DAIFMT_RIGHT_J:
1288 case SND_SOC_DAIFMT_LEFT_J:
1289 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1290 case SND_SOC_DAIFMT_NB_NF:
1291 break;
1292 case SND_SOC_DAIFMT_IB_IF:
1293 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1294 break;
1295 case SND_SOC_DAIFMT_IB_NF:
1296 aif1 |= WM8903_AIF_BCLK_INV;
1297 break;
1298 case SND_SOC_DAIFMT_NB_IF:
1299 aif1 |= WM8903_AIF_LRCLK_INV;
1300 break;
1301 default:
1302 return -EINVAL;
1303 }
1304 break;
1305 default:
1306 return -EINVAL;
1307 }
1308
1309 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1310
1311 return 0;
1312 }
1313
1314 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1315 {
1316 struct snd_soc_codec *codec = codec_dai->codec;
1317 u16 reg;
1318
1319 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1320
1321 if (mute)
1322 reg |= WM8903_DAC_MUTE;
1323 else
1324 reg &= ~WM8903_DAC_MUTE;
1325
1326 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
1327
1328 return 0;
1329 }
1330
1331 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1332 * for optimal performance so we list the lower rates first and match
1333 * on the last match we find. */
1334 static struct {
1335 int div;
1336 int rate;
1337 int mode;
1338 int mclk_div;
1339 } clk_sys_ratios[] = {
1340 { 64, 0x0, 0x0, 1 },
1341 { 68, 0x0, 0x1, 1 },
1342 { 125, 0x0, 0x2, 1 },
1343 { 128, 0x1, 0x0, 1 },
1344 { 136, 0x1, 0x1, 1 },
1345 { 192, 0x2, 0x0, 1 },
1346 { 204, 0x2, 0x1, 1 },
1347
1348 { 64, 0x0, 0x0, 2 },
1349 { 68, 0x0, 0x1, 2 },
1350 { 125, 0x0, 0x2, 2 },
1351 { 128, 0x1, 0x0, 2 },
1352 { 136, 0x1, 0x1, 2 },
1353 { 192, 0x2, 0x0, 2 },
1354 { 204, 0x2, 0x1, 2 },
1355
1356 { 250, 0x2, 0x2, 1 },
1357 { 256, 0x3, 0x0, 1 },
1358 { 272, 0x3, 0x1, 1 },
1359 { 384, 0x4, 0x0, 1 },
1360 { 408, 0x4, 0x1, 1 },
1361 { 375, 0x4, 0x2, 1 },
1362 { 512, 0x5, 0x0, 1 },
1363 { 544, 0x5, 0x1, 1 },
1364 { 500, 0x5, 0x2, 1 },
1365 { 768, 0x6, 0x0, 1 },
1366 { 816, 0x6, 0x1, 1 },
1367 { 750, 0x6, 0x2, 1 },
1368 { 1024, 0x7, 0x0, 1 },
1369 { 1088, 0x7, 0x1, 1 },
1370 { 1000, 0x7, 0x2, 1 },
1371 { 1408, 0x8, 0x0, 1 },
1372 { 1496, 0x8, 0x1, 1 },
1373 { 1536, 0x9, 0x0, 1 },
1374 { 1632, 0x9, 0x1, 1 },
1375 { 1500, 0x9, 0x2, 1 },
1376
1377 { 250, 0x2, 0x2, 2 },
1378 { 256, 0x3, 0x0, 2 },
1379 { 272, 0x3, 0x1, 2 },
1380 { 384, 0x4, 0x0, 2 },
1381 { 408, 0x4, 0x1, 2 },
1382 { 375, 0x4, 0x2, 2 },
1383 { 512, 0x5, 0x0, 2 },
1384 { 544, 0x5, 0x1, 2 },
1385 { 500, 0x5, 0x2, 2 },
1386 { 768, 0x6, 0x0, 2 },
1387 { 816, 0x6, 0x1, 2 },
1388 { 750, 0x6, 0x2, 2 },
1389 { 1024, 0x7, 0x0, 2 },
1390 { 1088, 0x7, 0x1, 2 },
1391 { 1000, 0x7, 0x2, 2 },
1392 { 1408, 0x8, 0x0, 2 },
1393 { 1496, 0x8, 0x1, 2 },
1394 { 1536, 0x9, 0x0, 2 },
1395 { 1632, 0x9, 0x1, 2 },
1396 { 1500, 0x9, 0x2, 2 },
1397 };
1398
1399 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1400 static struct {
1401 int ratio;
1402 int div;
1403 } bclk_divs[] = {
1404 { 10, 0 },
1405 { 20, 2 },
1406 { 30, 3 },
1407 { 40, 4 },
1408 { 50, 5 },
1409 { 60, 7 },
1410 { 80, 8 },
1411 { 100, 9 },
1412 { 120, 11 },
1413 { 160, 12 },
1414 { 200, 13 },
1415 { 220, 14 },
1416 { 240, 15 },
1417 { 300, 17 },
1418 { 320, 18 },
1419 { 440, 19 },
1420 { 480, 20 },
1421 };
1422
1423 /* Sample rates for DSP */
1424 static struct {
1425 int rate;
1426 int value;
1427 } sample_rates[] = {
1428 { 8000, 0 },
1429 { 11025, 1 },
1430 { 12000, 2 },
1431 { 16000, 3 },
1432 { 22050, 4 },
1433 { 24000, 5 },
1434 { 32000, 6 },
1435 { 44100, 7 },
1436 { 48000, 8 },
1437 { 88200, 9 },
1438 { 96000, 10 },
1439 { 0, 0 },
1440 };
1441
1442 static int wm8903_hw_params(struct snd_pcm_substream *substream,
1443 struct snd_pcm_hw_params *params,
1444 struct snd_soc_dai *dai)
1445 {
1446 struct snd_soc_codec *codec = dai->codec;
1447 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1448 int fs = params_rate(params);
1449 int bclk;
1450 int bclk_div;
1451 int i;
1452 int dsp_config;
1453 int clk_config;
1454 int best_val;
1455 int cur_val;
1456 int clk_sys;
1457
1458 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1459 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1460 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1461 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1462 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1463 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1464
1465 /* Enable sloping stopband filter for low sample rates */
1466 if (fs <= 24000)
1467 dac_digital1 |= WM8903_DAC_SB_FILT;
1468 else
1469 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1470
1471 /* Configure sample rate logic for DSP - choose nearest rate */
1472 dsp_config = 0;
1473 best_val = abs(sample_rates[dsp_config].rate - fs);
1474 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1475 cur_val = abs(sample_rates[i].rate - fs);
1476 if (cur_val <= best_val) {
1477 dsp_config = i;
1478 best_val = cur_val;
1479 }
1480 }
1481
1482 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1483 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1484 clock1 |= sample_rates[dsp_config].value;
1485
1486 aif1 &= ~WM8903_AIF_WL_MASK;
1487 bclk = 2 * fs;
1488 switch (params_width(params)) {
1489 case 16:
1490 bclk *= 16;
1491 break;
1492 case 20:
1493 bclk *= 20;
1494 aif1 |= 0x4;
1495 break;
1496 case 24:
1497 bclk *= 24;
1498 aif1 |= 0x8;
1499 break;
1500 case 32:
1501 bclk *= 32;
1502 aif1 |= 0xc;
1503 break;
1504 default:
1505 return -EINVAL;
1506 }
1507
1508 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1509 wm8903->sysclk, fs);
1510
1511 /* We may not have an MCLK which allows us to generate exactly
1512 * the clock we want, particularly with USB derived inputs, so
1513 * approximate.
1514 */
1515 clk_config = 0;
1516 best_val = abs((wm8903->sysclk /
1517 (clk_sys_ratios[0].mclk_div *
1518 clk_sys_ratios[0].div)) - fs);
1519 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1520 cur_val = abs((wm8903->sysclk /
1521 (clk_sys_ratios[i].mclk_div *
1522 clk_sys_ratios[i].div)) - fs);
1523
1524 if (cur_val <= best_val) {
1525 clk_config = i;
1526 best_val = cur_val;
1527 }
1528 }
1529
1530 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1531 clock0 |= WM8903_MCLKDIV2;
1532 clk_sys = wm8903->sysclk / 2;
1533 } else {
1534 clock0 &= ~WM8903_MCLKDIV2;
1535 clk_sys = wm8903->sysclk;
1536 }
1537
1538 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1539 WM8903_CLK_SYS_MODE_MASK);
1540 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1541 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1542
1543 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1544 clk_sys_ratios[clk_config].rate,
1545 clk_sys_ratios[clk_config].mode,
1546 clk_sys_ratios[clk_config].div);
1547
1548 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1549
1550 /* We may not get quite the right frequency if using
1551 * approximate clocks so look for the closest match that is
1552 * higher than the target (we need to ensure that there enough
1553 * BCLKs to clock out the samples).
1554 */
1555 bclk_div = 0;
1556 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1557 i = 1;
1558 while (i < ARRAY_SIZE(bclk_divs)) {
1559 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1560 if (cur_val < 0) /* BCLK table is sorted */
1561 break;
1562 bclk_div = i;
1563 best_val = cur_val;
1564 i++;
1565 }
1566
1567 aif2 &= ~WM8903_BCLK_DIV_MASK;
1568 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1569
1570 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1571 bclk_divs[bclk_div].ratio / 10, bclk,
1572 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1573
1574 aif2 |= bclk_divs[bclk_div].div;
1575 aif3 |= bclk / fs;
1576
1577 wm8903->fs = params_rate(params);
1578 wm8903_set_deemph(codec);
1579
1580 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1581 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1582 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1583 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1584 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1585 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
1586
1587 return 0;
1588 }
1589
1590 /**
1591 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1592 *
1593 * @codec: WM8903 codec
1594 * @jack: jack to report detection events on
1595 * @det: value to report for presence detection
1596 * @shrt: value to report for short detection
1597 *
1598 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1599 * being used to bring out signals to the processor then only platform
1600 * data configuration is needed for WM8903 and processor GPIOs should
1601 * be configured using snd_soc_jack_add_gpios() instead.
1602 *
1603 * The current threasholds for detection should be configured using
1604 * micdet_cfg in the platform data. Using this function will force on
1605 * the microphone bias for the device.
1606 */
1607 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1608 int det, int shrt)
1609 {
1610 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1611 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
1612
1613 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1614 det, shrt);
1615
1616 /* Store the configuration */
1617 wm8903->mic_jack = jack;
1618 wm8903->mic_det = det;
1619 wm8903->mic_short = shrt;
1620
1621 /* Enable interrupts we've got a report configured for */
1622 if (det)
1623 irq_mask &= ~WM8903_MICDET_EINT;
1624 if (shrt)
1625 irq_mask &= ~WM8903_MICSHRT_EINT;
1626
1627 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1628 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1629 irq_mask);
1630
1631 if (det || shrt) {
1632 /* Enable mic detection, this may not have been set through
1633 * platform data (eg, if the defaults are OK). */
1634 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1635 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1636 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1637 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1638 } else {
1639 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1640 WM8903_MICDET_ENA, 0);
1641 }
1642
1643 return 0;
1644 }
1645 EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1646
1647 static irqreturn_t wm8903_irq(int irq, void *data)
1648 {
1649 struct wm8903_priv *wm8903 = data;
1650 int mic_report, ret;
1651 unsigned int int_val, mask, int_pol;
1652
1653 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK,
1654 &mask);
1655 if (ret != 0) {
1656 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret);
1657 return IRQ_NONE;
1658 }
1659
1660 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val);
1661 if (ret != 0) {
1662 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret);
1663 return IRQ_NONE;
1664 }
1665
1666 int_val &= ~mask;
1667
1668 if (int_val & WM8903_WSEQ_BUSY_EINT) {
1669 dev_warn(wm8903->dev, "Write sequencer done\n");
1670 }
1671
1672 /*
1673 * The rest is microphone jack detection. We need to manually
1674 * invert the polarity of the interrupt after each event - to
1675 * simplify the code keep track of the last state we reported
1676 * and just invert the relevant bits in both the report and
1677 * the polarity register.
1678 */
1679 mic_report = wm8903->mic_last_report;
1680 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1681 &int_pol);
1682 if (ret != 0) {
1683 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n",
1684 ret);
1685 return IRQ_HANDLED;
1686 }
1687
1688 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1689 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1690 trace_snd_soc_jack_irq(dev_name(wm8903->dev));
1691 #endif
1692
1693 if (int_val & WM8903_MICSHRT_EINT) {
1694 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol);
1695
1696 mic_report ^= wm8903->mic_short;
1697 int_pol ^= WM8903_MICSHRT_INV;
1698 }
1699
1700 if (int_val & WM8903_MICDET_EINT) {
1701 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol);
1702
1703 mic_report ^= wm8903->mic_det;
1704 int_pol ^= WM8903_MICDET_INV;
1705
1706 msleep(wm8903->mic_delay);
1707 }
1708
1709 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1710 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1711
1712 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1713 wm8903->mic_short | wm8903->mic_det);
1714
1715 wm8903->mic_last_report = mic_report;
1716
1717 return IRQ_HANDLED;
1718 }
1719
1720 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1721 SNDRV_PCM_RATE_11025 | \
1722 SNDRV_PCM_RATE_16000 | \
1723 SNDRV_PCM_RATE_22050 | \
1724 SNDRV_PCM_RATE_32000 | \
1725 SNDRV_PCM_RATE_44100 | \
1726 SNDRV_PCM_RATE_48000 | \
1727 SNDRV_PCM_RATE_88200 | \
1728 SNDRV_PCM_RATE_96000)
1729
1730 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1731 SNDRV_PCM_RATE_11025 | \
1732 SNDRV_PCM_RATE_16000 | \
1733 SNDRV_PCM_RATE_22050 | \
1734 SNDRV_PCM_RATE_32000 | \
1735 SNDRV_PCM_RATE_44100 | \
1736 SNDRV_PCM_RATE_48000)
1737
1738 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1739 SNDRV_PCM_FMTBIT_S20_3LE |\
1740 SNDRV_PCM_FMTBIT_S24_LE)
1741
1742 static const struct snd_soc_dai_ops wm8903_dai_ops = {
1743 .hw_params = wm8903_hw_params,
1744 .digital_mute = wm8903_digital_mute,
1745 .set_fmt = wm8903_set_dai_fmt,
1746 .set_sysclk = wm8903_set_dai_sysclk,
1747 };
1748
1749 static struct snd_soc_dai_driver wm8903_dai = {
1750 .name = "wm8903-hifi",
1751 .playback = {
1752 .stream_name = "Playback",
1753 .channels_min = 2,
1754 .channels_max = 2,
1755 .rates = WM8903_PLAYBACK_RATES,
1756 .formats = WM8903_FORMATS,
1757 },
1758 .capture = {
1759 .stream_name = "Capture",
1760 .channels_min = 2,
1761 .channels_max = 2,
1762 .rates = WM8903_CAPTURE_RATES,
1763 .formats = WM8903_FORMATS,
1764 },
1765 .ops = &wm8903_dai_ops,
1766 .symmetric_rates = 1,
1767 };
1768
1769 static int wm8903_resume(struct snd_soc_codec *codec)
1770 {
1771 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1772
1773 regcache_sync(wm8903->regmap);
1774
1775 return 0;
1776 }
1777
1778 #ifdef CONFIG_GPIOLIB
1779 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1780 {
1781 if (offset >= WM8903_NUM_GPIO)
1782 return -EINVAL;
1783
1784 return 0;
1785 }
1786
1787 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1788 {
1789 struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
1790 unsigned int mask, val;
1791 int ret;
1792
1793 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1794 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1795 WM8903_GP1_DIR;
1796
1797 ret = regmap_update_bits(wm8903->regmap,
1798 WM8903_GPIO_CONTROL_1 + offset, mask, val);
1799 if (ret < 0)
1800 return ret;
1801
1802 return 0;
1803 }
1804
1805 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1806 {
1807 struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
1808 unsigned int reg;
1809
1810 regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, &reg);
1811
1812 return !!((reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT);
1813 }
1814
1815 static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1816 unsigned offset, int value)
1817 {
1818 struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
1819 unsigned int mask, val;
1820 int ret;
1821
1822 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1823 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1824 (value << WM8903_GP2_LVL_SHIFT);
1825
1826 ret = regmap_update_bits(wm8903->regmap,
1827 WM8903_GPIO_CONTROL_1 + offset, mask, val);
1828 if (ret < 0)
1829 return ret;
1830
1831 return 0;
1832 }
1833
1834 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1835 {
1836 struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
1837
1838 regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset,
1839 WM8903_GP1_LVL_MASK,
1840 !!value << WM8903_GP1_LVL_SHIFT);
1841 }
1842
1843 static const struct gpio_chip wm8903_template_chip = {
1844 .label = "wm8903",
1845 .owner = THIS_MODULE,
1846 .request = wm8903_gpio_request,
1847 .direction_input = wm8903_gpio_direction_in,
1848 .get = wm8903_gpio_get,
1849 .direction_output = wm8903_gpio_direction_out,
1850 .set = wm8903_gpio_set,
1851 .can_sleep = 1,
1852 };
1853
1854 static void wm8903_init_gpio(struct wm8903_priv *wm8903)
1855 {
1856 struct wm8903_platform_data *pdata = wm8903->pdata;
1857 int ret;
1858
1859 wm8903->gpio_chip = wm8903_template_chip;
1860 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1861 wm8903->gpio_chip.parent = wm8903->dev;
1862
1863 if (pdata->gpio_base)
1864 wm8903->gpio_chip.base = pdata->gpio_base;
1865 else
1866 wm8903->gpio_chip.base = -1;
1867
1868 ret = gpiochip_add_data(&wm8903->gpio_chip, wm8903);
1869 if (ret != 0)
1870 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret);
1871 }
1872
1873 static void wm8903_free_gpio(struct wm8903_priv *wm8903)
1874 {
1875 gpiochip_remove(&wm8903->gpio_chip);
1876 }
1877 #else
1878 static void wm8903_init_gpio(struct wm8903_priv *wm8903)
1879 {
1880 }
1881
1882 static void wm8903_free_gpio(struct wm8903_priv *wm8903)
1883 {
1884 }
1885 #endif
1886
1887 static const struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1888 .resume = wm8903_resume,
1889 .set_bias_level = wm8903_set_bias_level,
1890 .seq_notifier = wm8903_seq_notifier,
1891 .suspend_bias_off = true,
1892
1893 .component_driver = {
1894 .controls = wm8903_snd_controls,
1895 .num_controls = ARRAY_SIZE(wm8903_snd_controls),
1896 .dapm_widgets = wm8903_dapm_widgets,
1897 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
1898 .dapm_routes = wm8903_intercon,
1899 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
1900 },
1901 };
1902
1903 static const struct regmap_config wm8903_regmap = {
1904 .reg_bits = 8,
1905 .val_bits = 16,
1906
1907 .max_register = WM8903_MAX_REGISTER,
1908 .volatile_reg = wm8903_volatile_register,
1909 .readable_reg = wm8903_readable_register,
1910
1911 .cache_type = REGCACHE_RBTREE,
1912 .reg_defaults = wm8903_reg_defaults,
1913 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
1914 };
1915
1916 static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,
1917 struct wm8903_platform_data *pdata)
1918 {
1919 struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
1920 if (!irq_data) {
1921 dev_err(&i2c->dev, "Invalid IRQ: %d\n",
1922 i2c->irq);
1923 return -EINVAL;
1924 }
1925
1926 switch (irqd_get_trigger_type(irq_data)) {
1927 case IRQ_TYPE_NONE:
1928 default:
1929 /*
1930 * We assume the controller imposes no restrictions,
1931 * so we are able to select active-high
1932 */
1933 /* Fall-through */
1934 case IRQ_TYPE_LEVEL_HIGH:
1935 pdata->irq_active_low = false;
1936 break;
1937 case IRQ_TYPE_LEVEL_LOW:
1938 pdata->irq_active_low = true;
1939 break;
1940 }
1941
1942 return 0;
1943 }
1944
1945 static int wm8903_set_pdata_from_of(struct i2c_client *i2c,
1946 struct wm8903_platform_data *pdata)
1947 {
1948 const struct device_node *np = i2c->dev.of_node;
1949 u32 val32;
1950 int i;
1951
1952 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)
1953 pdata->micdet_cfg = val32;
1954
1955 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)
1956 pdata->micdet_delay = val32;
1957
1958 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,
1959 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {
1960 /*
1961 * In device tree: 0 means "write 0",
1962 * 0xffffffff means "don't touch".
1963 *
1964 * In platform data: 0 means "don't touch",
1965 * 0x8000 means "write 0".
1966 *
1967 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
1968 *
1969 * Convert from DT to pdata representation here,
1970 * so no other code needs to change.
1971 */
1972 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1973 if (pdata->gpio_cfg[i] == 0) {
1974 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;
1975 } else if (pdata->gpio_cfg[i] == 0xffffffff) {
1976 pdata->gpio_cfg[i] = 0;
1977 } else if (pdata->gpio_cfg[i] > 0x7fff) {
1978 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",
1979 i, pdata->gpio_cfg[i]);
1980 return -EINVAL;
1981 }
1982 }
1983 }
1984
1985 return 0;
1986 }
1987
1988 static int wm8903_i2c_probe(struct i2c_client *i2c,
1989 const struct i2c_device_id *id)
1990 {
1991 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
1992 struct wm8903_priv *wm8903;
1993 int trigger;
1994 bool mic_gpio = false;
1995 unsigned int val, irq_pol;
1996 int ret, i;
1997
1998 wm8903 = devm_kzalloc(&i2c->dev, sizeof(*wm8903), GFP_KERNEL);
1999 if (wm8903 == NULL)
2000 return -ENOMEM;
2001
2002 mutex_init(&wm8903->lock);
2003 wm8903->dev = &i2c->dev;
2004
2005 wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);
2006 if (IS_ERR(wm8903->regmap)) {
2007 ret = PTR_ERR(wm8903->regmap);
2008 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2009 ret);
2010 return ret;
2011 }
2012
2013 i2c_set_clientdata(i2c, wm8903);
2014
2015 /* If no platform data was supplied, create storage for defaults */
2016 if (pdata) {
2017 wm8903->pdata = pdata;
2018 } else {
2019 wm8903->pdata = devm_kzalloc(&i2c->dev, sizeof(*wm8903->pdata),
2020 GFP_KERNEL);
2021 if (!wm8903->pdata)
2022 return -ENOMEM;
2023
2024 if (i2c->irq) {
2025 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);
2026 if (ret != 0)
2027 return ret;
2028 }
2029
2030 if (i2c->dev.of_node) {
2031 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);
2032 if (ret != 0)
2033 return ret;
2034 }
2035 }
2036
2037 pdata = wm8903->pdata;
2038
2039 for (i = 0; i < ARRAY_SIZE(wm8903->supplies); i++)
2040 wm8903->supplies[i].supply = wm8903_supply_names[i];
2041
2042 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8903->supplies),
2043 wm8903->supplies);
2044 if (ret != 0) {
2045 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2046 return ret;
2047 }
2048
2049 ret = regulator_bulk_enable(ARRAY_SIZE(wm8903->supplies),
2050 wm8903->supplies);
2051 if (ret != 0) {
2052 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2053 return ret;
2054 }
2055
2056 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
2057 if (ret != 0) {
2058 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
2059 goto err;
2060 }
2061 if (val != 0x8903) {
2062 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
2063 ret = -ENODEV;
2064 goto err;
2065 }
2066
2067 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
2068 if (ret != 0) {
2069 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
2070 goto err;
2071 }
2072 dev_info(&i2c->dev, "WM8903 revision %c\n",
2073 (val & WM8903_CHIP_REV_MASK) + 'A');
2074
2075 /* Reset the device */
2076 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
2077
2078 wm8903_init_gpio(wm8903);
2079
2080 /* Set up GPIO pin state, detect if any are MIC detect outputs */
2081 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
2082 if ((!pdata->gpio_cfg[i]) ||
2083 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
2084 continue;
2085
2086 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i,
2087 pdata->gpio_cfg[i] & 0x7fff);
2088
2089 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
2090 >> WM8903_GP1_FN_SHIFT;
2091
2092 switch (val) {
2093 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
2094 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
2095 mic_gpio = true;
2096 break;
2097 default:
2098 break;
2099 }
2100 }
2101
2102 /* Set up microphone detection */
2103 regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0,
2104 pdata->micdet_cfg);
2105
2106 /* Microphone detection needs the WSEQ clock */
2107 if (pdata->micdet_cfg)
2108 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0,
2109 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
2110
2111 /* If microphone detection is enabled by pdata but
2112 * detected via IRQ then interrupts can be lost before
2113 * the machine driver has set up microphone detection
2114 * IRQs as the IRQs are clear on read. The detection
2115 * will be enabled when the machine driver configures.
2116 */
2117 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
2118
2119 wm8903->mic_delay = pdata->micdet_delay;
2120
2121 if (i2c->irq) {
2122 if (pdata->irq_active_low) {
2123 trigger = IRQF_TRIGGER_LOW;
2124 irq_pol = WM8903_IRQ_POL;
2125 } else {
2126 trigger = IRQF_TRIGGER_HIGH;
2127 irq_pol = 0;
2128 }
2129
2130 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL,
2131 WM8903_IRQ_POL, irq_pol);
2132
2133 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
2134 trigger | IRQF_ONESHOT,
2135 "wm8903", wm8903);
2136 if (ret != 0) {
2137 dev_err(wm8903->dev, "Failed to request IRQ: %d\n",
2138 ret);
2139 return ret;
2140 }
2141
2142 /* Enable write sequencer interrupts */
2143 regmap_update_bits(wm8903->regmap,
2144 WM8903_INTERRUPT_STATUS_1_MASK,
2145 WM8903_IM_WSEQ_BUSY_EINT, 0);
2146 }
2147
2148 /* Latch volume update bits */
2149 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT,
2150 WM8903_ADCVU, WM8903_ADCVU);
2151 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT,
2152 WM8903_ADCVU, WM8903_ADCVU);
2153
2154 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT,
2155 WM8903_DACVU, WM8903_DACVU);
2156 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT,
2157 WM8903_DACVU, WM8903_DACVU);
2158
2159 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT,
2160 WM8903_HPOUTVU, WM8903_HPOUTVU);
2161 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT,
2162 WM8903_HPOUTVU, WM8903_HPOUTVU);
2163
2164 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT,
2165 WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2166 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT,
2167 WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2168
2169 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT,
2170 WM8903_SPKVU, WM8903_SPKVU);
2171 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT,
2172 WM8903_SPKVU, WM8903_SPKVU);
2173
2174 /* Enable DAC soft mute by default */
2175 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1,
2176 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2177 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
2178
2179 ret = snd_soc_register_codec(&i2c->dev,
2180 &soc_codec_dev_wm8903, &wm8903_dai, 1);
2181 if (ret != 0)
2182 goto err;
2183
2184 return 0;
2185 err:
2186 regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),
2187 wm8903->supplies);
2188 return ret;
2189 }
2190
2191 static int wm8903_i2c_remove(struct i2c_client *client)
2192 {
2193 struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2194
2195 regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),
2196 wm8903->supplies);
2197 if (client->irq)
2198 free_irq(client->irq, wm8903);
2199 wm8903_free_gpio(wm8903);
2200 snd_soc_unregister_codec(&client->dev);
2201
2202 return 0;
2203 }
2204
2205 static const struct of_device_id wm8903_of_match[] = {
2206 { .compatible = "wlf,wm8903", },
2207 {},
2208 };
2209 MODULE_DEVICE_TABLE(of, wm8903_of_match);
2210
2211 static const struct i2c_device_id wm8903_i2c_id[] = {
2212 { "wm8903", 0 },
2213 { }
2214 };
2215 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2216
2217 static struct i2c_driver wm8903_i2c_driver = {
2218 .driver = {
2219 .name = "wm8903",
2220 .of_match_table = wm8903_of_match,
2221 },
2222 .probe = wm8903_i2c_probe,
2223 .remove = wm8903_i2c_remove,
2224 .id_table = wm8903_i2c_id,
2225 };
2226
2227 module_i2c_driver(wm8903_i2c_driver);
2228
2229 MODULE_DESCRIPTION("ASoC WM8903 driver");
2230 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2231 MODULE_LICENSE("GPL");
CRIS linux kernel tree