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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / sound / soc / davinci / davinci-i2s.c
blob3849616519048401a44e691db64945050b7a8d68
1 /*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * DT support (c) 2016 Petr Kulhavy, Barix AG <petr@barix.com>
8 * based on davinci-mcasp.c DT support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * TODO:
15 * on DA850 implement HW FIFOs instead of DMA into DXR and DRR registers
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/platform_data/davinci_asp.h>
26
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
32 #include <sound/dmaengine_pcm.h>
33
34 #include "edma-pcm.h"
35 #include "davinci-i2s.h"
36
37
38 /*
39 * NOTE: terminology here is confusing.
40 *
41 * - This driver supports the "Audio Serial Port" (ASP),
42 * found on dm6446, dm355, and other DaVinci chips.
43 *
44 * - But it labels it a "Multi-channel Buffered Serial Port"
45 * (McBSP) as on older chips like the dm642 ... which was
46 * backward-compatible, possibly explaining that confusion.
47 *
48 * - OMAP chips have a controller called McBSP, which is
49 * incompatible with the DaVinci flavor of McBSP.
50 *
51 * - Newer DaVinci chips have a controller called McASP,
52 * incompatible with ASP and with either McBSP.
53 *
54 * In short: this uses ASP to implement I2S, not McBSP.
55 * And it won't be the only DaVinci implemention of I2S.
56 */
57 #define DAVINCI_MCBSP_DRR_REG 0x00
58 #define DAVINCI_MCBSP_DXR_REG 0x04
59 #define DAVINCI_MCBSP_SPCR_REG 0x08
60 #define DAVINCI_MCBSP_RCR_REG 0x0c
61 #define DAVINCI_MCBSP_XCR_REG 0x10
62 #define DAVINCI_MCBSP_SRGR_REG 0x14
63 #define DAVINCI_MCBSP_PCR_REG 0x24
64
65 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
66 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
67 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
68 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
69 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
70 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
71 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
72
73 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
74 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
75 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
76 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
77 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
78 #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
79 #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
80
81 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
82 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
83 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
84 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
85 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
86 #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
87 #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
88
89 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
90 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
91 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
92 #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
93
94 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
95 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
96 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
97 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
98 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
99 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
100 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
101 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
102 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
103
104 enum {
105 DAVINCI_MCBSP_WORD_8 = 0,
106 DAVINCI_MCBSP_WORD_12,
107 DAVINCI_MCBSP_WORD_16,
108 DAVINCI_MCBSP_WORD_20,
109 DAVINCI_MCBSP_WORD_24,
110 DAVINCI_MCBSP_WORD_32,
111 };
112
113 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
114 [SNDRV_PCM_FORMAT_S8] = 1,
115 [SNDRV_PCM_FORMAT_S16_LE] = 2,
116 [SNDRV_PCM_FORMAT_S32_LE] = 4,
117 };
118
119 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
120 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
121 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
122 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
123 };
124
125 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
126 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
127 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
128 };
129
130 struct davinci_mcbsp_dev {
131 struct device *dev;
132 struct snd_dmaengine_dai_dma_data dma_data[2];
133 int dma_request[2];
134 void __iomem *base;
135 #define MOD_DSP_A 0
136 #define MOD_DSP_B 1
137 int mode;
138 u32 pcr;
139 struct clk *clk;
140 /*
141 * Combining both channels into 1 element will at least double the
142 * amount of time between servicing the dma channel, increase
143 * effiency, and reduce the chance of overrun/underrun. But,
144 * it will result in the left & right channels being swapped.
145 *
146 * If relabeling the left and right channels is not possible,
147 * you may want to let the codec know to swap them back.
148 *
149 * It may allow x10 the amount of time to service dma requests,
150 * if the codec is master and is using an unnecessarily fast bit clock
151 * (ie. tlvaic23b), independent of the sample rate. So, having an
152 * entire frame at once means it can be serviced at the sample rate
153 * instead of the bit clock rate.
154 *
155 * In the now unlikely case that an underrun still
156 * occurs, both the left and right samples will be repeated
157 * so that no pops are heard, and the left and right channels
158 * won't end up being swapped because of the underrun.
159 */
160 unsigned enable_channel_combine:1;
161
162 unsigned int fmt;
163 int clk_div;
164 int clk_input_pin;
165 bool i2s_accurate_sck;
166 };
167
168 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
169 int reg, u32 val)
170 {
171 __raw_writel(val, dev->base + reg);
172 }
173
174 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
175 {
176 return __raw_readl(dev->base + reg);
177 }
178
179 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
180 {
181 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
182 /* The clock needs to toggle to complete reset.
183 * So, fake it by toggling the clk polarity.
184 */
185 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
186 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
187 }
188
189 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
190 struct snd_pcm_substream *substream)
191 {
192 struct snd_soc_pcm_runtime *rtd = substream->private_data;
193 struct snd_soc_platform *platform = rtd->platform;
194 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
195 u32 spcr;
196 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
197 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
198 if (spcr & mask) {
199 /* start off disabled */
200 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
201 spcr & ~mask);
202 toggle_clock(dev, playback);
203 }
204 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
205 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
206 /* Start the sample generator */
207 spcr |= DAVINCI_MCBSP_SPCR_GRST;
208 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
209 }
210
211 if (playback) {
212 /* Stop the DMA to avoid data loss */
213 /* while the transmitter is out of reset to handle XSYNCERR */
214 if (platform->driver->ops->trigger) {
215 int ret = platform->driver->ops->trigger(substream,
216 SNDRV_PCM_TRIGGER_STOP);
217 if (ret < 0)
218 printk(KERN_DEBUG "Playback DMA stop failed\n");
219 }
220
221 /* Enable the transmitter */
222 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
223 spcr |= DAVINCI_MCBSP_SPCR_XRST;
224 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
225
226 /* wait for any unexpected frame sync error to occur */
227 udelay(100);
228
229 /* Disable the transmitter to clear any outstanding XSYNCERR */
230 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
231 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
232 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
233 toggle_clock(dev, playback);
234
235 /* Restart the DMA */
236 if (platform->driver->ops->trigger) {
237 int ret = platform->driver->ops->trigger(substream,
238 SNDRV_PCM_TRIGGER_START);
239 if (ret < 0)
240 printk(KERN_DEBUG "Playback DMA start failed\n");
241 }
242 }
243
244 /* Enable transmitter or receiver */
245 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
246 spcr |= mask;
247
248 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
249 /* Start frame sync */
250 spcr |= DAVINCI_MCBSP_SPCR_FRST;
251 }
252 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
253 }
254
255 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
256 {
257 u32 spcr;
258
259 /* Reset transmitter/receiver and sample rate/frame sync generators */
260 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
261 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
262 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
263 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
264 toggle_clock(dev, playback);
265 }
266
267 #define DEFAULT_BITPERSAMPLE 16
268
269 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
270 unsigned int fmt)
271 {
272 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
273 unsigned int pcr;
274 unsigned int srgr;
275 bool inv_fs = false;
276 /* Attention srgr is updated by hw_params! */
277 srgr = DAVINCI_MCBSP_SRGR_FSGM |
278 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
279 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
280
281 dev->fmt = fmt;
282 /* set master/slave audio interface */
283 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
284 case SND_SOC_DAIFMT_CBS_CFS:
285 /* cpu is master */
286 pcr = DAVINCI_MCBSP_PCR_FSXM |
287 DAVINCI_MCBSP_PCR_FSRM |
288 DAVINCI_MCBSP_PCR_CLKXM |
289 DAVINCI_MCBSP_PCR_CLKRM;
290 break;
291 case SND_SOC_DAIFMT_CBM_CFS:
292 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
293 /*
294 * Selection of the clock input pin that is the
295 * input for the Sample Rate Generator.
296 * McBSP FSR and FSX are driven by the Sample Rate
297 * Generator.
298 */
299 switch (dev->clk_input_pin) {
300 case MCBSP_CLKS:
301 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
302 DAVINCI_MCBSP_PCR_CLKRM;
303 break;
304 case MCBSP_CLKR:
305 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
306 break;
307 default:
308 dev_err(dev->dev, "bad clk_input_pin\n");
309 return -EINVAL;
310 }
311
312 break;
313 case SND_SOC_DAIFMT_CBM_CFM:
314 /* codec is master */
315 pcr = 0;
316 break;
317 default:
318 printk(KERN_ERR "%s:bad master\n", __func__);
319 return -EINVAL;
320 }
321
322 /* interface format */
323 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
324 case SND_SOC_DAIFMT_I2S:
325 /* Davinci doesn't support TRUE I2S, but some codecs will have
326 * the left and right channels contiguous. This allows
327 * dsp_a mode to be used with an inverted normal frame clk.
328 * If your codec is master and does not have contiguous
329 * channels, then you will have sound on only one channel.
330 * Try using a different mode, or codec as slave.
331 *
332 * The TLV320AIC33 is an example of a codec where this works.
333 * It has a variable bit clock frequency allowing it to have
334 * valid data on every bit clock.
335 *
336 * The TLV320AIC23 is an example of a codec where this does not
337 * work. It has a fixed bit clock frequency with progressively
338 * more empty bit clock slots between channels as the sample
339 * rate is lowered.
340 */
341 inv_fs = true;
342 case SND_SOC_DAIFMT_DSP_A:
343 dev->mode = MOD_DSP_A;
344 break;
345 case SND_SOC_DAIFMT_DSP_B:
346 dev->mode = MOD_DSP_B;
347 break;
348 default:
349 printk(KERN_ERR "%s:bad format\n", __func__);
350 return -EINVAL;
351 }
352
353 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
354 case SND_SOC_DAIFMT_NB_NF:
355 /* CLKRP Receive clock polarity,
356 * 1 - sampled on rising edge of CLKR
357 * valid on rising edge
358 * CLKXP Transmit clock polarity,
359 * 1 - clocked on falling edge of CLKX
360 * valid on rising edge
361 * FSRP Receive frame sync pol, 0 - active high
362 * FSXP Transmit frame sync pol, 0 - active high
363 */
364 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
365 break;
366 case SND_SOC_DAIFMT_IB_IF:
367 /* CLKRP Receive clock polarity,
368 * 0 - sampled on falling edge of CLKR
369 * valid on falling edge
370 * CLKXP Transmit clock polarity,
371 * 0 - clocked on rising edge of CLKX
372 * valid on falling edge
373 * FSRP Receive frame sync pol, 1 - active low
374 * FSXP Transmit frame sync pol, 1 - active low
375 */
376 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
377 break;
378 case SND_SOC_DAIFMT_NB_IF:
379 /* CLKRP Receive clock polarity,
380 * 1 - sampled on rising edge of CLKR
381 * valid on rising edge
382 * CLKXP Transmit clock polarity,
383 * 1 - clocked on falling edge of CLKX
384 * valid on rising edge
385 * FSRP Receive frame sync pol, 1 - active low
386 * FSXP Transmit frame sync pol, 1 - active low
387 */
388 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
389 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
390 break;
391 case SND_SOC_DAIFMT_IB_NF:
392 /* CLKRP Receive clock polarity,
393 * 0 - sampled on falling edge of CLKR
394 * valid on falling edge
395 * CLKXP Transmit clock polarity,
396 * 0 - clocked on rising edge of CLKX
397 * valid on falling edge
398 * FSRP Receive frame sync pol, 0 - active high
399 * FSXP Transmit frame sync pol, 0 - active high
400 */
401 break;
402 default:
403 return -EINVAL;
404 }
405 if (inv_fs == true)
406 pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
407 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
408 dev->pcr = pcr;
409 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
410 return 0;
411 }
412
413 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
414 int div_id, int div)
415 {
416 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
417
418 if (div_id != DAVINCI_MCBSP_CLKGDV)
419 return -ENODEV;
420
421 dev->clk_div = div;
422 return 0;
423 }
424
425 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
426 struct snd_pcm_hw_params *params,
427 struct snd_soc_dai *dai)
428 {
429 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
430 struct snd_interval *i = NULL;
431 int mcbsp_word_length, master;
432 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
433 u32 spcr;
434 snd_pcm_format_t fmt;
435 unsigned element_cnt = 1;
436
437 /* general line settings */
438 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
439 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
440 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
441 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
442 } else {
443 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
444 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
445 }
446
447 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
448 fmt = params_format(params);
449 mcbsp_word_length = asp_word_length[fmt];
450
451 switch (master) {
452 case SND_SOC_DAIFMT_CBS_CFS:
453 freq = clk_get_rate(dev->clk);
454 srgr = DAVINCI_MCBSP_SRGR_FSGM |
455 DAVINCI_MCBSP_SRGR_CLKSM;
456 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
457 8 - 1);
458 if (dev->i2s_accurate_sck) {
459 clk_div = 256;
460 do {
461 framesize = (freq / (--clk_div)) /
462 params->rate_num *
463 params->rate_den;
464 } while (((framesize < 33) || (framesize > 4095)) &&
465 (clk_div));
466 clk_div--;
467 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
468 } else {
469 /* symmetric waveforms */
470 clk_div = freq / (mcbsp_word_length * 16) /
471 params->rate_num * params->rate_den;
472 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
473 16 - 1);
474 }
475 clk_div &= 0xFF;
476 srgr |= clk_div;
477 break;
478 case SND_SOC_DAIFMT_CBM_CFS:
479 srgr = DAVINCI_MCBSP_SRGR_FSGM;
480 clk_div = dev->clk_div - 1;
481 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
482 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
483 clk_div &= 0xFF;
484 srgr |= clk_div;
485 break;
486 case SND_SOC_DAIFMT_CBM_CFM:
487 /* Clock and frame sync given from external sources */
488 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
489 srgr = DAVINCI_MCBSP_SRGR_FSGM;
490 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
491 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
492 __func__, __LINE__, snd_interval_value(i) - 1);
493
494 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
495 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
496 break;
497 default:
498 return -EINVAL;
499 }
500 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
501
502 rcr = DAVINCI_MCBSP_RCR_RFIG;
503 xcr = DAVINCI_MCBSP_XCR_XFIG;
504 if (dev->mode == MOD_DSP_B) {
505 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
506 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
507 } else {
508 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
509 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
510 }
511 /* Determine xfer data type */
512 fmt = params_format(params);
513 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
514 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
515 return -EINVAL;
516 }
517
518 if (params_channels(params) == 2) {
519 element_cnt = 2;
520 if (double_fmt[fmt] && dev->enable_channel_combine) {
521 element_cnt = 1;
522 fmt = double_fmt[fmt];
523 }
524 switch (master) {
525 case SND_SOC_DAIFMT_CBS_CFS:
526 case SND_SOC_DAIFMT_CBS_CFM:
527 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
528 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
529 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
530 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
531 break;
532 case SND_SOC_DAIFMT_CBM_CFM:
533 case SND_SOC_DAIFMT_CBM_CFS:
534 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
535 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
536 break;
537 default:
538 return -EINVAL;
539 }
540 }
541 mcbsp_word_length = asp_word_length[fmt];
542
543 switch (master) {
544 case SND_SOC_DAIFMT_CBS_CFS:
545 case SND_SOC_DAIFMT_CBS_CFM:
546 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
547 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
548 break;
549 case SND_SOC_DAIFMT_CBM_CFM:
550 case SND_SOC_DAIFMT_CBM_CFS:
551 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
552 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
553 break;
554 default:
555 return -EINVAL;
556 }
557
558 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
559 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
560 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
561 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
562
563 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
564 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
565 else
566 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
567
568 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
569 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
570 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
571 return 0;
572 }
573
574 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
575 struct snd_soc_dai *dai)
576 {
577 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
578 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
579 davinci_mcbsp_stop(dev, playback);
580 return 0;
581 }
582
583 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
584 struct snd_soc_dai *dai)
585 {
586 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
587 int ret = 0;
588 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
589
590 switch (cmd) {
591 case SNDRV_PCM_TRIGGER_START:
592 case SNDRV_PCM_TRIGGER_RESUME:
593 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
594 davinci_mcbsp_start(dev, substream);
595 break;
596 case SNDRV_PCM_TRIGGER_STOP:
597 case SNDRV_PCM_TRIGGER_SUSPEND:
598 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
599 davinci_mcbsp_stop(dev, playback);
600 break;
601 default:
602 ret = -EINVAL;
603 }
604 return ret;
605 }
606
607 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
608 struct snd_soc_dai *dai)
609 {
610 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
611 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
612 davinci_mcbsp_stop(dev, playback);
613 }
614
615 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
616
617 static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
618 .shutdown = davinci_i2s_shutdown,
619 .prepare = davinci_i2s_prepare,
620 .trigger = davinci_i2s_trigger,
621 .hw_params = davinci_i2s_hw_params,
622 .set_fmt = davinci_i2s_set_dai_fmt,
623 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
624
625 };
626
627 static int davinci_i2s_dai_probe(struct snd_soc_dai *dai)
628 {
629 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
630
631 dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
632 dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
633
634 return 0;
635 }
636
637 static struct snd_soc_dai_driver davinci_i2s_dai = {
638 .probe = davinci_i2s_dai_probe,
639 .playback = {
640 .channels_min = 2,
641 .channels_max = 2,
642 .rates = DAVINCI_I2S_RATES,
643 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
644 .capture = {
645 .channels_min = 2,
646 .channels_max = 2,
647 .rates = DAVINCI_I2S_RATES,
648 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
649 .ops = &davinci_i2s_dai_ops,
650
651 };
652
653 static const struct snd_soc_component_driver davinci_i2s_component = {
654 .name = "davinci-i2s",
655 };
656
657 static int davinci_i2s_probe(struct platform_device *pdev)
658 {
659 struct snd_dmaengine_dai_dma_data *dma_data;
660 struct davinci_mcbsp_dev *dev;
661 struct resource *mem, *res;
662 void __iomem *io_base;
663 int *dma;
664 int ret;
665
666 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
667 if (!mem) {
668 dev_warn(&pdev->dev,
669 "\"mpu\" mem resource not found, using index 0\n");
670 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
671 if (!mem) {
672 dev_err(&pdev->dev, "no mem resource?\n");
673 return -ENODEV;
674 }
675 }
676
677 io_base = devm_ioremap_resource(&pdev->dev, mem);
678 if (IS_ERR(io_base))
679 return PTR_ERR(io_base);
680
681 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
682 GFP_KERNEL);
683 if (!dev)
684 return -ENOMEM;
685
686 dev->base = io_base;
687
688 /* setup DMA, first TX, then RX */
689 dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
690 dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
691
692 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
693 if (res) {
694 dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
695 *dma = res->start;
696 dma_data->filter_data = dma;
697 } else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
698 dma_data->filter_data = "tx";
699 } else {
700 dev_err(&pdev->dev, "Missing DMA tx resource\n");
701 return -ENODEV;
702 }
703
704 dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
705 dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
706
707 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
708 if (res) {
709 dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
710 *dma = res->start;
711 dma_data->filter_data = dma;
712 } else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
713 dma_data->filter_data = "rx";
714 } else {
715 dev_err(&pdev->dev, "Missing DMA rx resource\n");
716 return -ENODEV;
717 }
718
719 dev->clk = clk_get(&pdev->dev, NULL);
720 if (IS_ERR(dev->clk))
721 return -ENODEV;
722 clk_enable(dev->clk);
723
724 dev->dev = &pdev->dev;
725 dev_set_drvdata(&pdev->dev, dev);
726
727 ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
728 &davinci_i2s_dai, 1);
729 if (ret != 0)
730 goto err_release_clk;
731
732 ret = edma_pcm_platform_register(&pdev->dev);
733 if (ret) {
734 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
735 goto err_unregister_component;
736 }
737
738 return 0;
739
740 err_unregister_component:
741 snd_soc_unregister_component(&pdev->dev);
742 err_release_clk:
743 clk_disable(dev->clk);
744 clk_put(dev->clk);
745 return ret;
746 }
747
748 static int davinci_i2s_remove(struct platform_device *pdev)
749 {
750 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
751
752 snd_soc_unregister_component(&pdev->dev);
753
754 clk_disable(dev->clk);
755 clk_put(dev->clk);
756 dev->clk = NULL;
757
758 return 0;
759 }
760
761 static const struct of_device_id davinci_i2s_match[] = {
762 { .compatible = "ti,da850-mcbsp" },
763 {},
764 };
765 MODULE_DEVICE_TABLE(of, davinci_i2s_match);
766
767 static struct platform_driver davinci_mcbsp_driver = {
768 .probe = davinci_i2s_probe,
769 .remove = davinci_i2s_remove,
770 .driver = {
771 .name = "davinci-mcbsp",
772 .of_match_table = of_match_ptr(davinci_i2s_match),
773 },
774 };
775
776 module_platform_driver(davinci_mcbsp_driver);
777
778 MODULE_AUTHOR("Vladimir Barinov");
779 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
780 MODULE_LICENSE("GPL");
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