drivers/video/geode/lxfb_ops.c

   1 /* Geode LX framebuffer driver
   2  *
   3  * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/fb.h>
  14 #include <linux/uaccess.h>
  15 #include <linux/delay.h>
  16 #include <linux/cs5535.h>
  17
  18 #include "lxfb.h"
  19
  20 /* TODO
  21  * Support panel scaling
  22  * Add acceleration
  23  * Add support for interlacing (TV out)
  24  * Support compression
  25  */
  26
  27 /* This is the complete list of PLL frequencies that we can set -
  28  * we will choose the closest match to the incoming clock.
  29  * freq is the frequency of the dotclock * 1000 (for example,
  30  * 24823 = 24.983 Mhz).
  31  * pllval is the corresponding PLL value
  32 */
  33
  34 static const struct {
  35   unsigned int pllval;
  36   unsigned int freq;
  37 } pll_table[] = {
  38   { 0x000131AC,   6231 },
  39   { 0x0001215D,   6294 },
  40   { 0x00011087,   6750 },
  41   { 0x0001216C,   7081 },
  42   { 0x0001218D,   7140 },
  43   { 0x000110C9,   7800 },
  44   { 0x00013147,   7875 },
  45   { 0x000110A7,   8258 },
  46   { 0x00012159,   8778 },
  47   { 0x00014249,   8875 },
  48   { 0x00010057,   9000 },
  49   { 0x0001219A,   9472 },
  50   { 0x00012158,   9792 },
  51   { 0x00010045,  10000 },
  52   { 0x00010089,  10791 },
  53   { 0x000110E7,  11225 },
  54   { 0x00012136,  11430 },
  55   { 0x00013207,  12375 },
  56   { 0x00012187,  12500 },
  57   { 0x00014286,  14063 },
  58   { 0x000110E5,  15016 },
  59   { 0x00014214,  16250 },
  60   { 0x00011105,  17045 },
  61   { 0x000131E4,  18563 },
  62   { 0x00013183,  18750 },
  63   { 0x00014284,  19688 },
  64   { 0x00011104,  20400 },
  65   { 0x00016363,  23625 },
  66   { 0x000031AC,  24923 },
  67   { 0x0000215D,  25175 },
  68   { 0x00001087,  27000 },
  69   { 0x0000216C,  28322 },
  70   { 0x0000218D,  28560 },
  71   { 0x000010C9,  31200 },
  72   { 0x00003147,  31500 },
  73   { 0x000010A7,  33032 },
  74   { 0x00002159,  35112 },
  75   { 0x00004249,  35500 },
  76   { 0x00000057,  36000 },
  77   { 0x0000219A,  37889 },
  78   { 0x00002158,  39168 },
  79   { 0x00000045,  40000 },
  80   { 0x00000089,  43163 },
  81   { 0x000010E7,  44900 },
  82   { 0x00002136,  45720 },
  83   { 0x00003207,  49500 },
  84   { 0x00002187,  50000 },
  85   { 0x00004286,  56250 },
  86   { 0x000010E5,  60065 },
  87   { 0x00004214,  65000 },
  88   { 0x00001105,  68179 },
  89   { 0x000031E4,  74250 },
  90   { 0x00003183,  75000 },
  91   { 0x00004284,  78750 },
  92   { 0x00001104,  81600 },
  93   { 0x00006363,  94500 },
  94   { 0x00005303,  97520 },
  95   { 0x00002183, 100187 },
  96   { 0x00002122, 101420 },
  97   { 0x00001081, 108000 },
  98   { 0x00006201, 113310 },
  99   { 0x00000041, 119650 },
 100   { 0x000041A1, 129600 },
 101   { 0x00002182, 133500 },
 102   { 0x000041B1, 135000 },
 103   { 0x00000051, 144000 },
 104   { 0x000041E1, 148500 },
 105   { 0x000062D1, 157500 },
 106   { 0x000031A1, 162000 },
 107   { 0x00000061, 169203 },
 108   { 0x00004231, 172800 },
 109   { 0x00002151, 175500 },
 110   { 0x000052E1, 189000 },
 111   { 0x00000071, 192000 },
 112   { 0x00003201, 198000 },
 113   { 0x00004291, 202500 },
 114   { 0x00001101, 204750 },
 115   { 0x00007481, 218250 },
 116   { 0x00004170, 229500 },
 117   { 0x00006210, 234000 },
 118   { 0x00003140, 251182 },
 119   { 0x00006250, 261000 },
 120   { 0x000041C0, 278400 },
 121   { 0x00005220, 280640 },
 122   { 0x00000050, 288000 },
 123   { 0x000041E0, 297000 },
 124   { 0x00002130, 320207 }
 125 };
 126
 127
 128 static void lx_set_dotpll(u32 pllval)
 129 {
 130         u32 dotpll_lo, dotpll_hi;
 131         int i;
 132
 133         rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 134
 135         if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
 136                 return;
 137
 138         dotpll_hi = pllval;
 139         dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
 140         dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
 141
 142         wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 143
 144         /* Wait 100us for the PLL to lock */
 145
 146         udelay(100);
 147
 148         /* Now, loop for the lock bit */
 149
 150         for (i = 0; i < 1000; i++) {
 151                 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 152                 if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
 153                         break;
 154         }
 155
 156         /* Clear the reset bit */
 157
 158         dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
 159         wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 160 }
 161
 162 /* Set the clock based on the frequency specified by the current mode */
 163
 164 static void lx_set_clock(struct fb_info *info)
 165 {
 166         unsigned int diff, min, best = 0;
 167         unsigned int freq, i;
 168
 169         freq = (unsigned int) (1000000000 / info->var.pixclock);
 170
 171         min = abs(pll_table[0].freq - freq);
 172
 173         for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
 174                 diff = abs(pll_table[i].freq - freq);
 175                 if (diff < min) {
 176                         min = diff;
 177                         best = i;
 178                 }
 179         }
 180
 181         lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
 182 }
 183
 184 static void lx_graphics_disable(struct fb_info *info)
 185 {
 186         struct lxfb_par *par = info->par;
 187         unsigned int val, gcfg;
 188
 189         /* Note:  This assumes that the video is in a quitet state */
 190
 191         write_vp(par, VP_A1T, 0);
 192         write_vp(par, VP_A2T, 0);
 193         write_vp(par, VP_A3T, 0);
 194
 195         /* Turn off the VGA and video enable */
 196         val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE |
 197                         DC_GENERAL_CFG_VIDE);
 198
 199         write_dc(par, DC_GENERAL_CFG, val);
 200
 201         val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN;
 202         write_vp(par, VP_VCFG, val);
 203
 204         write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
 205                         DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS);
 206
 207         val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN;
 208         write_dc(par, DC_GENLK_CTL, val);
 209
 210         val = read_dc(par, DC_CLR_KEY);
 211         write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
 212
 213         /* turn off the panel */
 214         write_fp(par, FP_PM, read_fp(par, FP_PM) & ~FP_PM_P);
 215
 216         val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN;
 217         write_vp(par, VP_MISC, val);
 218
 219         /* Turn off the display */
 220
 221         val = read_vp(par, VP_DCFG);
 222         write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
 223                         VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN));
 224
 225         gcfg = read_dc(par, DC_GENERAL_CFG);
 226         gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE);
 227         write_dc(par, DC_GENERAL_CFG, gcfg);
 228
 229         /* Turn off the TGEN */
 230         val = read_dc(par, DC_DISPLAY_CFG);
 231         val &= ~DC_DISPLAY_CFG_TGEN;
 232         write_dc(par, DC_DISPLAY_CFG, val);
 233
 234         /* Wait 1000 usecs to ensure that the TGEN is clear */
 235         udelay(1000);
 236
 237         /* Turn off the FIFO loader */
 238
 239         gcfg &= ~DC_GENERAL_CFG_DFLE;
 240         write_dc(par, DC_GENERAL_CFG, gcfg);
 241
 242         /* Lastly, wait for the GP to go idle */
 243
 244         do {
 245                 val = read_gp(par, GP_BLT_STATUS);
 246         } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE));
 247 }
 248
 249 static void lx_graphics_enable(struct fb_info *info)
 250 {
 251         struct lxfb_par *par = info->par;
 252         u32 temp, config;
 253
 254         /* Set the video request register */
 255         write_vp(par, VP_VRR, 0);
 256
 257         /* Set up the polarities */
 258
 259         config = read_vp(par, VP_DCFG);
 260
 261         config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY |
 262                         VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL);
 263
 264         config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT
 265                         | VP_DCFG_GV_GAM);
 266
 267         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 268                 config |= VP_DCFG_CRT_HSYNC_POL;
 269
 270         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 271                 config |= VP_DCFG_CRT_VSYNC_POL;
 272
 273         if (par->output & OUTPUT_PANEL) {
 274                 u32 msrlo, msrhi;
 275
 276                 write_fp(par, FP_PT1, 0);
 277                 write_fp(par, FP_PT2, FP_PT2_SCRC);
 278                 write_fp(par, FP_DFC, FP_DFC_BC);
 279
 280                 msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
 281                 msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
 282
 283                 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
 284         }
 285
 286         if (par->output & OUTPUT_CRT) {
 287                 config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
 288                                 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN;
 289         }
 290
 291         write_vp(par, VP_DCFG, config);
 292
 293         /* Turn the CRT dacs back on */
 294
 295         if (par->output & OUTPUT_CRT) {
 296                 temp = read_vp(par, VP_MISC);
 297                 temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN);
 298                 write_vp(par, VP_MISC, temp);
 299         }
 300
 301         /* Turn the panel on (if it isn't already) */
 302         if (par->output & OUTPUT_PANEL)
 303                 write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P);
 304 }
 305
 306 unsigned int lx_framebuffer_size(void)
 307 {
 308         unsigned int val;
 309
 310         if (!cs5535_has_vsa2()) {
 311                 uint32_t hi, lo;
 312
 313                 /* The number of pages is (PMAX - PMIN)+1 */
 314                 rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
 315
 316                 /* PMAX */
 317                 val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
 318                 /* PMIN */
 319                 val -= (lo & 0x000fffff);
 320                 val += 1;
 321
 322                 /* The page size is 4k */
 323                 return (val << 12);
 324         }
 325
 326         /* The frame buffer size is reported by a VSM in VSA II */
 327         /* Virtual Register Class    = 0x02                     */
 328         /* VG_MEM_SIZE (1MB units)   = 0x00                     */
 329
 330         outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
 331         outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
 332
 333         val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE;
 334         return (val << 20);
 335 }
 336
 337 void lx_set_mode(struct fb_info *info)
 338 {
 339         struct lxfb_par *par = info->par;
 340         u64 msrval;
 341
 342         unsigned int max, dv, val, size;
 343
 344         unsigned int gcfg, dcfg;
 345         int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
 346         int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
 347
 348         /* Unlock the DC registers */
 349         write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
 350
 351         lx_graphics_disable(info);
 352
 353         lx_set_clock(info);
 354
 355         /* Set output mode */
 356
 357         rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
 358         msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
 359
 360         if (par->output & OUTPUT_PANEL) {
 361                 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP;
 362
 363                 if (par->output & OUTPUT_CRT)
 364                         msrval |= MSR_LX_GLD_MSR_CONFIG_FPC;
 365                 else
 366                         msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC;
 367         } else
 368                 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT;
 369
 370         wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
 371
 372         /* Clear the various buffers */
 373         /* FIXME:  Adjust for panning here */
 374
 375         write_dc(par, DC_FB_ST_OFFSET, 0);
 376         write_dc(par, DC_CB_ST_OFFSET, 0);
 377         write_dc(par, DC_CURS_ST_OFFSET, 0);
 378
 379         /* FIXME: Add support for interlacing */
 380         /* FIXME: Add support for scaling */
 381
 382         val = read_dc(par, DC_GENLK_CTL);
 383         val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN |
 384                         DC_GENLK_CTL_FLICK_SEL_MASK);
 385
 386         /* Default scaling params */
 387
 388         write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
 389         write_dc(par, DC_IRQ_FILT_CTL, 0);
 390         write_dc(par, DC_GENLK_CTL, val);
 391
 392         /* FIXME:  Support compression */
 393
 394         if (info->fix.line_length > 4096)
 395                 dv = DC_DV_CTL_DV_LINE_SIZE_8K;
 396         else if (info->fix.line_length > 2048)
 397                 dv = DC_DV_CTL_DV_LINE_SIZE_4K;
 398         else if (info->fix.line_length > 1024)
 399                 dv = DC_DV_CTL_DV_LINE_SIZE_2K;
 400         else
 401                 dv = DC_DV_CTL_DV_LINE_SIZE_1K;
 402
 403         max = info->fix.line_length * info->var.yres;
 404         max = (max + 0x3FF) & 0xFFFFFC00;
 405
 406         write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
 407
 408         val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE;
 409         write_dc(par, DC_DV_CTL, val | dv);
 410
 411         size = info->var.xres * (info->var.bits_per_pixel >> 3);
 412
 413         write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
 414         write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
 415
 416         /* Set default watermark values */
 417
 418         rdmsrl(MSR_LX_SPARE_MSR, msrval);
 419
 420         msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
 421                         | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
 422                         | MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M
 423                         | MSR_LX_SPARE_MSR_WM_LPEN_OVRD);
 424         msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM |
 425                         MSR_LX_SPARE_MSR_DIS_INIT_V_PRI;
 426         wrmsrl(MSR_LX_SPARE_MSR, msrval);
 427
 428         gcfg = DC_GENERAL_CFG_DFLE;   /* Display fifo enable */
 429         gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */
 430                         (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT);
 431         gcfg |= DC_GENERAL_CFG_FDTY;  /* Set the frame dirty mode */
 432
 433         dcfg  = DC_DISPLAY_CFG_VDEN;  /* Enable video data */
 434         dcfg |= DC_DISPLAY_CFG_GDEN;  /* Enable graphics */
 435         dcfg |= DC_DISPLAY_CFG_TGEN;  /* Turn on the timing generator */
 436         dcfg |= DC_DISPLAY_CFG_TRUP;  /* Update timings immediately */
 437         dcfg |= DC_DISPLAY_CFG_PALB;  /* Palette bypass in > 8 bpp modes */
 438         dcfg |= DC_DISPLAY_CFG_VISL;
 439         dcfg |= DC_DISPLAY_CFG_DCEN;  /* Always center the display */
 440
 441         /* Set the current BPP mode */
 442
 443         switch (info->var.bits_per_pixel) {
 444         case 8:
 445                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
 446                 break;
 447
 448         case 16:
 449                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
 450                 break;
 451
 452         case 32:
 453         case 24:
 454                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
 455                 break;
 456         }
 457
 458         /* Now - set up the timings */
 459
 460         hactive = info->var.xres;
 461         hblankstart = hactive;
 462         hsyncstart = hblankstart + info->var.right_margin;
 463         hsyncend =  hsyncstart + info->var.hsync_len;
 464         hblankend = hsyncend + info->var.left_margin;
 465         htotal = hblankend;
 466
 467         vactive = info->var.yres;
 468         vblankstart = vactive;
 469         vsyncstart = vblankstart + info->var.lower_margin;
 470         vsyncend =  vsyncstart + info->var.vsync_len;
 471         vblankend = vsyncend + info->var.upper_margin;
 472         vtotal = vblankend;
 473
 474         write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
 475         write_dc(par, DC_H_BLANK_TIMING,
 476                         (hblankstart - 1) | ((hblankend - 1) << 16));
 477         write_dc(par, DC_H_SYNC_TIMING,
 478                         (hsyncstart - 1) | ((hsyncend - 1) << 16));
 479
 480         write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
 481         write_dc(par, DC_V_BLANK_TIMING,
 482                         (vblankstart - 1) | ((vblankend - 1) << 16));
 483         write_dc(par, DC_V_SYNC_TIMING,
 484                         (vsyncstart - 1) | ((vsyncend - 1) << 16));
 485
 486         write_dc(par, DC_FB_ACTIVE,
 487                         (info->var.xres - 1) << 16 | (info->var.yres - 1));
 488
 489         /* And re-enable the graphics output */
 490         lx_graphics_enable(info);
 491
 492         /* Write the two main configuration registers */
 493         write_dc(par, DC_DISPLAY_CFG, dcfg);
 494         write_dc(par, DC_ARB_CFG, 0);
 495         write_dc(par, DC_GENERAL_CFG, gcfg);
 496
 497         /* Lock the DC registers */
 498         write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
 499 }
 500
 501 void lx_set_palette_reg(struct fb_info *info, unsigned regno,
 502                         unsigned red, unsigned green, unsigned blue)
 503 {
 504         struct lxfb_par *par = info->par;
 505         int val;
 506
 507         /* Hardware palette is in RGB 8-8-8 format. */
 508
 509         val  = (red   << 8) & 0xff0000;
 510         val |= (green)      & 0x00ff00;
 511         val |= (blue  >> 8) & 0x0000ff;
 512
 513         write_dc(par, DC_PAL_ADDRESS, regno);
 514         write_dc(par, DC_PAL_DATA, val);
 515 }
 516
 517 int lx_blank_display(struct fb_info *info, int blank_mode)
 518 {
 519         struct lxfb_par *par = info->par;
 520         u32 dcfg, misc, fp_pm;
 521         int blank, hsync, vsync;
 522
 523         /* CRT power saving modes. */
 524         switch (blank_mode) {
 525         case FB_BLANK_UNBLANK:
 526                 blank = 0; hsync = 1; vsync = 1;
 527                 break;
 528         case FB_BLANK_NORMAL:
 529                 blank = 1; hsync = 1; vsync = 1;
 530                 break;
 531         case FB_BLANK_VSYNC_SUSPEND:
 532                 blank = 1; hsync = 1; vsync = 0;
 533                 break;
 534         case FB_BLANK_HSYNC_SUSPEND:
 535                 blank = 1; hsync = 0; vsync = 1;
 536                 break;
 537         case FB_BLANK_POWERDOWN:
 538                 blank = 1; hsync = 0; vsync = 0;
 539                 break;
 540         default:
 541                 return -EINVAL;
 542         }
 543
 544         dcfg = read_vp(par, VP_DCFG);
 545         dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
 546                         VP_DCFG_CRT_EN);
 547         if (!blank)
 548                 dcfg |= VP_DCFG_DAC_BL_EN | VP_DCFG_CRT_EN;
 549         if (hsync)
 550                 dcfg |= VP_DCFG_HSYNC_EN;
 551         if (vsync)
 552                 dcfg |= VP_DCFG_VSYNC_EN;
 553
 554         write_vp(par, VP_DCFG, dcfg);
 555
 556         misc = read_vp(par, VP_MISC);
 557
 558         if (vsync && hsync)
 559                 misc &= ~VP_MISC_DACPWRDN;
 560         else
 561                 misc |= VP_MISC_DACPWRDN;
 562
 563         write_vp(par, VP_MISC, misc);
 564
 565         /* Power on/off flat panel */
 566
 567         if (par->output & OUTPUT_PANEL) {
 568                 fp_pm = read_fp(par, FP_PM);
 569                 if (blank_mode == FB_BLANK_POWERDOWN)
 570                         fp_pm &= ~FP_PM_P;
 571                 else
 572                         fp_pm |= FP_PM_P;
 573                 write_fp(par, FP_PM, fp_pm);
 574         }
 575
 576         return 0;
 577 }
 578
 579 #ifdef CONFIG_PM
 580
 581 static void lx_save_regs(struct lxfb_par *par)
 582 {
 583         uint32_t filt;
 584         int i;
 585
 586         /* wait for the BLT engine to stop being busy */
 587         do {
 588                 i = read_gp(par, GP_BLT_STATUS);
 589         } while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE));
 590
 591         /* save MSRs */
 592         rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
 593         rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
 594         rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
 595         rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
 596
 597         write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
 598
 599         /* save registers */
 600         memcpy(par->gp, par->gp_regs, sizeof(par->gp));
 601         memcpy(par->dc, par->dc_regs, sizeof(par->dc));
 602         memcpy(par->vp, par->vp_regs, sizeof(par->vp));
 603         memcpy(par->fp, par->vp_regs + VP_FP_START, sizeof(par->fp));
 604
 605         /* save the palette */
 606         write_dc(par, DC_PAL_ADDRESS, 0);
 607         for (i = 0; i < ARRAY_SIZE(par->pal); i++)
 608                 par->pal[i] = read_dc(par, DC_PAL_DATA);
 609
 610         /* save the horizontal filter coefficients */
 611         filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
 612         for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
 613                 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
 614                 par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1);
 615                 par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2);
 616         }
 617
 618         /* save the vertical filter coefficients */
 619         filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
 620         for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
 621                 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
 622                 par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1);
 623         }
 624
 625         /* save video coeff ram */
 626         memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff));
 627 }
 628
 629 static void lx_restore_gfx_proc(struct lxfb_par *par)
 630 {
 631         int i;
 632
 633         /* a bunch of registers require GP_RASTER_MODE to be set first */
 634         write_gp(par, GP_RASTER_MODE, par->gp[GP_RASTER_MODE]);
 635
 636         for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
 637                 switch (i) {
 638                 case GP_RASTER_MODE:
 639                 case GP_VECTOR_MODE:
 640                 case GP_BLT_MODE:
 641                 case GP_BLT_STATUS:
 642                 case GP_HST_SRC:
 643                         /* FIXME: restore LUT data */
 644                 case GP_LUT_INDEX:
 645                 case GP_LUT_DATA:
 646                         /* don't restore these registers */
 647                         break;
 648
 649                 default:
 650                         write_gp(par, i, par->gp[i]);
 651                 }
 652         }
 653 }
 654
 655 static void lx_restore_display_ctlr(struct lxfb_par *par)
 656 {
 657         uint32_t filt;
 658         int i;
 659
 660         wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
 661
 662         for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
 663                 switch (i) {
 664                 case DC_UNLOCK:
 665                         /* unlock the DC; runs first */
 666                         write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
 667                         break;
 668
 669                 case DC_GENERAL_CFG:
 670                 case DC_DISPLAY_CFG:
 671                         /* disable all while restoring */
 672                         write_dc(par, i, 0);
 673                         break;
 674
 675                 case DC_DV_CTL:
 676                         /* set all ram to dirty */
 677                         write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);
 678
 679                 case DC_RSVD_1:
 680                 case DC_RSVD_2:
 681                 case DC_RSVD_3:
 682                 case DC_LINE_CNT:
 683                 case DC_PAL_ADDRESS:
 684                 case DC_PAL_DATA:
 685                 case DC_DFIFO_DIAG:
 686                 case DC_CFIFO_DIAG:
 687                 case DC_FILT_COEFF1:
 688                 case DC_FILT_COEFF2:
 689                 case DC_RSVD_4:
 690                 case DC_RSVD_5:
 691                         /* don't restore these registers */
 692                         break;
 693
 694                 default:
 695                         write_dc(par, i, par->dc[i]);
 696                 }
 697         }
 698
 699         /* restore the palette */
 700         write_dc(par, DC_PAL_ADDRESS, 0);
 701         for (i = 0; i < ARRAY_SIZE(par->pal); i++)
 702                 write_dc(par, DC_PAL_DATA, par->pal[i]);
 703
 704         /* restore the horizontal filter coefficients */
 705         filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
 706         for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
 707                 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
 708                 write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]);
 709                 write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]);
 710         }
 711
 712         /* restore the vertical filter coefficients */
 713         filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
 714         for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
 715                 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
 716                 write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]);
 717         }
 718 }
 719
 720 static void lx_restore_video_proc(struct lxfb_par *par)
 721 {
 722         int i;
 723
 724         wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
 725         wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
 726
 727         for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
 728                 switch (i) {
 729                 case VP_VCFG:
 730                 case VP_DCFG:
 731                 case VP_PAR:
 732                 case VP_PDR:
 733                 case VP_CCS:
 734                 case VP_RSVD_0:
 735                 /* case VP_VDC: */ /* why should this not be restored? */
 736                 case VP_RSVD_1:
 737                 case VP_CRC32:
 738                         /* don't restore these registers */
 739                         break;
 740
 741                 default:
 742                         write_vp(par, i, par->vp[i]);
 743                 }
 744         }
 745
 746         /* restore video coeff ram */
 747         memcpy(par->vp_regs + VP_VCR, par->vp_coeff, sizeof(par->vp_coeff));
 748 }
 749
 750 static void lx_restore_regs(struct lxfb_par *par)
 751 {
 752         int i;
 753
 754         lx_set_dotpll((u32) (par->msr.dotpll >> 32));
 755         lx_restore_gfx_proc(par);
 756         lx_restore_display_ctlr(par);
 757         lx_restore_video_proc(par);
 758
 759         /* Flat Panel */
 760         for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
 761                 switch (i) {
 762                 case FP_PM:
 763                 case FP_RSVD_0:
 764                 case FP_RSVD_1:
 765                 case FP_RSVD_2:
 766                 case FP_RSVD_3:
 767                 case FP_RSVD_4:
 768                         /* don't restore these registers */
 769                         break;
 770
 771                 default:
 772                         write_fp(par, i, par->fp[i]);
 773                 }
 774         }
 775
 776         /* control the panel */
 777         if (par->fp[FP_PM] & FP_PM_P) {
 778                 /* power on the panel if not already power{ed,ing} on */
 779                 if (!(read_fp(par, FP_PM) &
 780                                 (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
 781                         write_fp(par, FP_PM, par->fp[FP_PM]);
 782         } else {
 783                 /* power down the panel if not already power{ed,ing} down */
 784                 if (!(read_fp(par, FP_PM) &
 785                                 (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
 786                         write_fp(par, FP_PM, par->fp[FP_PM]);
 787         }
 788
 789         /* turn everything on */
 790         write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
 791         write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
 792         write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
 793         /* do this last; it will enable the FIFO load */
 794         write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
 795
 796         /* lock the door behind us */
 797         write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
 798 }
 799
 800 int lx_powerdown(struct fb_info *info)
 801 {
 802         struct lxfb_par *par = info->par;
 803
 804         if (par->powered_down)
 805                 return 0;
 806
 807         lx_save_regs(par);
 808         lx_graphics_disable(info);
 809
 810         par->powered_down = 1;
 811         return 0;
 812 }
 813
 814 int lx_powerup(struct fb_info *info)
 815 {
 816         struct lxfb_par *par = info->par;
 817
 818         if (!par->powered_down)
 819                 return 0;
 820
 821         lx_restore_regs(par);
 822
 823         par->powered_down = 0;
 824         return 0;
 825 }
 826
 827 #endif