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Linux 2.6.33-rc6
[cris-mirror.git] / drivers / video / omap / lcdc.c
bloba33483910dc8361aaf86a84714b9f0705164e499
1 /*
2 * OMAP1 internal LCD controller
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Imre Deak <imre.deak@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/spinlock.h>
25 #include <linux/err.h>
26 #include <linux/mm.h>
27 #include <linux/fb.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/vmalloc.h>
30 #include <linux/clk.h>
31
32 #include <mach/lcdc.h>
33 #include <plat/dma.h>
34
35 #include <asm/mach-types.h>
36
37 #include "omapfb.h"
38
39 #include "lcdc.h"
40
41 #define MODULE_NAME "lcdc"
42
43 #define MAX_PALETTE_SIZE PAGE_SIZE
44
45 enum lcdc_load_mode {
46 OMAP_LCDC_LOAD_PALETTE,
47 OMAP_LCDC_LOAD_FRAME,
48 OMAP_LCDC_LOAD_PALETTE_AND_FRAME
49 };
50
51 static struct omap_lcd_controller {
52 enum omapfb_update_mode update_mode;
53 int ext_mode;
54
55 unsigned long frame_offset;
56 int screen_width;
57 int xres;
58 int yres;
59
60 enum omapfb_color_format color_mode;
61 int bpp;
62 void *palette_virt;
63 dma_addr_t palette_phys;
64 int palette_code;
65 int palette_size;
66
67 unsigned int irq_mask;
68 struct completion last_frame_complete;
69 struct completion palette_load_complete;
70 struct clk *lcd_ck;
71 struct omapfb_device *fbdev;
72
73 void (*dma_callback)(void *data);
74 void *dma_callback_data;
75
76 int fbmem_allocated;
77 dma_addr_t vram_phys;
78 void *vram_virt;
79 unsigned long vram_size;
80 } lcdc;
81
82 static void inline enable_irqs(int mask)
83 {
84 lcdc.irq_mask |= mask;
85 }
86
87 static void inline disable_irqs(int mask)
88 {
89 lcdc.irq_mask &= ~mask;
90 }
91
92 static void set_load_mode(enum lcdc_load_mode mode)
93 {
94 u32 l;
95
96 l = omap_readl(OMAP_LCDC_CONTROL);
97 l &= ~(3 << 20);
98 switch (mode) {
99 case OMAP_LCDC_LOAD_PALETTE:
100 l |= 1 << 20;
101 break;
102 case OMAP_LCDC_LOAD_FRAME:
103 l |= 2 << 20;
104 break;
105 case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
106 break;
107 default:
108 BUG();
109 }
110 omap_writel(l, OMAP_LCDC_CONTROL);
111 }
112
113 static void enable_controller(void)
114 {
115 u32 l;
116
117 l = omap_readl(OMAP_LCDC_CONTROL);
118 l |= OMAP_LCDC_CTRL_LCD_EN;
119 l &= ~OMAP_LCDC_IRQ_MASK;
120 l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */
121 omap_writel(l, OMAP_LCDC_CONTROL);
122 }
123
124 static void disable_controller_async(void)
125 {
126 u32 l;
127 u32 mask;
128
129 l = omap_readl(OMAP_LCDC_CONTROL);
130 mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
131 /*
132 * Preserve the DONE mask, since we still want to get the
133 * final DONE irq. It will be disabled in the IRQ handler.
134 */
135 mask &= ~OMAP_LCDC_IRQ_DONE;
136 l &= ~mask;
137 omap_writel(l, OMAP_LCDC_CONTROL);
138 }
139
140 static void disable_controller(void)
141 {
142 init_completion(&lcdc.last_frame_complete);
143 disable_controller_async();
144 if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
145 msecs_to_jiffies(500)))
146 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
147 }
148
149 static void reset_controller(u32 status)
150 {
151 static unsigned long reset_count;
152 static unsigned long last_jiffies;
153
154 disable_controller_async();
155 reset_count++;
156 if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
157 dev_err(lcdc.fbdev->dev,
158 "resetting (status %#010x,reset count %lu)\n",
159 status, reset_count);
160 last_jiffies = jiffies;
161 }
162 if (reset_count < 100) {
163 enable_controller();
164 } else {
165 reset_count = 0;
166 dev_err(lcdc.fbdev->dev,
167 "too many reset attempts, giving up.\n");
168 }
169 }
170
171 /*
172 * Configure the LCD DMA according to the current mode specified by parameters
173 * in lcdc.fbdev and fbdev->var.
174 */
175 static void setup_lcd_dma(void)
176 {
177 static const int dma_elem_type[] = {
178 0,
179 OMAP_DMA_DATA_TYPE_S8,
180 OMAP_DMA_DATA_TYPE_S16,
181 0,
182 OMAP_DMA_DATA_TYPE_S32,
183 };
184 struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
185 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
186 unsigned long src;
187 int esize, xelem, yelem;
188
189 src = lcdc.vram_phys + lcdc.frame_offset;
190
191 switch (var->rotate) {
192 case 0:
193 if (plane->info.mirror || (src & 3) ||
194 lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
195 (lcdc.xres & 1))
196 esize = 2;
197 else
198 esize = 4;
199 xelem = lcdc.xres * lcdc.bpp / 8 / esize;
200 yelem = lcdc.yres;
201 break;
202 case 90:
203 case 180:
204 case 270:
205 if (cpu_is_omap15xx()) {
206 BUG();
207 }
208 esize = 2;
209 xelem = lcdc.yres * lcdc.bpp / 16;
210 yelem = lcdc.xres;
211 break;
212 default:
213 BUG();
214 return;
215 }
216 #ifdef VERBOSE
217 dev_dbg(lcdc.fbdev->dev,
218 "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
219 src, esize, xelem, yelem);
220 #endif
221 omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
222 if (!cpu_is_omap15xx()) {
223 int bpp = lcdc.bpp;
224
225 /*
226 * YUV support is only for external mode when we have the
227 * YUV window embedded in a 16bpp frame buffer.
228 */
229 if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
230 bpp = 16;
231 /* Set virtual xres elem size */
232 omap_set_lcd_dma_b1_vxres(
233 lcdc.screen_width * bpp / 8 / esize);
234 /* Setup transformations */
235 omap_set_lcd_dma_b1_rotation(var->rotate);
236 omap_set_lcd_dma_b1_mirror(plane->info.mirror);
237 }
238 omap_setup_lcd_dma();
239 }
240
241 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
242 {
243 u32 status;
244
245 status = omap_readl(OMAP_LCDC_STATUS);
246
247 if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
248 reset_controller(status);
249 else {
250 if (status & OMAP_LCDC_STAT_DONE) {
251 u32 l;
252
253 /*
254 * Disable IRQ_DONE. The status bit will be cleared
255 * only when the controller is reenabled and we don't
256 * want to get more interrupts.
257 */
258 l = omap_readl(OMAP_LCDC_CONTROL);
259 l &= ~OMAP_LCDC_IRQ_DONE;
260 omap_writel(l, OMAP_LCDC_CONTROL);
261 complete(&lcdc.last_frame_complete);
262 }
263 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
264 disable_controller_async();
265 complete(&lcdc.palette_load_complete);
266 }
267 }
268
269 /*
270 * Clear these interrupt status bits.
271 * Sync_lost, FUF bits were cleared by disabling the LCD controller
272 * LOADED_PALETTE can be cleared this way only in palette only
273 * load mode. In other load modes it's cleared by disabling the
274 * controller.
275 */
276 status &= ~(OMAP_LCDC_STAT_VSYNC |
277 OMAP_LCDC_STAT_LOADED_PALETTE |
278 OMAP_LCDC_STAT_ABC |
279 OMAP_LCDC_STAT_LINE_INT);
280 omap_writel(status, OMAP_LCDC_STATUS);
281 return IRQ_HANDLED;
282 }
283
284 /*
285 * Change to a new video mode. We defer this to a later time to avoid any
286 * flicker and not to mess up the current LCD DMA context. For this we disable
287 * the LCD controller, which will generate a DONE irq after the last frame has
288 * been transferred. Then it'll be safe to reconfigure both the LCD controller
289 * as well as the LCD DMA.
290 */
291 static int omap_lcdc_setup_plane(int plane, int channel_out,
292 unsigned long offset, int screen_width,
293 int pos_x, int pos_y, int width, int height,
294 int color_mode)
295 {
296 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
297 struct lcd_panel *panel = lcdc.fbdev->panel;
298 int rot_x, rot_y;
299
300 if (var->rotate == 0) {
301 rot_x = panel->x_res;
302 rot_y = panel->y_res;
303 } else {
304 rot_x = panel->y_res;
305 rot_y = panel->x_res;
306 }
307 if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
308 width > rot_x || height > rot_y) {
309 #ifdef VERBOSE
310 dev_dbg(lcdc.fbdev->dev,
311 "invalid plane params plane %d pos_x %d pos_y %d "
312 "w %d h %d\n", plane, pos_x, pos_y, width, height);
313 #endif
314 return -EINVAL;
315 }
316
317 lcdc.frame_offset = offset;
318 lcdc.xres = width;
319 lcdc.yres = height;
320 lcdc.screen_width = screen_width;
321 lcdc.color_mode = color_mode;
322
323 switch (color_mode) {
324 case OMAPFB_COLOR_CLUT_8BPP:
325 lcdc.bpp = 8;
326 lcdc.palette_code = 0x3000;
327 lcdc.palette_size = 512;
328 break;
329 case OMAPFB_COLOR_RGB565:
330 lcdc.bpp = 16;
331 lcdc.palette_code = 0x4000;
332 lcdc.palette_size = 32;
333 break;
334 case OMAPFB_COLOR_RGB444:
335 lcdc.bpp = 16;
336 lcdc.palette_code = 0x4000;
337 lcdc.palette_size = 32;
338 break;
339 case OMAPFB_COLOR_YUV420:
340 if (lcdc.ext_mode) {
341 lcdc.bpp = 12;
342 break;
343 }
344 /* fallthrough */
345 case OMAPFB_COLOR_YUV422:
346 if (lcdc.ext_mode) {
347 lcdc.bpp = 16;
348 break;
349 }
350 /* fallthrough */
351 default:
352 /* FIXME: other BPPs.
353 * bpp1: code 0, size 256
354 * bpp2: code 0x1000 size 256
355 * bpp4: code 0x2000 size 256
356 * bpp12: code 0x4000 size 32
357 */
358 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
359 BUG();
360 return -1;
361 }
362
363 if (lcdc.ext_mode) {
364 setup_lcd_dma();
365 return 0;
366 }
367
368 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
369 disable_controller();
370 omap_stop_lcd_dma();
371 setup_lcd_dma();
372 enable_controller();
373 }
374
375 return 0;
376 }
377
378 static int omap_lcdc_enable_plane(int plane, int enable)
379 {
380 dev_dbg(lcdc.fbdev->dev,
381 "plane %d enable %d update_mode %d ext_mode %d\n",
382 plane, enable, lcdc.update_mode, lcdc.ext_mode);
383 if (plane != OMAPFB_PLANE_GFX)
384 return -EINVAL;
385
386 return 0;
387 }
388
389 /*
390 * Configure the LCD DMA for a palette load operation and do the palette
391 * downloading synchronously. We don't use the frame+palette load mode of
392 * the controller, since the palette can always be downloaded seperately.
393 */
394 static void load_palette(void)
395 {
396 u16 *palette;
397
398 palette = (u16 *)lcdc.palette_virt;
399
400 *(u16 *)palette &= 0x0fff;
401 *(u16 *)palette |= lcdc.palette_code;
402
403 omap_set_lcd_dma_b1(lcdc.palette_phys,
404 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
405
406 omap_set_lcd_dma_single_transfer(1);
407 omap_setup_lcd_dma();
408
409 init_completion(&lcdc.palette_load_complete);
410 enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
411 set_load_mode(OMAP_LCDC_LOAD_PALETTE);
412 enable_controller();
413 if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
414 msecs_to_jiffies(500)))
415 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
416 /* The controller gets disabled in the irq handler */
417 disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
418 omap_stop_lcd_dma();
419
420 omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
421 }
422
423 /* Used only in internal controller mode */
424 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
425 u16 transp, int update_hw_pal)
426 {
427 u16 *palette;
428
429 if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
430 return -EINVAL;
431
432 palette = (u16 *)lcdc.palette_virt;
433
434 palette[regno] &= ~0x0fff;
435 palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
436 (blue >> 12);
437
438 if (update_hw_pal) {
439 disable_controller();
440 omap_stop_lcd_dma();
441 load_palette();
442 setup_lcd_dma();
443 set_load_mode(OMAP_LCDC_LOAD_FRAME);
444 enable_controller();
445 }
446
447 return 0;
448 }
449
450 static void calc_ck_div(int is_tft, int pck, int *pck_div)
451 {
452 unsigned long lck;
453
454 pck = max(1, pck);
455 lck = clk_get_rate(lcdc.lcd_ck);
456 *pck_div = (lck + pck - 1) / pck;
457 if (is_tft)
458 *pck_div = max(2, *pck_div);
459 else
460 *pck_div = max(3, *pck_div);
461 if (*pck_div > 255) {
462 /* FIXME: try to adjust logic clock divider as well */
463 *pck_div = 255;
464 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
465 pck / 1000);
466 }
467 }
468
469 static void inline setup_regs(void)
470 {
471 u32 l;
472 struct lcd_panel *panel = lcdc.fbdev->panel;
473 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
474 unsigned long lck;
475 int pcd;
476
477 l = omap_readl(OMAP_LCDC_CONTROL);
478 l &= ~OMAP_LCDC_CTRL_LCD_TFT;
479 l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
480 #ifdef CONFIG_MACH_OMAP_PALMTE
481 /* FIXME:if (machine_is_omap_palmte()) { */
482 /* PalmTE uses alternate TFT setting in 8BPP mode */
483 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
484 /* } */
485 #endif
486 omap_writel(l, OMAP_LCDC_CONTROL);
487
488 l = omap_readl(OMAP_LCDC_TIMING2);
489 l &= ~(((1 << 6) - 1) << 20);
490 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
491 omap_writel(l, OMAP_LCDC_TIMING2);
492
493 l = panel->x_res - 1;
494 l |= (panel->hsw - 1) << 10;
495 l |= (panel->hfp - 1) << 16;
496 l |= (panel->hbp - 1) << 24;
497 omap_writel(l, OMAP_LCDC_TIMING0);
498
499 l = panel->y_res - 1;
500 l |= (panel->vsw - 1) << 10;
501 l |= panel->vfp << 16;
502 l |= panel->vbp << 24;
503 omap_writel(l, OMAP_LCDC_TIMING1);
504
505 l = omap_readl(OMAP_LCDC_TIMING2);
506 l &= ~0xff;
507
508 lck = clk_get_rate(lcdc.lcd_ck);
509
510 if (!panel->pcd)
511 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
512 else {
513 dev_warn(lcdc.fbdev->dev,
514 "Pixel clock divider value is obsolete.\n"
515 "Try to set pixel_clock to %lu and pcd to 0 "
516 "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
517 lck / panel->pcd / 1000, panel->name);
518
519 pcd = panel->pcd;
520 }
521 l |= pcd & 0xff;
522 l |= panel->acb << 8;
523 omap_writel(l, OMAP_LCDC_TIMING2);
524
525 /* update panel info with the exact clock */
526 panel->pixel_clock = lck / pcd / 1000;
527 }
528
529 /*
530 * Configure the LCD controller, download the color palette and start a looped
531 * DMA transfer of the frame image data. Called only in internal
532 * controller mode.
533 */
534 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
535 {
536 int r = 0;
537
538 if (mode != lcdc.update_mode) {
539 switch (mode) {
540 case OMAPFB_AUTO_UPDATE:
541 setup_regs();
542 load_palette();
543
544 /* Setup and start LCD DMA */
545 setup_lcd_dma();
546
547 set_load_mode(OMAP_LCDC_LOAD_FRAME);
548 enable_irqs(OMAP_LCDC_IRQ_DONE);
549 /* This will start the actual DMA transfer */
550 enable_controller();
551 lcdc.update_mode = mode;
552 break;
553 case OMAPFB_UPDATE_DISABLED:
554 disable_controller();
555 omap_stop_lcd_dma();
556 lcdc.update_mode = mode;
557 break;
558 default:
559 r = -EINVAL;
560 }
561 }
562
563 return r;
564 }
565
566 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
567 {
568 return lcdc.update_mode;
569 }
570
571 /* PM code called only in internal controller mode */
572 static void omap_lcdc_suspend(void)
573 {
574 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
575 disable_controller();
576 omap_stop_lcd_dma();
577 }
578 }
579
580 static void omap_lcdc_resume(void)
581 {
582 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
583 setup_regs();
584 load_palette();
585 setup_lcd_dma();
586 set_load_mode(OMAP_LCDC_LOAD_FRAME);
587 enable_irqs(OMAP_LCDC_IRQ_DONE);
588 enable_controller();
589 }
590 }
591
592 static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
593 {
594 return;
595 }
596
597 int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
598 {
599 BUG_ON(callback == NULL);
600
601 if (lcdc.dma_callback)
602 return -EBUSY;
603 else {
604 lcdc.dma_callback = callback;
605 lcdc.dma_callback_data = data;
606 }
607 return 0;
608 }
609 EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
610
611 void omap_lcdc_free_dma_callback(void)
612 {
613 lcdc.dma_callback = NULL;
614 }
615 EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
616
617 static void lcdc_dma_handler(u16 status, void *data)
618 {
619 if (lcdc.dma_callback)
620 lcdc.dma_callback(lcdc.dma_callback_data);
621 }
622
623 static int mmap_kern(void)
624 {
625 struct vm_struct *kvma;
626 struct vm_area_struct vma;
627 pgprot_t pgprot;
628 unsigned long vaddr;
629
630 kvma = get_vm_area(lcdc.vram_size, VM_IOREMAP);
631 if (kvma == NULL) {
632 dev_err(lcdc.fbdev->dev, "can't get kernel vm area\n");
633 return -ENOMEM;
634 }
635 vma.vm_mm = &init_mm;
636
637 vaddr = (unsigned long)kvma->addr;
638 vma.vm_start = vaddr;
639 vma.vm_end = vaddr + lcdc.vram_size;
640
641 pgprot = pgprot_writecombine(pgprot_kernel);
642 if (io_remap_pfn_range(&vma, vaddr,
643 lcdc.vram_phys >> PAGE_SHIFT,
644 lcdc.vram_size, pgprot) < 0) {
645 dev_err(lcdc.fbdev->dev, "kernel mmap for FB memory failed\n");
646 return -EAGAIN;
647 }
648
649 lcdc.vram_virt = (void *)vaddr;
650
651 return 0;
652 }
653
654 static void unmap_kern(void)
655 {
656 vunmap(lcdc.vram_virt);
657 }
658
659 static int alloc_palette_ram(void)
660 {
661 lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
662 MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL);
663 if (lcdc.palette_virt == NULL) {
664 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
665 return -ENOMEM;
666 }
667 memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
668
669 return 0;
670 }
671
672 static void free_palette_ram(void)
673 {
674 dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
675 lcdc.palette_virt, lcdc.palette_phys);
676 }
677
678 static int alloc_fbmem(struct omapfb_mem_region *region)
679 {
680 int bpp;
681 int frame_size;
682 struct lcd_panel *panel = lcdc.fbdev->panel;
683
684 bpp = panel->bpp;
685 if (bpp == 12)
686 bpp = 16;
687 frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
688 if (region->size > frame_size)
689 frame_size = region->size;
690 lcdc.vram_size = frame_size;
691 lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
692 lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL);
693 if (lcdc.vram_virt == NULL) {
694 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
695 return -ENOMEM;
696 }
697 region->size = frame_size;
698 region->paddr = lcdc.vram_phys;
699 region->vaddr = lcdc.vram_virt;
700 region->alloc = 1;
701
702 memset(lcdc.vram_virt, 0, lcdc.vram_size);
703
704 return 0;
705 }
706
707 static void free_fbmem(void)
708 {
709 dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size,
710 lcdc.vram_virt, lcdc.vram_phys);
711 }
712
713 static int setup_fbmem(struct omapfb_mem_desc *req_md)
714 {
715 int r;
716
717 if (!req_md->region_cnt) {
718 dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
719 return -EINVAL;
720 }
721
722 if (req_md->region_cnt > 1) {
723 dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
724 req_md->region_cnt = 1;
725 }
726
727 if (req_md->region[0].paddr == 0) {
728 lcdc.fbmem_allocated = 1;
729 if ((r = alloc_fbmem(&req_md->region[0])) < 0)
730 return r;
731 return 0;
732 }
733
734 lcdc.vram_phys = req_md->region[0].paddr;
735 lcdc.vram_size = req_md->region[0].size;
736
737 if ((r = mmap_kern()) < 0)
738 return r;
739
740 dev_dbg(lcdc.fbdev->dev, "vram at %08x size %08lx mapped to 0x%p\n",
741 lcdc.vram_phys, lcdc.vram_size, lcdc.vram_virt);
742
743 return 0;
744 }
745
746 static void cleanup_fbmem(void)
747 {
748 if (lcdc.fbmem_allocated)
749 free_fbmem();
750 else
751 unmap_kern();
752 }
753
754 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
755 struct omapfb_mem_desc *req_vram)
756 {
757 int r;
758 u32 l;
759 int rate;
760 struct clk *tc_ck;
761
762 lcdc.irq_mask = 0;
763
764 lcdc.fbdev = fbdev;
765 lcdc.ext_mode = ext_mode;
766
767 l = 0;
768 omap_writel(l, OMAP_LCDC_CONTROL);
769
770 /* FIXME:
771 * According to errata some platforms have a clock rate limitiation
772 */
773 lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
774 if (IS_ERR(lcdc.lcd_ck)) {
775 dev_err(fbdev->dev, "unable to access LCD clock\n");
776 r = PTR_ERR(lcdc.lcd_ck);
777 goto fail0;
778 }
779
780 tc_ck = clk_get(fbdev->dev, "tc_ck");
781 if (IS_ERR(tc_ck)) {
782 dev_err(fbdev->dev, "unable to access TC clock\n");
783 r = PTR_ERR(tc_ck);
784 goto fail1;
785 }
786
787 rate = clk_get_rate(tc_ck);
788 clk_put(tc_ck);
789
790 if (machine_is_ams_delta())
791 rate /= 4;
792 if (machine_is_omap_h3())
793 rate /= 3;
794 r = clk_set_rate(lcdc.lcd_ck, rate);
795 if (r) {
796 dev_err(fbdev->dev, "failed to adjust LCD rate\n");
797 goto fail1;
798 }
799 clk_enable(lcdc.lcd_ck);
800
801 r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
802 if (r) {
803 dev_err(fbdev->dev, "unable to get IRQ\n");
804 goto fail2;
805 }
806
807 r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
808 if (r) {
809 dev_err(fbdev->dev, "unable to get LCD DMA\n");
810 goto fail3;
811 }
812
813 omap_set_lcd_dma_single_transfer(ext_mode);
814 omap_set_lcd_dma_ext_controller(ext_mode);
815
816 if (!ext_mode)
817 if ((r = alloc_palette_ram()) < 0)
818 goto fail4;
819
820 if ((r = setup_fbmem(req_vram)) < 0)
821 goto fail5;
822
823 pr_info("omapfb: LCDC initialized\n");
824
825 return 0;
826 fail5:
827 if (!ext_mode)
828 free_palette_ram();
829 fail4:
830 omap_free_lcd_dma();
831 fail3:
832 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
833 fail2:
834 clk_disable(lcdc.lcd_ck);
835 fail1:
836 clk_put(lcdc.lcd_ck);
837 fail0:
838 return r;
839 }
840
841 static void omap_lcdc_cleanup(void)
842 {
843 if (!lcdc.ext_mode)
844 free_palette_ram();
845 cleanup_fbmem();
846 omap_free_lcd_dma();
847 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
848 clk_disable(lcdc.lcd_ck);
849 clk_put(lcdc.lcd_ck);
850 }
851
852 const struct lcd_ctrl omap1_int_ctrl = {
853 .name = "internal",
854 .init = omap_lcdc_init,
855 .cleanup = omap_lcdc_cleanup,
856 .get_caps = omap_lcdc_get_caps,
857 .set_update_mode = omap_lcdc_set_update_mode,
858 .get_update_mode = omap_lcdc_get_update_mode,
859 .update_window = NULL,
860 .suspend = omap_lcdc_suspend,
861 .resume = omap_lcdc_resume,
862 .setup_plane = omap_lcdc_setup_plane,
863 .enable_plane = omap_lcdc_enable_plane,
864 .setcolreg = omap_lcdc_setcolreg,
865 };
CRIS linux kernel tree