drivers/char/drm/radeon_drm.h

   1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  *    Keith Whitwell <keith@tungstengraphics.com>
  31  */
  32
  33 #ifndef __RADEON_DRM_H__
  34 #define __RADEON_DRM_H__
  35
  36 /* WARNING: If you change any of these defines, make sure to change the
  37  * defines in the X server file (radeon_sarea.h)
  38  */
  39 #ifndef __RADEON_SAREA_DEFINES__
  40 #define __RADEON_SAREA_DEFINES__
  41
  42 /* Old style state flags, required for sarea interface (1.1 and 1.2
  43  * clears) and 1.2 drm_vertex2 ioctl.
  44  */
  45 #define RADEON_UPLOAD_CONTEXT           0x00000001
  46 #define RADEON_UPLOAD_VERTFMT           0x00000002
  47 #define RADEON_UPLOAD_LINE              0x00000004
  48 #define RADEON_UPLOAD_BUMPMAP           0x00000008
  49 #define RADEON_UPLOAD_MASKS             0x00000010
  50 #define RADEON_UPLOAD_VIEWPORT          0x00000020
  51 #define RADEON_UPLOAD_SETUP             0x00000040
  52 #define RADEON_UPLOAD_TCL               0x00000080
  53 #define RADEON_UPLOAD_MISC              0x00000100
  54 #define RADEON_UPLOAD_TEX0              0x00000200
  55 #define RADEON_UPLOAD_TEX1              0x00000400
  56 #define RADEON_UPLOAD_TEX2              0x00000800
  57 #define RADEON_UPLOAD_TEX0IMAGES        0x00001000
  58 #define RADEON_UPLOAD_TEX1IMAGES        0x00002000
  59 #define RADEON_UPLOAD_TEX2IMAGES        0x00004000
  60 #define RADEON_UPLOAD_CLIPRECTS         0x00008000 /* handled client-side */
  61 #define RADEON_REQUIRE_QUIESCENCE       0x00010000
  62 #define RADEON_UPLOAD_ZBIAS             0x00020000 /* version 1.2 and newer */
  63 #define RADEON_UPLOAD_ALL               0x003effff
  64 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
  65
  66
  67 /* New style per-packet identifiers for use in cmd_buffer ioctl with
  68  * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
  69  * state bits and the packet size:
  70  */
  71 #define RADEON_EMIT_PP_MISC                         0 /* context/7 */
  72 #define RADEON_EMIT_PP_CNTL                         1 /* context/3 */
  73 #define RADEON_EMIT_RB3D_COLORPITCH                 2 /* context/1 */
  74 #define RADEON_EMIT_RE_LINE_PATTERN                 3 /* line/2 */
  75 #define RADEON_EMIT_SE_LINE_WIDTH                   4 /* line/1 */
  76 #define RADEON_EMIT_PP_LUM_MATRIX                   5 /* bumpmap/1 */
  77 #define RADEON_EMIT_PP_ROT_MATRIX_0                 6 /* bumpmap/2 */
  78 #define RADEON_EMIT_RB3D_STENCILREFMASK             7 /* masks/3 */
  79 #define RADEON_EMIT_SE_VPORT_XSCALE                 8 /* viewport/6 */
  80 #define RADEON_EMIT_SE_CNTL                         9 /* setup/2 */
  81 #define RADEON_EMIT_SE_CNTL_STATUS                  10 /* setup/1 */
  82 #define RADEON_EMIT_RE_MISC                         11 /* misc/1 */
  83 #define RADEON_EMIT_PP_TXFILTER_0                   12 /* tex0/6 */
  84 #define RADEON_EMIT_PP_BORDER_COLOR_0               13 /* tex0/1 */
  85 #define RADEON_EMIT_PP_TXFILTER_1                   14 /* tex1/6 */
  86 #define RADEON_EMIT_PP_BORDER_COLOR_1               15 /* tex1/1 */
  87 #define RADEON_EMIT_PP_TXFILTER_2                   16 /* tex2/6 */
  88 #define RADEON_EMIT_PP_BORDER_COLOR_2               17 /* tex2/1 */
  89 #define RADEON_EMIT_SE_ZBIAS_FACTOR                 18 /* zbias/2 */
  90 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19 /* tcl/11 */
  91 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20 /* material/17 */
  92 #define R200_EMIT_PP_TXCBLEND_0                     21 /* tex0/4 */
  93 #define R200_EMIT_PP_TXCBLEND_1                     22 /* tex1/4 */
  94 #define R200_EMIT_PP_TXCBLEND_2                     23 /* tex2/4 */
  95 #define R200_EMIT_PP_TXCBLEND_3                     24 /* tex3/4 */
  96 #define R200_EMIT_PP_TXCBLEND_4                     25 /* tex4/4 */
  97 #define R200_EMIT_PP_TXCBLEND_5                     26 /* tex5/4 */
  98 #define R200_EMIT_PP_TXCBLEND_6                     27 /* /4 */
  99 #define R200_EMIT_PP_TXCBLEND_7                     28 /* /4 */
 100 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29 /* tcl/7 */
 101 #define R200_EMIT_TFACTOR_0                         30 /* tf/7 */
 102 #define R200_EMIT_VTX_FMT_0                         31 /* vtx/5 */
 103 #define R200_EMIT_VAP_CTL                           32 /* vap/1 */
 104 #define R200_EMIT_MATRIX_SELECT_0                   33 /* msl/5 */
 105 #define R200_EMIT_TEX_PROC_CTL_2                    34 /* tcg/5 */
 106 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35 /* tcl/1 */
 107 #define R200_EMIT_PP_TXFILTER_0                     36 /* tex0/6 */
 108 #define R200_EMIT_PP_TXFILTER_1                     37 /* tex1/6 */
 109 #define R200_EMIT_PP_TXFILTER_2                     38 /* tex2/6 */
 110 #define R200_EMIT_PP_TXFILTER_3                     39 /* tex3/6 */
 111 #define R200_EMIT_PP_TXFILTER_4                     40 /* tex4/6 */
 112 #define R200_EMIT_PP_TXFILTER_5                     41 /* tex5/6 */
 113 #define R200_EMIT_PP_TXOFFSET_0                     42 /* tex0/1 */
 114 #define R200_EMIT_PP_TXOFFSET_1                     43 /* tex1/1 */
 115 #define R200_EMIT_PP_TXOFFSET_2                     44 /* tex2/1 */
 116 #define R200_EMIT_PP_TXOFFSET_3                     45 /* tex3/1 */
 117 #define R200_EMIT_PP_TXOFFSET_4                     46 /* tex4/1 */
 118 #define R200_EMIT_PP_TXOFFSET_5                     47 /* tex5/1 */
 119 #define R200_EMIT_VTE_CNTL                          48 /* vte/1 */
 120 #define R200_EMIT_OUTPUT_VTX_COMP_SEL               49 /* vtx/1 */
 121 #define R200_EMIT_PP_TAM_DEBUG3                     50 /* tam/1 */
 122 #define R200_EMIT_PP_CNTL_X                         51 /* cst/1 */
 123 #define R200_EMIT_RB3D_DEPTHXY_OFFSET               52 /* cst/1 */
 124 #define R200_EMIT_RE_AUX_SCISSOR_CNTL               53 /* cst/1 */
 125 #define R200_EMIT_RE_SCISSOR_TL_0                   54 /* cst/2 */
 126 #define R200_EMIT_RE_SCISSOR_TL_1                   55 /* cst/2 */
 127 #define R200_EMIT_RE_SCISSOR_TL_2                   56 /* cst/2 */
 128 #define R200_EMIT_SE_VAP_CNTL_STATUS                57 /* cst/1 */
 129 #define R200_EMIT_SE_VTX_STATE_CNTL                 58 /* cst/1 */
 130 #define R200_EMIT_RE_POINTSIZE                      59 /* cst/1 */
 131 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60 /* cst/4 */
 132 #define R200_EMIT_PP_CUBIC_FACES_0                  61
 133 #define R200_EMIT_PP_CUBIC_OFFSETS_0                62
 134 #define R200_EMIT_PP_CUBIC_FACES_1                  63
 135 #define R200_EMIT_PP_CUBIC_OFFSETS_1                64
 136 #define R200_EMIT_PP_CUBIC_FACES_2                  65
 137 #define R200_EMIT_PP_CUBIC_OFFSETS_2                66
 138 #define R200_EMIT_PP_CUBIC_FACES_3                  67
 139 #define R200_EMIT_PP_CUBIC_OFFSETS_3                68
 140 #define R200_EMIT_PP_CUBIC_FACES_4                  69
 141 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
 142 #define R200_EMIT_PP_CUBIC_FACES_5                  71
 143 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
 144 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
 145 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
 146 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
 147 #define R200_EMIT_RB3D_BLENDCOLOR                   76
 148 #define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
 149 #define RADEON_EMIT_PP_CUBIC_FACES_0                78
 150 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
 151 #define RADEON_EMIT_PP_CUBIC_FACES_1                80
 152 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
 153 #define RADEON_EMIT_PP_CUBIC_FACES_2                82
 154 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
 155 #define R200_EMIT_PP_TRI_PERF_CNTL                  84
 156 #define RADEON_MAX_STATE_PACKETS                    85
 157
 158 /* Commands understood by cmd_buffer ioctl.  More can be added but
 159  * obviously these can't be removed or changed:
 160  */
 161 #define RADEON_CMD_PACKET      1 /* emit one of the register packets above */
 162 #define RADEON_CMD_SCALARS     2 /* emit scalar data */
 163 #define RADEON_CMD_VECTORS     3 /* emit vector data */
 164 #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
 165 #define RADEON_CMD_PACKET3     5 /* emit hw packet */
 166 #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
 167 #define RADEON_CMD_SCALARS2     7 /* r200 stopgap */
 168 #define RADEON_CMD_WAIT         8 /* emit hw wait commands -- note:
 169                                    *  doesn't make the cpu wait, just
 170                                    *  the graphics hardware */
 171
 172
 173 typedef union {
 174         int i;
 175         struct {
 176                 unsigned char cmd_type, pad0, pad1, pad2;
 177         } header;
 178         struct {
 179                 unsigned char cmd_type, packet_id, pad0, pad1;
 180         } packet;
 181         struct {
 182                 unsigned char cmd_type, offset, stride, count;
 183         } scalars;
 184         struct {
 185                 unsigned char cmd_type, offset, stride, count;
 186         } vectors;
 187         struct {
 188                 unsigned char cmd_type, buf_idx, pad0, pad1;
 189         } dma;
 190         struct {
 191                 unsigned char cmd_type, flags, pad0, pad1;
 192         } wait;
 193 } drm_radeon_cmd_header_t;
 194
 195 #define RADEON_WAIT_2D  0x1
 196 #define RADEON_WAIT_3D  0x2
 197
 198
 199 #define RADEON_FRONT                    0x1
 200 #define RADEON_BACK                     0x2
 201 #define RADEON_DEPTH                    0x4
 202 #define RADEON_STENCIL                  0x8
 203 #define RADEON_CLEAR_FASTZ              0x80000000
 204 #define RADEON_USE_HIERZ                0x40000000
 205 #define RADEON_USE_COMP_ZBUF            0x20000000
 206
 207 /* Primitive types
 208  */
 209 #define RADEON_POINTS                   0x1
 210 #define RADEON_LINES                    0x2
 211 #define RADEON_LINE_STRIP               0x3
 212 #define RADEON_TRIANGLES                0x4
 213 #define RADEON_TRIANGLE_FAN             0x5
 214 #define RADEON_TRIANGLE_STRIP           0x6
 215
 216 /* Vertex/indirect buffer size
 217  */
 218 #define RADEON_BUFFER_SIZE              65536
 219
 220 /* Byte offsets for indirect buffer data
 221  */
 222 #define RADEON_INDEX_PRIM_OFFSET        20
 223
 224 #define RADEON_SCRATCH_REG_OFFSET       32
 225
 226 #define RADEON_NR_SAREA_CLIPRECTS       12
 227
 228 /* There are 2 heaps (local/GART).  Each region within a heap is a
 229  * minimum of 64k, and there are at most 64 of them per heap.
 230  */
 231 #define RADEON_LOCAL_TEX_HEAP           0
 232 #define RADEON_GART_TEX_HEAP            1
 233 #define RADEON_NR_TEX_HEAPS             2
 234 #define RADEON_NR_TEX_REGIONS           64
 235 #define RADEON_LOG_TEX_GRANULARITY      16
 236
 237 #define RADEON_MAX_TEXTURE_LEVELS       12
 238 #define RADEON_MAX_TEXTURE_UNITS        3
 239
 240 #define RADEON_MAX_SURFACES             8
 241
 242 /* Blits have strict offset rules.  All blit offset must be aligned on
 243  * a 1K-byte boundary.
 244  */
 245 #define RADEON_OFFSET_SHIFT             10
 246 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
 247 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
 248
 249 #endif /* __RADEON_SAREA_DEFINES__ */
 250
 251 typedef struct {
 252         unsigned int red;
 253         unsigned int green;
 254         unsigned int blue;
 255         unsigned int alpha;
 256 } radeon_color_regs_t;
 257
 258 typedef struct {
 259         /* Context state */
 260         unsigned int pp_misc;                           /* 0x1c14 */
 261         unsigned int pp_fog_color;
 262         unsigned int re_solid_color;
 263         unsigned int rb3d_blendcntl;
 264         unsigned int rb3d_depthoffset;
 265         unsigned int rb3d_depthpitch;
 266         unsigned int rb3d_zstencilcntl;
 267
 268         unsigned int pp_cntl;                           /* 0x1c38 */
 269         unsigned int rb3d_cntl;
 270         unsigned int rb3d_coloroffset;
 271         unsigned int re_width_height;
 272         unsigned int rb3d_colorpitch;
 273         unsigned int se_cntl;
 274
 275         /* Vertex format state */
 276         unsigned int se_coord_fmt;                      /* 0x1c50 */
 277
 278         /* Line state */
 279         unsigned int re_line_pattern;                   /* 0x1cd0 */
 280         unsigned int re_line_state;
 281
 282         unsigned int se_line_width;                     /* 0x1db8 */
 283
 284         /* Bumpmap state */
 285         unsigned int pp_lum_matrix;                     /* 0x1d00 */
 286
 287         unsigned int pp_rot_matrix_0;                   /* 0x1d58 */
 288         unsigned int pp_rot_matrix_1;
 289
 290         /* Mask state */
 291         unsigned int rb3d_stencilrefmask;               /* 0x1d7c */
 292         unsigned int rb3d_ropcntl;
 293         unsigned int rb3d_planemask;
 294
 295         /* Viewport state */
 296         unsigned int se_vport_xscale;                   /* 0x1d98 */
 297         unsigned int se_vport_xoffset;
 298         unsigned int se_vport_yscale;
 299         unsigned int se_vport_yoffset;
 300         unsigned int se_vport_zscale;
 301         unsigned int se_vport_zoffset;
 302
 303         /* Setup state */
 304         unsigned int se_cntl_status;                    /* 0x2140 */
 305
 306         /* Misc state */
 307         unsigned int re_top_left;                       /* 0x26c0 */
 308         unsigned int re_misc;
 309 } drm_radeon_context_regs_t;
 310
 311 typedef struct {
 312         /* Zbias state */
 313         unsigned int se_zbias_factor;                   /* 0x1dac */
 314         unsigned int se_zbias_constant;
 315 } drm_radeon_context2_regs_t;
 316
 317
 318 /* Setup registers for each texture unit
 319  */
 320 typedef struct {
 321         unsigned int pp_txfilter;
 322         unsigned int pp_txformat;
 323         unsigned int pp_txoffset;
 324         unsigned int pp_txcblend;
 325         unsigned int pp_txablend;
 326         unsigned int pp_tfactor;
 327         unsigned int pp_border_color;
 328 } drm_radeon_texture_regs_t;
 329
 330 typedef struct {
 331         unsigned int start;
 332         unsigned int finish;
 333         unsigned int prim:8;
 334         unsigned int stateidx:8;
 335         unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
 336         unsigned int vc_format;   /* vertex format */
 337 } drm_radeon_prim_t;
 338
 339
 340 typedef struct {
 341         drm_radeon_context_regs_t context;
 342         drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
 343         drm_radeon_context2_regs_t context2;
 344         unsigned int dirty;
 345 } drm_radeon_state_t;
 346
 347
 348 typedef struct {
 349         /* The channel for communication of state information to the
 350          * kernel on firing a vertex buffer with either of the
 351          * obsoleted vertex/index ioctls.
 352          */
 353         drm_radeon_context_regs_t context_state;
 354         drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
 355         unsigned int dirty;
 356         unsigned int vertsize;
 357         unsigned int vc_format;
 358
 359         /* The current cliprects, or a subset thereof.
 360          */
 361         drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
 362         unsigned int nbox;
 363
 364         /* Counters for client-side throttling of rendering clients.
 365          */
 366         unsigned int last_frame;
 367         unsigned int last_dispatch;
 368         unsigned int last_clear;
 369
 370         drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
 371         unsigned int tex_age[RADEON_NR_TEX_HEAPS];
 372         int ctx_owner;
 373         int pfState;                /* number of 3d windows (0,1,2ormore) */
 374         int pfCurrentPage;          /* which buffer is being displayed? */
 375         int crtc2_base;             /* CRTC2 frame offset */
 376         int tiling_enabled;     /* set by drm, read by 2d + 3d clients */
 377 } drm_radeon_sarea_t;
 378
 379
 380 /* WARNING: If you change any of these defines, make sure to change the
 381  * defines in the Xserver file (xf86drmRadeon.h)
 382  *
 383  * KW: actually it's illegal to change any of this (backwards compatibility).
 384  */
 385
 386 /* Radeon specific ioctls
 387  * The device specific ioctl range is 0x40 to 0x79.
 388  */
 389 #define DRM_RADEON_CP_INIT    0x00
 390 #define DRM_RADEON_CP_START   0x01
 391 #define DRM_RADEON_CP_STOP    0x02
 392 #define DRM_RADEON_CP_RESET   0x03
 393 #define DRM_RADEON_CP_IDLE    0x04
 394 #define DRM_RADEON_RESET      0x05
 395 #define DRM_RADEON_FULLSCREEN 0x06
 396 #define DRM_RADEON_SWAP       0x07
 397 #define DRM_RADEON_CLEAR      0x08
 398 #define DRM_RADEON_VERTEX     0x09
 399 #define DRM_RADEON_INDICES    0x0A
 400 #define DRM_RADEON_NOT_USED
 401 #define DRM_RADEON_STIPPLE    0x0C
 402 #define DRM_RADEON_INDIRECT   0x0D
 403 #define DRM_RADEON_TEXTURE    0x0E
 404 #define DRM_RADEON_VERTEX2    0x0F
 405 #define DRM_RADEON_CMDBUF     0x10
 406 #define DRM_RADEON_GETPARAM   0x11
 407 #define DRM_RADEON_FLIP       0x12
 408 #define DRM_RADEON_ALLOC      0x13
 409 #define DRM_RADEON_FREE       0x14
 410 #define DRM_RADEON_INIT_HEAP  0x15
 411 #define DRM_RADEON_IRQ_EMIT   0x16
 412 #define DRM_RADEON_IRQ_WAIT   0x17
 413 #define DRM_RADEON_CP_RESUME  0x18
 414 #define DRM_RADEON_SETPARAM   0x19
 415 #define DRM_RADEON_SURF_ALLOC 0x1a
 416 #define DRM_RADEON_SURF_FREE  0x1b
 417
 418 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 419 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
 420 #define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
 421 #define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
 422 #define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
 423 #define DRM_IOCTL_RADEON_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_RESET)
 424 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
 425 #define DRM_IOCTL_RADEON_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_SWAP)
 426 #define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
 427 #define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
 428 #define DRM_IOCTL_RADEON_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
 429 #define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
 430 #define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
 431 #define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
 432 #define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
 433 #define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
 434 #define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
 435 #define DRM_IOCTL_RADEON_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_FLIP)
 436 #define DRM_IOCTL_RADEON_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
 437 #define DRM_IOCTL_RADEON_FREE       DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
 438 #define DRM_IOCTL_RADEON_INIT_HEAP  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
 439 #define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
 440 #define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
 441 #define DRM_IOCTL_RADEON_CP_RESUME  DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
 442 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 443 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
 444 #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
 445
 446 typedef struct drm_radeon_init {
 447         enum {
 448                 RADEON_INIT_CP    = 0x01,
 449                 RADEON_CLEANUP_CP = 0x02,
 450                 RADEON_INIT_R200_CP = 0x03,
 451                 RADEON_INIT_R300_CP = 0x04
 452         } func;
 453         unsigned long sarea_priv_offset;
 454         int is_pci;
 455         int cp_mode;
 456         int gart_size;
 457         int ring_size;
 458         int usec_timeout;
 459
 460         unsigned int fb_bpp;
 461         unsigned int front_offset, front_pitch;
 462         unsigned int back_offset, back_pitch;
 463         unsigned int depth_bpp;
 464         unsigned int depth_offset, depth_pitch;
 465
 466         unsigned long fb_offset;
 467         unsigned long mmio_offset;
 468         unsigned long ring_offset;
 469         unsigned long ring_rptr_offset;
 470         unsigned long buffers_offset;
 471         unsigned long gart_textures_offset;
 472 } drm_radeon_init_t;
 473
 474 typedef struct drm_radeon_cp_stop {
 475         int flush;
 476         int idle;
 477 } drm_radeon_cp_stop_t;
 478
 479 typedef struct drm_radeon_fullscreen {
 480         enum {
 481                 RADEON_INIT_FULLSCREEN    = 0x01,
 482                 RADEON_CLEANUP_FULLSCREEN = 0x02
 483         } func;
 484 } drm_radeon_fullscreen_t;
 485
 486 #define CLEAR_X1        0
 487 #define CLEAR_Y1        1
 488 #define CLEAR_X2        2
 489 #define CLEAR_Y2        3
 490 #define CLEAR_DEPTH     4
 491
 492 typedef union drm_radeon_clear_rect {
 493         float f[5];
 494         unsigned int ui[5];
 495 } drm_radeon_clear_rect_t;
 496
 497 typedef struct drm_radeon_clear {
 498         unsigned int flags;
 499         unsigned int clear_color;
 500         unsigned int clear_depth;
 501         unsigned int color_mask;
 502         unsigned int depth_mask;   /* misnamed field:  should be stencil */
 503         drm_radeon_clear_rect_t __user *depth_boxes;
 504 } drm_radeon_clear_t;
 505
 506 typedef struct drm_radeon_vertex {
 507         int prim;
 508         int idx;                        /* Index of vertex buffer */
 509         int count;                      /* Number of vertices in buffer */
 510         int discard;                    /* Client finished with buffer? */
 511 } drm_radeon_vertex_t;
 512
 513 typedef struct drm_radeon_indices {
 514         int prim;
 515         int idx;
 516         int start;
 517         int end;
 518         int discard;                    /* Client finished with buffer? */
 519 } drm_radeon_indices_t;
 520
 521 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
 522  *      - allows multiple primitives and state changes in a single ioctl
 523  *      - supports driver change to emit native primitives
 524  */
 525 typedef struct drm_radeon_vertex2 {
 526         int idx;                        /* Index of vertex buffer */
 527         int discard;                    /* Client finished with buffer? */
 528         int nr_states;
 529         drm_radeon_state_t __user *state;
 530         int nr_prims;
 531         drm_radeon_prim_t __user *prim;
 532 } drm_radeon_vertex2_t;
 533
 534 /* v1.3 - obsoletes drm_radeon_vertex2
 535  *      - allows arbitarily large cliprect list
 536  *      - allows updating of tcl packet, vector and scalar state
 537  *      - allows memory-efficient description of state updates
 538  *      - allows state to be emitted without a primitive
 539  *           (for clears, ctx switches)
 540  *      - allows more than one dma buffer to be referenced per ioctl
 541  *      - supports tcl driver
 542  *      - may be extended in future versions with new cmd types, packets
 543  */
 544 typedef struct drm_radeon_cmd_buffer {
 545         int bufsz;
 546         char __user *buf;
 547         int nbox;
 548         drm_clip_rect_t __user *boxes;
 549 } drm_radeon_cmd_buffer_t;
 550
 551 typedef struct drm_radeon_tex_image {
 552         unsigned int x, y;              /* Blit coordinates */
 553         unsigned int width, height;
 554         const void __user *data;
 555 } drm_radeon_tex_image_t;
 556
 557 typedef struct drm_radeon_texture {
 558         unsigned int offset;
 559         int pitch;
 560         int format;
 561         int width;                      /* Texture image coordinates */
 562         int height;
 563         drm_radeon_tex_image_t __user *image;
 564 } drm_radeon_texture_t;
 565
 566 typedef struct drm_radeon_stipple {
 567         unsigned int __user *mask;
 568 } drm_radeon_stipple_t;
 569
 570 typedef struct drm_radeon_indirect {
 571         int idx;
 572         int start;
 573         int end;
 574         int discard;
 575 } drm_radeon_indirect_t;
 576
 577
 578 /* 1.3: An ioctl to get parameters that aren't available to the 3d
 579  * client any other way.
 580  */
 581 #define RADEON_PARAM_GART_BUFFER_OFFSET    1 /* card offset of 1st GART buffer */
 582 #define RADEON_PARAM_LAST_FRAME            2
 583 #define RADEON_PARAM_LAST_DISPATCH         3
 584 #define RADEON_PARAM_LAST_CLEAR            4
 585 /* Added with DRM version 1.6. */
 586 #define RADEON_PARAM_IRQ_NR                5
 587 #define RADEON_PARAM_GART_BASE             6 /* card offset of GART base */
 588 /* Added with DRM version 1.8. */
 589 #define RADEON_PARAM_REGISTER_HANDLE       7 /* for drmMap() */
 590 #define RADEON_PARAM_STATUS_HANDLE         8
 591 #define RADEON_PARAM_SAREA_HANDLE          9
 592 #define RADEON_PARAM_GART_TEX_HANDLE       10
 593 #define RADEON_PARAM_SCRATCH_OFFSET        11
 594
 595 typedef struct drm_radeon_getparam {
 596         int param;
 597         void __user *value;
 598 } drm_radeon_getparam_t;
 599
 600 /* 1.6: Set up a memory manager for regions of shared memory:
 601  */
 602 #define RADEON_MEM_REGION_GART 1
 603 #define RADEON_MEM_REGION_FB   2
 604
 605 typedef struct drm_radeon_mem_alloc {
 606         int region;
 607         int alignment;
 608         int size;
 609         int __user *region_offset;      /* offset from start of fb or GART */
 610 } drm_radeon_mem_alloc_t;
 611
 612 typedef struct drm_radeon_mem_free {
 613         int region;
 614         int region_offset;
 615 } drm_radeon_mem_free_t;
 616
 617 typedef struct drm_radeon_mem_init_heap {
 618         int region;
 619         int size;
 620         int start;
 621 } drm_radeon_mem_init_heap_t;
 622
 623
 624 /* 1.6: Userspace can request & wait on irq's:
 625  */
 626 typedef struct drm_radeon_irq_emit {
 627         int __user *irq_seq;
 628 } drm_radeon_irq_emit_t;
 629
 630 typedef struct drm_radeon_irq_wait {
 631         int irq_seq;
 632 } drm_radeon_irq_wait_t;
 633
 634
 635 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
 636  * the card's address space, via a new generic ioctl to set parameters
 637  */
 638
 639 typedef struct drm_radeon_setparam {
 640         unsigned int param;
 641         int64_t      value;
 642 } drm_radeon_setparam_t;
 643
 644 #define RADEON_SETPARAM_FB_LOCATION    1        /* determined framebuffer location */
 645 #define RADEON_SETPARAM_SWITCH_TILING  2        /* enable/disable color tiling */
 646
 647 /* 1.14: Clients can allocate/free a surface
 648  */
 649 typedef struct drm_radeon_surface_alloc {
 650         unsigned int address;
 651         unsigned int size;
 652         unsigned int flags;
 653 } drm_radeon_surface_alloc_t;
 654
 655 typedef struct drm_radeon_surface_free {
 656         unsigned int address;
 657 } drm_radeon_surface_free_t;
 658
 659 #endif