[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / char / ip2 / i2ellis.c
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1 /*******************************************************************************
3 * (c) 1998 by Computone Corporation
5 ********************************************************************************
8 * PACKAGE: Linux tty Device Driver for IntelliPort family of multiport
9 * serial I/O controllers.
11 * DESCRIPTION: Low-level interface code for the device driver
12 * (This is included source code, not a separate compilation
13 * module.)
15 *******************************************************************************/
16 //---------------------------------------------
17 // Function declarations private to this module
18 //---------------------------------------------
19 // Functions called only indirectly through i2eBordStr entries.
21 static int iiWriteBuf16(i2eBordStrPtr, unsigned char *, int);
22 static int iiWriteBuf8(i2eBordStrPtr, unsigned char *, int);
23 static int iiReadBuf16(i2eBordStrPtr, unsigned char *, int);
24 static int iiReadBuf8(i2eBordStrPtr, unsigned char *, int);
26 static unsigned short iiReadWord16(i2eBordStrPtr);
27 static unsigned short iiReadWord8(i2eBordStrPtr);
28 static void iiWriteWord16(i2eBordStrPtr, unsigned short);
29 static void iiWriteWord8(i2eBordStrPtr, unsigned short);
31 static int iiWaitForTxEmptyII(i2eBordStrPtr, int);
32 static int iiWaitForTxEmptyIIEX(i2eBordStrPtr, int);
33 static int iiTxMailEmptyII(i2eBordStrPtr);
34 static int iiTxMailEmptyIIEX(i2eBordStrPtr);
35 static int iiTrySendMailII(i2eBordStrPtr, unsigned char);
36 static int iiTrySendMailIIEX(i2eBordStrPtr, unsigned char);
38 static unsigned short iiGetMailII(i2eBordStrPtr);
39 static unsigned short iiGetMailIIEX(i2eBordStrPtr);
41 static void iiEnableMailIrqII(i2eBordStrPtr);
42 static void iiEnableMailIrqIIEX(i2eBordStrPtr);
43 static void iiWriteMaskII(i2eBordStrPtr, unsigned char);
44 static void iiWriteMaskIIEX(i2eBordStrPtr, unsigned char);
46 static void ii2DelayTimer(unsigned int);
47 static void ii2DelayWakeup(unsigned long id);
48 static void ii2Nop(void);
50 //***************
51 //* Static Data *
52 //***************
54 static int ii2Safe; // Safe I/O address for delay routine
56 static int iiDelayed; // Set when the iiResetDelay function is
57 // called. Cleared when ANY board is reset.
58 static struct timer_list * pDelayTimer; // Used by iiDelayTimer
59 static wait_queue_head_t pDelayWait; // Used by iiDelayTimer
60 static rwlock_t Dl_spinlock;
62 //********
63 //* Code *
64 //********
66 //=======================================================
67 // Initialization Routines
69 // iiSetAddress
70 // iiReset
71 // iiResetDelay
72 // iiInitialize
73 //=======================================================
75 //******************************************************************************
76 // Function: iiEllisInit()
77 // Parameters: None
79 // Returns: Nothing
81 // Description:
83 // This routine performs any required initialization of the iiEllis subsystem.
85 //******************************************************************************
86 static void
87 iiEllisInit(void)
89 pDelayTimer = kmalloc ( sizeof (struct timer_list), GFP_KERNEL );
90 init_timer(pDelayTimer);
91 init_waitqueue_head(&pDelayWait);
92 LOCK_INIT(&Dl_spinlock);
95 //******************************************************************************
96 // Function: iiEllisCleanup()
97 // Parameters: None
99 // Returns: Nothing
101 // Description:
103 // This routine performs any required cleanup of the iiEllis subsystem.
105 //******************************************************************************
106 static void
107 iiEllisCleanup(void)
109 if ( pDelayTimer != NULL ) {
110 kfree ( pDelayTimer );
114 //******************************************************************************
115 // Function: iiSetAddress(pB, address, delay)
116 // Parameters: pB - pointer to the board structure
117 // address - the purported I/O address of the board
118 // delay - pointer to the 1-ms delay function to use
119 // in this and any future operations to this board
121 // Returns: True if everything appears copacetic.
122 // False if there is any error: the pB->i2eError field has the error
124 // Description:
126 // This routine (roughly) checks for address validity, sets the i2eValid OK and
127 // sets the state to II_STATE_COLD which means that we haven't even sent a reset
128 // yet.
130 //******************************************************************************
131 static int
132 iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay )
134 // Should any failure occur before init is finished...
135 pB->i2eValid = I2E_INCOMPLETE;
137 // Cannot check upper limit except extremely: Might be microchannel
138 // Address must be on an 8-byte boundary
140 if ((unsigned int)address <= 0x100
141 || (unsigned int)address >= 0xfff8
142 || (address & 0x7)
145 COMPLETE(pB,I2EE_BADADDR);
148 // Initialize accelerators
149 pB->i2eBase = address;
150 pB->i2eData = address + FIFO_DATA;
151 pB->i2eStatus = address + FIFO_STATUS;
152 pB->i2ePointer = address + FIFO_PTR;
153 pB->i2eXMail = address + FIFO_MAIL;
154 pB->i2eXMask = address + FIFO_MASK;
156 // Initialize i/o address for ii2DelayIO
157 ii2Safe = address + FIFO_NOP;
159 // Initialize the delay routine
160 pB->i2eDelay = ((delay != (delayFunc_t)NULL) ? delay : (delayFunc_t)ii2Nop);
162 pB->i2eValid = I2E_MAGIC;
163 pB->i2eState = II_STATE_COLD;
165 COMPLETE(pB, I2EE_GOOD);
168 //******************************************************************************
169 // Function: iiReset(pB)
170 // Parameters: pB - pointer to the board structure
172 // Returns: True if everything appears copacetic.
173 // False if there is any error: the pB->i2eError field has the error
175 // Description:
177 // Attempts to reset the board (see also i2hw.h). Normally, we would use this to
178 // reset a board immediately after iiSetAddress(), but it is valid to reset a
179 // board from any state, say, in order to change or re-load loadware. (Under
180 // such circumstances, no reason to re-run iiSetAddress(), which is why it is a
181 // separate routine and not included in this routine.
183 //******************************************************************************
184 static int
185 iiReset(i2eBordStrPtr pB)
187 // Magic number should be set, else even the address is suspect
188 if (pB->i2eValid != I2E_MAGIC)
190 COMPLETE(pB, I2EE_BADMAGIC);
193 OUTB(pB->i2eBase + FIFO_RESET, 0); // Any data will do
194 iiDelay(pB, 50); // Pause between resets
195 OUTB(pB->i2eBase + FIFO_RESET, 0); // Second reset
197 // We must wait before even attempting to read anything from the FIFO: the
198 // board's P.O.S.T may actually attempt to read and write its end of the
199 // FIFO in order to check flags, loop back (where supported), etc. On
200 // completion of this testing it would reset the FIFO, and on completion
201 // of all // P.O.S.T., write the message. We must not mistake data which
202 // might have been sent for testing as part of the reset message. To
203 // better utilize time, say, when resetting several boards, we allow the
204 // delay to be performed externally; in this way the caller can reset
205 // several boards, delay a single time, then call the initialization
206 // routine for all.
208 pB->i2eState = II_STATE_RESET;
210 iiDelayed = 0; // i.e., the delay routine hasn't been called since the most
211 // recent reset.
213 // Ensure anything which would have been of use to standard loadware is
214 // blanked out, since board has now forgotten everything!.
216 pB->i2eUsingIrq = IRQ_UNDEFINED; // Not set up to use an interrupt yet
217 pB->i2eWaitingForEmptyFifo = 0;
218 pB->i2eOutMailWaiting = 0;
219 pB->i2eChannelPtr = NULL;
220 pB->i2eChannelCnt = 0;
222 pB->i2eLeadoffWord[0] = 0;
223 pB->i2eFifoInInts = 0;
224 pB->i2eFifoOutInts = 0;
225 pB->i2eFatalTrap = NULL;
226 pB->i2eFatal = 0;
228 COMPLETE(pB, I2EE_GOOD);
231 //******************************************************************************
232 // Function: iiResetDelay(pB)
233 // Parameters: pB - pointer to the board structure
235 // Returns: True if everything appears copacetic.
236 // False if there is any error: the pB->i2eError field has the error
238 // Description:
240 // Using the delay defined in board structure, waits two seconds (for board to
241 // reset).
243 //******************************************************************************
244 static int
245 iiResetDelay(i2eBordStrPtr pB)
247 if (pB->i2eValid != I2E_MAGIC) {
248 COMPLETE(pB, I2EE_BADMAGIC);
250 if (pB->i2eState != II_STATE_RESET) {
251 COMPLETE(pB, I2EE_BADSTATE);
253 iiDelay(pB,2000); /* Now we wait for two seconds. */
254 iiDelayed = 1; /* Delay has been called: ok to initialize */
255 COMPLETE(pB, I2EE_GOOD);
258 //******************************************************************************
259 // Function: iiInitialize(pB)
260 // Parameters: pB - pointer to the board structure
262 // Returns: True if everything appears copacetic.
263 // False if there is any error: the pB->i2eError field has the error
265 // Description:
267 // Attempts to read the Power-on reset message. Initializes any remaining fields
268 // in the pB structure.
270 // This should be called as the third step of a process beginning with
271 // iiReset(), then iiResetDelay(). This routine checks to see that the structure
272 // is "valid" and in the reset state, also confirms that the delay routine has
273 // been called since the latest reset (to any board! overly strong!).
275 //******************************************************************************
276 static int
277 iiInitialize(i2eBordStrPtr pB)
279 int itemp;
280 unsigned char c;
281 unsigned short utemp;
282 unsigned int ilimit;
284 if (pB->i2eValid != I2E_MAGIC)
286 COMPLETE(pB, I2EE_BADMAGIC);
289 if (pB->i2eState != II_STATE_RESET || !iiDelayed)
291 COMPLETE(pB, I2EE_BADSTATE);
294 // In case there is a failure short of our completely reading the power-up
295 // message.
296 pB->i2eValid = I2E_INCOMPLETE;
299 // Now attempt to read the message.
301 for (itemp = 0; itemp < sizeof(porStr); itemp++)
303 // We expect the entire message is ready.
304 if (HAS_NO_INPUT(pB))
306 pB->i2ePomSize = itemp;
307 COMPLETE(pB, I2EE_PORM_SHORT);
310 pB->i2ePom.c[itemp] = c = BYTE_FROM(pB);
312 // We check the magic numbers as soon as they are supposed to be read
313 // (rather than after) to minimize effect of reading something we
314 // already suspect can't be "us".
315 if ( (itemp == POR_1_INDEX && c != POR_MAGIC_1) ||
316 (itemp == POR_2_INDEX && c != POR_MAGIC_2))
318 pB->i2ePomSize = itemp+1;
319 COMPLETE(pB, I2EE_BADMAGIC);
323 pB->i2ePomSize = itemp;
325 // Ensure that this was all the data...
326 if (HAS_INPUT(pB))
327 COMPLETE(pB, I2EE_PORM_LONG);
329 // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper:
330 // Implying we will not be able to download any code either: That's ok: the
331 // condition is pretty explicit.
332 if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER)
334 COMPLETE(pB, I2EE_POSTERR);
337 // Determine anything which must be done differently depending on the family
338 // of boards!
339 switch (pB->i2ePom.e.porID & POR_ID_FAMILY)
341 case POR_ID_FII: // IntelliPort-II
343 pB->i2eFifoStyle = FIFO_II;
344 pB->i2eFifoSize = 512; // 512 bytes, always
345 pB->i2eDataWidth16 = NO;
347 pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit
348 // slot, we do allow it to be done (documentation!)
350 pB->i2eGoodMap[1] =
351 pB->i2eGoodMap[2] =
352 pB->i2eGoodMap[3] =
353 pB->i2eChannelMap[1] =
354 pB->i2eChannelMap[2] =
355 pB->i2eChannelMap[3] = 0;
357 switch (pB->i2ePom.e.porID & POR_ID_SIZE)
359 case POR_ID_II_4:
360 pB->i2eGoodMap[0] =
361 pB->i2eChannelMap[0] = 0x0f; // four-port
363 // Since porPorts1 is based on the Hardware ID register, the numbers
364 // should always be consistent for IntelliPort-II. Ditto below...
365 if (pB->i2ePom.e.porPorts1 != 4)
367 COMPLETE(pB, I2EE_INCONSIST);
369 break;
371 case POR_ID_II_8:
372 case POR_ID_II_8R:
373 pB->i2eGoodMap[0] =
374 pB->i2eChannelMap[0] = 0xff; // Eight port
375 if (pB->i2ePom.e.porPorts1 != 8)
377 COMPLETE(pB, I2EE_INCONSIST);
379 break;
381 case POR_ID_II_6:
382 pB->i2eGoodMap[0] =
383 pB->i2eChannelMap[0] = 0x3f; // Six Port
384 if (pB->i2ePom.e.porPorts1 != 6)
386 COMPLETE(pB, I2EE_INCONSIST);
388 break;
391 // Fix up the "good channel list based on any errors reported.
392 if (pB->i2ePom.e.porDiag1 & POR_BAD_UART1)
394 pB->i2eGoodMap[0] &= ~0x0f;
397 if (pB->i2ePom.e.porDiag1 & POR_BAD_UART2)
399 pB->i2eGoodMap[0] &= ~0xf0;
402 break; // POR_ID_FII case
404 case POR_ID_FIIEX: // IntelliPort-IIEX
406 pB->i2eFifoStyle = FIFO_IIEX;
408 itemp = pB->i2ePom.e.porFifoSize;
410 // Implicit assumption that fifo would not grow beyond 32k,
411 // nor would ever be less than 256.
413 if (itemp < 8 || itemp > 15)
415 COMPLETE(pB, I2EE_INCONSIST);
417 pB->i2eFifoSize = (1 << itemp);
419 // These are based on what P.O.S.T thinks should be there, based on
420 // box ID registers
421 ilimit = pB->i2ePom.e.porNumBoxes;
422 if (ilimit > ABS_MAX_BOXES)
424 ilimit = ABS_MAX_BOXES;
427 // For as many boxes as EXIST, gives the type of box.
428 // Added 8/6/93: check for the ISA-4 (asic) which looks like an
429 // expandable but for whom "8 or 16?" is not the right question.
431 utemp = pB->i2ePom.e.porFlags;
432 if (utemp & POR_CEX4)
434 pB->i2eChannelMap[0] = 0x000f;
435 } else {
436 utemp &= POR_BOXES;
437 for (itemp = 0; itemp < ilimit; itemp++)
439 pB->i2eChannelMap[itemp] =
440 ((utemp & POR_BOX_16) ? 0xffff : 0x00ff);
441 utemp >>= 1;
445 // These are based on what P.O.S.T actually found.
447 utemp = (pB->i2ePom.e.porPorts2 << 8) + pB->i2ePom.e.porPorts1;
449 for (itemp = 0; itemp < ilimit; itemp++)
451 pB->i2eGoodMap[itemp] = 0;
452 if (utemp & 1) pB->i2eGoodMap[itemp] |= 0x000f;
453 if (utemp & 2) pB->i2eGoodMap[itemp] |= 0x00f0;
454 if (utemp & 4) pB->i2eGoodMap[itemp] |= 0x0f00;
455 if (utemp & 8) pB->i2eGoodMap[itemp] |= 0xf000;
456 utemp >>= 4;
459 // Now determine whether we should transfer in 8 or 16-bit mode.
460 switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) )
462 case POR_BUS_SLOT16 | POR_BUS_DIP16:
463 pB->i2eDataWidth16 = YES;
464 pB->i2eMaxIrq = 15;
465 break;
467 case POR_BUS_SLOT16:
468 pB->i2eDataWidth16 = NO;
469 pB->i2eMaxIrq = 15;
470 break;
472 case 0:
473 case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care.
474 default:
475 pB->i2eDataWidth16 = NO;
476 pB->i2eMaxIrq = 7;
477 break;
479 break; // POR_ID_FIIEX case
481 default: // Unknown type of board
482 COMPLETE(pB, I2EE_BAD_FAMILY);
483 break;
484 } // End the switch based on family
486 // Temporarily, claim there is no room in the outbound fifo.
487 // We will maintain this whenever we check for an empty outbound FIFO.
488 pB->i2eFifoRemains = 0;
490 // Now, based on the bus type, should we expect to be able to re-configure
491 // interrupts (say, for testing purposes).
492 switch (pB->i2ePom.e.porBus & POR_BUS_TYPE)
494 case POR_BUS_T_ISA:
495 case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok.
496 pB->i2eChangeIrq = YES;
497 break;
498 case POR_BUS_T_MCA:
499 case POR_BUS_T_EISA:
500 pB->i2eChangeIrq = NO;
501 break;
502 default:
503 COMPLETE(pB, I2EE_BADBUS);
506 if (pB->i2eDataWidth16 == YES)
508 pB->i2eWriteBuf = iiWriteBuf16;
509 pB->i2eReadBuf = iiReadBuf16;
510 pB->i2eWriteWord = iiWriteWord16;
511 pB->i2eReadWord = iiReadWord16;
512 } else {
513 pB->i2eWriteBuf = iiWriteBuf8;
514 pB->i2eReadBuf = iiReadBuf8;
515 pB->i2eWriteWord = iiWriteWord8;
516 pB->i2eReadWord = iiReadWord8;
519 switch(pB->i2eFifoStyle)
521 case FIFO_II:
522 pB->i2eWaitForTxEmpty = iiWaitForTxEmptyII;
523 pB->i2eTxMailEmpty = iiTxMailEmptyII;
524 pB->i2eTrySendMail = iiTrySendMailII;
525 pB->i2eGetMail = iiGetMailII;
526 pB->i2eEnableMailIrq = iiEnableMailIrqII;
527 pB->i2eWriteMask = iiWriteMaskII;
529 break;
531 case FIFO_IIEX:
532 pB->i2eWaitForTxEmpty = iiWaitForTxEmptyIIEX;
533 pB->i2eTxMailEmpty = iiTxMailEmptyIIEX;
534 pB->i2eTrySendMail = iiTrySendMailIIEX;
535 pB->i2eGetMail = iiGetMailIIEX;
536 pB->i2eEnableMailIrq = iiEnableMailIrqIIEX;
537 pB->i2eWriteMask = iiWriteMaskIIEX;
539 break;
541 default:
542 COMPLETE(pB, I2EE_INCONSIST);
545 // Initialize state information.
546 pB->i2eState = II_STATE_READY; // Ready to load loadware.
548 // Some Final cleanup:
549 // For some boards, the bootstrap firmware may perform some sort of test
550 // resulting in a stray character pending in the incoming mailbox. If one is
551 // there, it should be read and discarded, especially since for the standard
552 // firmware, it's the mailbox that interrupts the host.
554 pB->i2eStartMail = iiGetMail(pB);
556 // Throw it away and clear the mailbox structure element
557 pB->i2eStartMail = NO_MAIL_HERE;
559 // Everything is ok now, return with good status/
561 pB->i2eValid = I2E_MAGIC;
562 COMPLETE(pB, I2EE_GOOD);
565 //=======================================================
566 // Delay Routines
568 // iiDelayIO
569 // iiNop
570 //=======================================================
572 static void
573 ii2DelayWakeup(unsigned long id)
575 wake_up_interruptible ( &pDelayWait );
578 //******************************************************************************
579 // Function: ii2DelayTimer(mseconds)
580 // Parameters: mseconds - number of milliseconds to delay
582 // Returns: Nothing
584 // Description:
586 // This routine delays for approximately mseconds milliseconds and is intended
587 // to be called indirectly through i2Delay field in i2eBordStr. It uses the
588 // Linux timer_list mechanism.
590 // The Linux timers use a unit called "jiffies" which are 10mS in the Intel
591 // architecture. This function rounds the delay period up to the next "jiffy".
592 // In the Alpha architecture the "jiffy" is 1mS, but this driver is not intended
593 // for Alpha platforms at this time.
595 //******************************************************************************
596 static void
597 ii2DelayTimer(unsigned int mseconds)
599 wait_queue_t wait;
601 init_waitqueue_entry(&wait, current);
603 init_timer ( pDelayTimer );
605 add_wait_queue(&pDelayWait, &wait);
607 set_current_state( TASK_INTERRUPTIBLE );
609 pDelayTimer->expires = jiffies + ( mseconds + 9 ) / 10;
610 pDelayTimer->function = ii2DelayWakeup;
611 pDelayTimer->data = 0;
613 add_timer ( pDelayTimer );
615 schedule();
617 set_current_state( TASK_RUNNING );
618 remove_wait_queue(&pDelayWait, &wait);
620 del_timer ( pDelayTimer );
623 #if 0
624 //static void ii2DelayIO(unsigned int);
625 //******************************************************************************
626 // !!! Not Used, this is DOS crap, some of you young folks may be interested in
627 // in how things were done in the stone age of caculating machines !!!
628 // Function: ii2DelayIO(mseconds)
629 // Parameters: mseconds - number of milliseconds to delay
631 // Returns: Nothing
633 // Description:
635 // This routine delays for approximately mseconds milliseconds and is intended
636 // to be called indirectly through i2Delay field in i2eBordStr. It is intended
637 // for use where a clock-based function is impossible: for example, DOS drivers.
639 // This function uses the IN instruction to place bounds on the timing and
640 // assumes that ii2Safe has been set. This is because I/O instructions are not
641 // subject to caching and will therefore take a certain minimum time. To ensure
642 // the delay is at least long enough on fast machines, it is based on some
643 // fastest-case calculations. On slower machines this may cause VERY long
644 // delays. (3 x fastest case). In the fastest case, everything is cached except
645 // the I/O instruction itself.
647 // Timing calculations:
648 // The fastest bus speed for I/O operations is likely to be 10 MHz. The I/O
649 // operation in question is a byte operation to an odd address. For 8-bit
650 // operations, the architecture generally enforces two wait states. At 10 MHz, a
651 // single cycle time is 100nS. A read operation at two wait states takes 6
652 // cycles for a total time of 600nS. Therefore approximately 1666 iterations
653 // would be required to generate a single millisecond delay. The worst
654 // (reasonable) case would be an 8MHz system with no cacheing. In this case, the
655 // I/O instruction would take 125nS x 6 cyles = 750 nS. More importantly, code
656 // fetch of other instructions in the loop would take time (zero wait states,
657 // however) and would be hard to estimate. This is minimized by using in-line
658 // assembler for the in inner loop of IN instructions. This consists of just a
659 // few bytes. So we'll guess about four code fetches per loop. Each code fetch
660 // should take four cycles, so we have 125nS * 8 = 1000nS. Worst case then is
661 // that what should have taken 1 mS takes instead 1666 * (1750) = 2.9 mS.
663 // So much for theoretical timings: results using 1666 value on some actual
664 // machines:
665 // IBM 286 6MHz 3.15 mS
666 // Zenith 386 33MHz 2.45 mS
667 // (brandX) 386 33MHz 1.90 mS (has cache)
668 // (brandY) 486 33MHz 2.35 mS
669 // NCR 486 ?? 1.65 mS (microchannel)
671 // For most machines, it is probably safe to scale this number back (remember,
672 // for robust operation use an actual timed delay if possible), so we are using
673 // a value of 1190. This yields 1.17 mS for the fastest machine in our sample,
674 // 1.75 mS for typical 386 machines, and 2.25 mS the absolute slowest machine.
676 // 1/29/93:
677 // The above timings are too slow. Actual cycle times might be faster. ISA cycle
678 // times could approach 500 nS, and ...
679 // The IBM model 77 being microchannel has no wait states for 8-bit reads and
680 // seems to be accessing the I/O at 440 nS per access (from start of one to
681 // start of next). This would imply we need 1000/.440 = 2272 iterations to
682 // guarantee we are fast enough. In actual testing, we see that 2 * 1190 are in
683 // fact enough. For diagnostics, we keep the level at 1190, but developers note
684 // this needs tuning.
686 // Safe assumption: 2270 i/o reads = 1 millisecond
688 //******************************************************************************
691 static int ii2DelValue = 1190; // See timing calculations below
692 // 1666 for fastest theoretical machine
693 // 1190 safe for most fast 386 machines
694 // 1000 for fastest machine tested here
695 // 540 (sic) for AT286/6Mhz
696 static void
697 ii2DelayIO(unsigned int mseconds)
699 if (!ii2Safe)
700 return; /* Do nothing if this variable uninitialized */
702 while(mseconds--) {
703 int i = ii2DelValue;
704 while ( i-- ) {
705 INB ( ii2Safe );
709 #endif
711 //******************************************************************************
712 // Function: ii2Nop()
713 // Parameters: None
715 // Returns: Nothing
717 // Description:
719 // iiInitialize will set i2eDelay to this if the delay parameter is NULL. This
720 // saves checking for a NULL pointer at every call.
721 //******************************************************************************
722 static void
723 ii2Nop(void)
725 return; // no mystery here
728 //=======================================================
729 // Routines which are available in 8/16-bit versions, or
730 // in different fifo styles. These are ALL called
731 // indirectly through the board structure.
732 //=======================================================
734 //******************************************************************************
735 // Function: iiWriteBuf16(pB, address, count)
736 // Parameters: pB - pointer to board structure
737 // address - address of data to write
738 // count - number of data bytes to write
740 // Returns: True if everything appears copacetic.
741 // False if there is any error: the pB->i2eError field has the error
743 // Description:
745 // Writes 'count' bytes from 'address' to the data fifo specified by the board
746 // structure pointer pB. Should count happen to be odd, an extra pad byte is
747 // sent (identity unknown...). Uses 16-bit (word) operations. Is called
748 // indirectly through pB->i2eWriteBuf.
750 //******************************************************************************
751 static int
752 iiWriteBuf16(i2eBordStrPtr pB, unsigned char *address, int count)
754 // Rudimentary sanity checking here.
755 if (pB->i2eValid != I2E_MAGIC)
756 COMPLETE(pB, I2EE_INVALID);
758 OUTSW ( pB->i2eData, address, count);
760 COMPLETE(pB, I2EE_GOOD);
763 //******************************************************************************
764 // Function: iiWriteBuf8(pB, address, count)
765 // Parameters: pB - pointer to board structure
766 // address - address of data to write
767 // count - number of data bytes to write
769 // Returns: True if everything appears copacetic.
770 // False if there is any error: the pB->i2eError field has the error
772 // Description:
774 // Writes 'count' bytes from 'address' to the data fifo specified by the board
775 // structure pointer pB. Should count happen to be odd, an extra pad byte is
776 // sent (identity unknown...). This is to be consistent with the 16-bit version.
777 // Uses 8-bit (byte) operations. Is called indirectly through pB->i2eWriteBuf.
779 //******************************************************************************
780 static int
781 iiWriteBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
783 /* Rudimentary sanity checking here */
784 if (pB->i2eValid != I2E_MAGIC)
785 COMPLETE(pB, I2EE_INVALID);
787 OUTSB ( pB->i2eData, address, count );
789 COMPLETE(pB, I2EE_GOOD);
792 //******************************************************************************
793 // Function: iiReadBuf16(pB, address, count)
794 // Parameters: pB - pointer to board structure
795 // address - address to put data read
796 // count - number of data bytes to read
798 // Returns: True if everything appears copacetic.
799 // False if there is any error: the pB->i2eError field has the error
801 // Description:
803 // Reads 'count' bytes into 'address' from the data fifo specified by the board
804 // structure pointer pB. Should count happen to be odd, an extra pad byte is
805 // received (identity unknown...). Uses 16-bit (word) operations. Is called
806 // indirectly through pB->i2eReadBuf.
808 //******************************************************************************
809 static int
810 iiReadBuf16(i2eBordStrPtr pB, unsigned char *address, int count)
812 // Rudimentary sanity checking here.
813 if (pB->i2eValid != I2E_MAGIC)
814 COMPLETE(pB, I2EE_INVALID);
816 INSW ( pB->i2eData, address, count);
818 COMPLETE(pB, I2EE_GOOD);
821 //******************************************************************************
822 // Function: iiReadBuf8(pB, address, count)
823 // Parameters: pB - pointer to board structure
824 // address - address to put data read
825 // count - number of data bytes to read
827 // Returns: True if everything appears copacetic.
828 // False if there is any error: the pB->i2eError field has the error
830 // Description:
832 // Reads 'count' bytes into 'address' from the data fifo specified by the board
833 // structure pointer pB. Should count happen to be odd, an extra pad byte is
834 // received (identity unknown...). This to match the 16-bit behaviour. Uses
835 // 8-bit (byte) operations. Is called indirectly through pB->i2eReadBuf.
837 //******************************************************************************
838 static int
839 iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
841 // Rudimentary sanity checking here.
842 if (pB->i2eValid != I2E_MAGIC)
843 COMPLETE(pB, I2EE_INVALID);
845 INSB ( pB->i2eData, address, count);
847 COMPLETE(pB, I2EE_GOOD);
850 //******************************************************************************
851 // Function: iiReadWord16(pB)
852 // Parameters: pB - pointer to board structure
854 // Returns: True if everything appears copacetic.
855 // False if there is any error: the pB->i2eError field has the error
857 // Description:
859 // Returns the word read from the data fifo specified by the board-structure
860 // pointer pB. Uses a 16-bit operation. Is called indirectly through
861 // pB->i2eReadWord.
863 //******************************************************************************
864 static unsigned short
865 iiReadWord16(i2eBordStrPtr pB)
867 return (unsigned short)( INW(pB->i2eData) );
870 //******************************************************************************
871 // Function: iiReadWord8(pB)
872 // Parameters: pB - pointer to board structure
874 // Returns: True if everything appears copacetic.
875 // False if there is any error: the pB->i2eError field has the error
877 // Description:
879 // Returns the word read from the data fifo specified by the board-structure
880 // pointer pB. Uses two 8-bit operations. Bytes are assumed to be LSB first. Is
881 // called indirectly through pB->i2eReadWord.
883 //******************************************************************************
884 static unsigned short
885 iiReadWord8(i2eBordStrPtr pB)
887 unsigned short urs;
889 urs = INB ( pB->i2eData );
891 return ( ( INB ( pB->i2eData ) << 8 ) | urs );
894 //******************************************************************************
895 // Function: iiWriteWord16(pB, value)
896 // Parameters: pB - pointer to board structure
897 // value - data to write
899 // Returns: True if everything appears copacetic.
900 // False if there is any error: the pB->i2eError field has the error
902 // Description:
904 // Writes the word 'value' to the data fifo specified by the board-structure
905 // pointer pB. Uses 16-bit operation. Is called indirectly through
906 // pB->i2eWriteWord.
908 //******************************************************************************
909 static void
910 iiWriteWord16(i2eBordStrPtr pB, unsigned short value)
912 WORD_TO(pB, (int)value);
915 //******************************************************************************
916 // Function: iiWriteWord8(pB, value)
917 // Parameters: pB - pointer to board structure
918 // value - data to write
920 // Returns: True if everything appears copacetic.
921 // False if there is any error: the pB->i2eError field has the error
923 // Description:
925 // Writes the word 'value' to the data fifo specified by the board-structure
926 // pointer pB. Uses two 8-bit operations (writes LSB first). Is called
927 // indirectly through pB->i2eWriteWord.
929 //******************************************************************************
930 static void
931 iiWriteWord8(i2eBordStrPtr pB, unsigned short value)
933 BYTE_TO(pB, (char)value);
934 BYTE_TO(pB, (char)(value >> 8) );
937 //******************************************************************************
938 // Function: iiWaitForTxEmptyII(pB, mSdelay)
939 // Parameters: pB - pointer to board structure
940 // mSdelay - period to wait before returning
942 // Returns: True if the FIFO is empty.
943 // False if it not empty in the required time: the pB->i2eError
944 // field has the error.
946 // Description:
948 // Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if
949 // not empty by the required time, returns false and error in pB->i2eError,
950 // otherwise returns true.
952 // mSdelay == 0 is taken to mean must be empty on the first test.
954 // This version operates on IntelliPort-II - style FIFO's
956 // Note this routine is organized so that if status is ok there is no delay at
957 // all called either before or after the test. Is called indirectly through
958 // pB->i2eWaitForTxEmpty.
960 //******************************************************************************
961 static int
962 iiWaitForTxEmptyII(i2eBordStrPtr pB, int mSdelay)
964 unsigned long flags;
965 int itemp;
967 for (;;)
969 // This routine hinges on being able to see the "other" status register
970 // (as seen by the local processor). His incoming fifo is our outgoing
971 // FIFO.
973 // By the nature of this routine, you would be using this as part of a
974 // larger atomic context: i.e., you would use this routine to ensure the
975 // fifo empty, then act on this information. Between these two halves,
976 // you will generally not want to service interrupts or in any way
977 // disrupt the assumptions implicit in the larger context.
979 // Even worse, however, this routine "shifts" the status register to
980 // point to the local status register which is not the usual situation.
981 // Therefore for extra safety, we force the critical section to be
982 // completely atomic, and pick up after ourselves before allowing any
983 // interrupts of any kind.
986 WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags)
987 OUTB(pB->i2ePointer, SEL_COMMAND);
988 OUTB(pB->i2ePointer, SEL_CMD_SH);
990 itemp = INB(pB->i2eStatus);
992 OUTB(pB->i2ePointer, SEL_COMMAND);
993 OUTB(pB->i2ePointer, SEL_CMD_UNSH);
995 if (itemp & ST_IN_EMPTY)
997 UPDATE_FIFO_ROOM(pB);
998 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
999 COMPLETE(pB, I2EE_GOOD);
1002 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
1004 if (mSdelay-- == 0)
1005 break;
1007 iiDelay(pB, 1); /* 1 mS granularity on checking condition */
1009 COMPLETE(pB, I2EE_TXE_TIME);
1012 //******************************************************************************
1013 // Function: iiWaitForTxEmptyIIEX(pB, mSdelay)
1014 // Parameters: pB - pointer to board structure
1015 // mSdelay - period to wait before returning
1017 // Returns: True if the FIFO is empty.
1018 // False if it not empty in the required time: the pB->i2eError
1019 // field has the error.
1021 // Description:
1023 // Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if
1024 // not empty by the required time, returns false and error in pB->i2eError,
1025 // otherwise returns true.
1027 // mSdelay == 0 is taken to mean must be empty on the first test.
1029 // This version operates on IntelliPort-IIEX - style FIFO's
1031 // Note this routine is organized so that if status is ok there is no delay at
1032 // all called either before or after the test. Is called indirectly through
1033 // pB->i2eWaitForTxEmpty.
1035 //******************************************************************************
1036 static int
1037 iiWaitForTxEmptyIIEX(i2eBordStrPtr pB, int mSdelay)
1039 unsigned long flags;
1041 for (;;)
1043 // By the nature of this routine, you would be using this as part of a
1044 // larger atomic context: i.e., you would use this routine to ensure the
1045 // fifo empty, then act on this information. Between these two halves,
1046 // you will generally not want to service interrupts or in any way
1047 // disrupt the assumptions implicit in the larger context.
1049 WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags)
1051 if (INB(pB->i2eStatus) & STE_OUT_MT) {
1052 UPDATE_FIFO_ROOM(pB);
1053 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
1054 COMPLETE(pB, I2EE_GOOD);
1056 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
1058 if (mSdelay-- == 0)
1059 break;
1061 iiDelay(pB, 1); // 1 mS granularity on checking condition
1063 COMPLETE(pB, I2EE_TXE_TIME);
1066 //******************************************************************************
1067 // Function: iiTxMailEmptyII(pB)
1068 // Parameters: pB - pointer to board structure
1070 // Returns: True if the transmit mailbox is empty.
1071 // False if it not empty.
1073 // Description:
1075 // Returns true or false according to whether the transmit mailbox is empty (and
1076 // therefore able to accept more mail)
1078 // This version operates on IntelliPort-II - style FIFO's
1080 //******************************************************************************
1081 static int
1082 iiTxMailEmptyII(i2eBordStrPtr pB)
1084 int port = pB->i2ePointer;
1085 OUTB ( port, SEL_OUTMAIL );
1086 return ( INB(port) == 0 );
1089 //******************************************************************************
1090 // Function: iiTxMailEmptyIIEX(pB)
1091 // Parameters: pB - pointer to board structure
1093 // Returns: True if the transmit mailbox is empty.
1094 // False if it not empty.
1096 // Description:
1098 // Returns true or false according to whether the transmit mailbox is empty (and
1099 // therefore able to accept more mail)
1101 // This version operates on IntelliPort-IIEX - style FIFO's
1103 //******************************************************************************
1104 static int
1105 iiTxMailEmptyIIEX(i2eBordStrPtr pB)
1107 return !(INB(pB->i2eStatus) & STE_OUT_MAIL);
1110 //******************************************************************************
1111 // Function: iiTrySendMailII(pB,mail)
1112 // Parameters: pB - pointer to board structure
1113 // mail - value to write to mailbox
1115 // Returns: True if the transmit mailbox is empty, and mail is sent.
1116 // False if it not empty.
1118 // Description:
1120 // If outgoing mailbox is empty, sends mail and returns true. If outgoing
1121 // mailbox is not empty, returns false.
1123 // This version operates on IntelliPort-II - style FIFO's
1125 //******************************************************************************
1126 static int
1127 iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail)
1129 int port = pB->i2ePointer;
1131 OUTB(port, SEL_OUTMAIL);
1132 if (INB(port) == 0) {
1133 OUTB(port, SEL_OUTMAIL);
1134 OUTB(port, mail);
1135 return 1;
1137 return 0;
1140 //******************************************************************************
1141 // Function: iiTrySendMailIIEX(pB,mail)
1142 // Parameters: pB - pointer to board structure
1143 // mail - value to write to mailbox
1145 // Returns: True if the transmit mailbox is empty, and mail is sent.
1146 // False if it not empty.
1148 // Description:
1150 // If outgoing mailbox is empty, sends mail and returns true. If outgoing
1151 // mailbox is not empty, returns false.
1153 // This version operates on IntelliPort-IIEX - style FIFO's
1155 //******************************************************************************
1156 static int
1157 iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail)
1159 if(INB(pB->i2eStatus) & STE_OUT_MAIL) {
1160 return 0;
1162 OUTB(pB->i2eXMail, mail);
1163 return 1;
1166 //******************************************************************************
1167 // Function: iiGetMailII(pB,mail)
1168 // Parameters: pB - pointer to board structure
1170 // Returns: Mailbox data or NO_MAIL_HERE.
1172 // Description:
1174 // If no mail available, returns NO_MAIL_HERE otherwise returns the data from
1175 // the mailbox, which is guaranteed != NO_MAIL_HERE.
1177 // This version operates on IntelliPort-II - style FIFO's
1179 //******************************************************************************
1180 static unsigned short
1181 iiGetMailII(i2eBordStrPtr pB)
1183 if (HAS_MAIL(pB)) {
1184 OUTB(pB->i2ePointer, SEL_INMAIL);
1185 return INB(pB->i2ePointer);
1186 } else {
1187 return NO_MAIL_HERE;
1191 //******************************************************************************
1192 // Function: iiGetMailIIEX(pB,mail)
1193 // Parameters: pB - pointer to board structure
1195 // Returns: Mailbox data or NO_MAIL_HERE.
1197 // Description:
1199 // If no mail available, returns NO_MAIL_HERE otherwise returns the data from
1200 // the mailbox, which is guaranteed != NO_MAIL_HERE.
1202 // This version operates on IntelliPort-IIEX - style FIFO's
1204 //******************************************************************************
1205 static unsigned short
1206 iiGetMailIIEX(i2eBordStrPtr pB)
1208 if (HAS_MAIL(pB)) {
1209 return INB(pB->i2eXMail);
1210 } else {
1211 return NO_MAIL_HERE;
1215 //******************************************************************************
1216 // Function: iiEnableMailIrqII(pB)
1217 // Parameters: pB - pointer to board structure
1219 // Returns: Nothing
1221 // Description:
1223 // Enables board to interrupt host (only) by writing to host's in-bound mailbox.
1225 // This version operates on IntelliPort-II - style FIFO's
1227 //******************************************************************************
1228 static void
1229 iiEnableMailIrqII(i2eBordStrPtr pB)
1231 OUTB(pB->i2ePointer, SEL_MASK);
1232 OUTB(pB->i2ePointer, ST_IN_MAIL);
1235 //******************************************************************************
1236 // Function: iiEnableMailIrqIIEX(pB)
1237 // Parameters: pB - pointer to board structure
1239 // Returns: Nothing
1241 // Description:
1243 // Enables board to interrupt host (only) by writing to host's in-bound mailbox.
1245 // This version operates on IntelliPort-IIEX - style FIFO's
1247 //******************************************************************************
1248 static void
1249 iiEnableMailIrqIIEX(i2eBordStrPtr pB)
1251 OUTB(pB->i2eXMask, MX_IN_MAIL);
1254 //******************************************************************************
1255 // Function: iiWriteMaskII(pB)
1256 // Parameters: pB - pointer to board structure
1258 // Returns: Nothing
1260 // Description:
1262 // Writes arbitrary value to the mask register.
1264 // This version operates on IntelliPort-II - style FIFO's
1266 //******************************************************************************
1267 static void
1268 iiWriteMaskII(i2eBordStrPtr pB, unsigned char value)
1270 OUTB(pB->i2ePointer, SEL_MASK);
1271 OUTB(pB->i2ePointer, value);
1274 //******************************************************************************
1275 // Function: iiWriteMaskIIEX(pB)
1276 // Parameters: pB - pointer to board structure
1278 // Returns: Nothing
1280 // Description:
1282 // Writes arbitrary value to the mask register.
1284 // This version operates on IntelliPort-IIEX - style FIFO's
1286 //******************************************************************************
1287 static void
1288 iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value)
1290 OUTB(pB->i2eXMask, value);
1293 //******************************************************************************
1294 // Function: iiDownloadBlock(pB, pSource, isStandard)
1295 // Parameters: pB - pointer to board structure
1296 // pSource - loadware block to download
1297 // isStandard - True if "standard" loadware, else false.
1299 // Returns: Success or Failure
1301 // Description:
1303 // Downloads a single block (at pSource)to the board referenced by pB. Caller
1304 // sets isStandard to true/false according to whether the "standard" loadware is
1305 // what's being loaded. The normal process, then, is to perform an iiInitialize
1306 // to the board, then perform some number of iiDownloadBlocks using the returned
1307 // state to determine when download is complete.
1309 // Possible return values: (see I2ELLIS.H)
1310 // II_DOWN_BADVALID
1311 // II_DOWN_BADFILE
1312 // II_DOWN_CONTINUING
1313 // II_DOWN_GOOD
1314 // II_DOWN_BAD
1315 // II_DOWN_BADSTATE
1316 // II_DOWN_TIMEOUT
1318 // Uses the i2eState and i2eToLoad fields (initialized at iiInitialize) to
1319 // determine whether this is the first block, whether to check for magic
1320 // numbers, how many blocks there are to go...
1322 //******************************************************************************
1323 static int
1324 iiDownloadBlock ( i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard)
1326 int itemp;
1327 int loadedFirst;
1329 if (pB->i2eValid != I2E_MAGIC) return II_DOWN_BADVALID;
1331 switch(pB->i2eState)
1333 case II_STATE_READY:
1335 // Loading the first block after reset. Must check the magic number of the
1336 // loadfile, store the number of blocks we expect to load.
1337 if (pSource->e.loadMagic != MAGIC_LOADFILE)
1339 return II_DOWN_BADFILE;
1342 // Next we store the total number of blocks to load, including this one.
1343 pB->i2eToLoad = 1 + pSource->e.loadBlocksMore;
1345 // Set the state, store the version numbers. ('Cause this may have come
1346 // from a file - we might want to report these versions and revisions in
1347 // case of an error!
1348 pB->i2eState = II_STATE_LOADING;
1349 pB->i2eLVersion = pSource->e.loadVersion;
1350 pB->i2eLRevision = pSource->e.loadRevision;
1351 pB->i2eLSub = pSource->e.loadSubRevision;
1353 // The time and date of compilation is also available but don't bother
1354 // storing it for normal purposes.
1355 loadedFirst = 1;
1356 break;
1358 case II_STATE_LOADING:
1359 loadedFirst = 0;
1360 break;
1362 default:
1363 return II_DOWN_BADSTATE;
1366 // Now we must be in the II_STATE_LOADING state, and we assume i2eToLoad
1367 // must be positive still, because otherwise we would have cleaned up last
1368 // time and set the state to II_STATE_LOADED.
1369 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) {
1370 return II_DOWN_TIMEOUT;
1373 if (!iiWriteBuf(pB, pSource->c, LOADWARE_BLOCK_SIZE)) {
1374 return II_DOWN_BADVALID;
1377 // If we just loaded the first block, wait for the fifo to empty an extra
1378 // long time to allow for any special startup code in the firmware, like
1379 // sending status messages to the LCD's.
1381 if (loadedFirst) {
1382 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_START_TIME)) {
1383 return II_DOWN_TIMEOUT;
1387 // Determine whether this was our last block!
1388 if (--(pB->i2eToLoad)) {
1389 return II_DOWN_CONTINUING; // more to come...
1392 // It WAS our last block: Clean up operations...
1393 // ...Wait for last buffer to drain from the board...
1394 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) {
1395 return II_DOWN_TIMEOUT;
1397 // If there were only a single block written, this would come back
1398 // immediately and be harmless, though not strictly necessary.
1399 itemp = MAX_DLOAD_ACK_TIME/10;
1400 while (--itemp) {
1401 if (HAS_INPUT(pB)) {
1402 switch(BYTE_FROM(pB))
1404 case LOADWARE_OK:
1405 pB->i2eState =
1406 isStandard ? II_STATE_STDLOADED :II_STATE_LOADED;
1408 // Some revisions of the bootstrap firmware (e.g. ISA-8 1.0.2)
1409 // will, // if there is a debug port attached, require some
1410 // time to send information to the debug port now. It will do
1411 // this before // executing any of the code we just downloaded.
1412 // It may take up to 700 milliseconds.
1413 if (pB->i2ePom.e.porDiag2 & POR_DEBUG_PORT) {
1414 iiDelay(pB, 700);
1417 return II_DOWN_GOOD;
1419 case LOADWARE_BAD:
1420 default:
1421 return II_DOWN_BAD;
1425 iiDelay(pB, 10); // 10 mS granularity on checking condition
1428 // Drop-through --> timed out waiting for firmware confirmation
1430 pB->i2eState = II_STATE_BADLOAD;
1431 return II_DOWN_TIMEOUT;
1434 //******************************************************************************
1435 // Function: iiDownloadAll(pB, pSource, isStandard, size)
1436 // Parameters: pB - pointer to board structure
1437 // pSource - loadware block to download
1438 // isStandard - True if "standard" loadware, else false.
1439 // size - size of data to download (in bytes)
1441 // Returns: Success or Failure
1443 // Description:
1445 // Given a pointer to a board structure, a pointer to the beginning of some
1446 // loadware, whether it is considered the "standard loadware", and the size of
1447 // the array in bytes loads the entire array to the board as loadware.
1449 // Assumes the board has been freshly reset and the power-up reset message read.
1450 // (i.e., in II_STATE_READY). Complains if state is bad, or if there seems to be
1451 // too much or too little data to load, or if iiDownloadBlock complains.
1452 //******************************************************************************
1453 static int
1454 iiDownloadAll(i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard, int size)
1456 int status;
1458 // We know (from context) board should be ready for the first block of
1459 // download. Complain if not.
1460 if (pB->i2eState != II_STATE_READY) return II_DOWN_BADSTATE;
1462 while (size > 0) {
1463 size -= LOADWARE_BLOCK_SIZE; // How much data should there be left to
1464 // load after the following operation ?
1466 // Note we just bump pSource by "one", because its size is actually that
1467 // of an entire block, same as LOADWARE_BLOCK_SIZE.
1468 status = iiDownloadBlock(pB, pSource++, isStandard);
1470 switch(status)
1472 case II_DOWN_GOOD:
1473 return ( (size > 0) ? II_DOWN_OVER : II_DOWN_GOOD);
1475 case II_DOWN_CONTINUING:
1476 break;
1478 default:
1479 return status;
1483 // We shouldn't drop out: it means "while" caught us with nothing left to
1484 // download, yet the previous DownloadBlock did not return complete. Ergo,
1485 // not enough data to match the size byte in the header.
1486 return II_DOWN_UNDER;