drivers/net/au1000_eth.h

   1 /*
   2  *
   3  * Alchemy Au1x00 ethernet driver include file
   4  *
   5  * Author: Pete Popov <ppopov@mvista.com>
   6  *
   7  * Copyright 2001 MontaVista Software Inc.
   8  *
   9  * ########################################################################
  10  *
  11  *  This program is free software; you can distribute it and/or modify it
  12  *  under the terms of the GNU General Public License (Version 2) as
  13  *  published by the Free Software Foundation.
  14  *
  15  *  This program is distributed in the hope it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18  *  for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along
  21  *  with this program; if not, write to the Free Software Foundation, Inc.,
  22  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  23  *
  24  * ########################################################################
  25  *
  26  *
  27  */
  28
  29
  30 #define MAC_IOSIZE 0x10000
  31 #define NUM_RX_DMA 4       /* Au1x00 has 4 rx hardware descriptors */
  32 #define NUM_TX_DMA 4       /* Au1x00 has 4 tx hardware descriptors */
  33
  34 #define NUM_RX_BUFFS 4
  35 #define NUM_TX_BUFFS 4
  36 #define MAX_BUF_SIZE 2048
  37
  38 #define ETH_TX_TIMEOUT HZ/4
  39 #define MAC_MIN_PKT_SIZE 64
  40
  41 #define MULTICAST_FILTER_LIMIT 64
  42
  43 /* FIXME
  44  * The PHY defines should be in a separate file.
  45  */
  46
  47 /* MII register offsets */
  48 #define MII_CONTROL 0x0000
  49 #define MII_STATUS  0x0001
  50 #define MII_PHY_ID0 0x0002
  51 #define MII_PHY_ID1 0x0003
  52 #define MII_ANADV   0x0004
  53 #define MII_ANLPAR  0x0005
  54 #define MII_AEXP    0x0006
  55 #define MII_ANEXT   0x0007
  56 #define MII_LSI_PHY_CONFIG 0x0011
  57 /* Status register */
  58 #define MII_LSI_PHY_STAT   0x0012
  59 #define MII_AMD_PHY_STAT   MII_LSI_PHY_STAT
  60 #define MII_INTEL_PHY_STAT 0x0011
  61
  62 #define MII_AUX_CNTRL  0x0018
  63 /* mii registers specific to AMD 79C901 */
  64 #define MII_STATUS_SUMMARY = 0x0018
  65
  66 /* MII Control register bit definitions. */
  67 #define MII_CNTL_FDX      0x0100
  68 #define MII_CNTL_RST_AUTO 0x0200
  69 #define MII_CNTL_ISOLATE  0x0400
  70 #define MII_CNTL_PWRDWN   0x0800
  71 #define MII_CNTL_AUTO     0x1000
  72 #define MII_CNTL_F100     0x2000
  73 #define MII_CNTL_LPBK     0x4000
  74 #define MII_CNTL_RESET    0x8000
  75
  76 /* MII Status register bit  */
  77 #define MII_STAT_EXT        0x0001
  78 #define MII_STAT_JAB        0x0002
  79 #define MII_STAT_LINK       0x0004
  80 #define MII_STAT_CAN_AUTO   0x0008
  81 #define MII_STAT_FAULT      0x0010
  82 #define MII_STAT_AUTO_DONE  0x0020
  83 #define MII_STAT_CAN_T      0x0800
  84 #define MII_STAT_CAN_T_FDX  0x1000
  85 #define MII_STAT_CAN_TX     0x2000
  86 #define MII_STAT_CAN_TX_FDX 0x4000
  87 #define MII_STAT_CAN_T4     0x8000
  88
  89
  90 #define         MII_ID1_OUI_LO          0xFC00  /* low bits of OUI mask */
  91 #define         MII_ID1_MODEL           0x03F0  /* model number */
  92 #define         MII_ID1_REV             0x000F  /* model number */
  93
  94 /* MII NWAY Register Bits ...
  95    valid for the ANAR (Auto-Negotiation Advertisement) and
  96    ANLPAR (Auto-Negotiation Link Partner) registers */
  97 #define MII_NWAY_NODE_SEL 0x001f
  98 #define MII_NWAY_CSMA_CD  0x0001
  99 #define MII_NWAY_T        0x0020
 100 #define MII_NWAY_T_FDX    0x0040
 101 #define MII_NWAY_TX       0x0080
 102 #define MII_NWAY_TX_FDX   0x0100
 103 #define MII_NWAY_T4       0x0200
 104 #define MII_NWAY_PAUSE    0x0400
 105 #define MII_NWAY_RF       0x2000 /* Remote Fault */
 106 #define MII_NWAY_ACK      0x4000 /* Remote Acknowledge */
 107 #define MII_NWAY_NP       0x8000 /* Next Page (Enable) */
 108
 109 /* mii stsout register bits */
 110 #define MII_STSOUT_LINK_FAIL 0x4000
 111 #define MII_STSOUT_SPD       0x0080
 112 #define MII_STSOUT_DPLX      0x0040
 113
 114 /* mii stsics register bits */
 115 #define MII_STSICS_SPD       0x8000
 116 #define MII_STSICS_DPLX      0x4000
 117 #define MII_STSICS_LINKSTS   0x0001
 118
 119 /* mii stssum register bits */
 120 #define MII_STSSUM_LINK  0x0008
 121 #define MII_STSSUM_DPLX  0x0004
 122 #define MII_STSSUM_AUTO  0x0002
 123 #define MII_STSSUM_SPD   0x0001
 124
 125 /* lsi phy status register */
 126 #define MII_LSI_PHY_STAT_FDX    0x0040
 127 #define MII_LSI_PHY_STAT_SPD    0x0080
 128
 129 /* amd phy status register */
 130 #define MII_AMD_PHY_STAT_FDX    0x0800
 131 #define MII_AMD_PHY_STAT_SPD    0x0400
 132
 133 /* intel phy status register */
 134 #define MII_INTEL_PHY_STAT_FDX  0x0200
 135 #define MII_INTEL_PHY_STAT_SPD  0x4000
 136
 137 /* Auxilliary Control/Status Register */
 138 #define MII_AUX_FDX      0x0001
 139 #define MII_AUX_100      0x0002
 140 #define MII_AUX_F100     0x0004
 141 #define MII_AUX_ANEG     0x0008
 142
 143 typedef struct mii_phy {
 144         struct mii_phy * next;
 145         struct mii_chip_info * chip_info;
 146         u16 status;
 147         u32 *mii_control_reg;
 148         u32 *mii_data_reg;
 149 } mii_phy_t;
 150
 151 struct phy_ops {
 152         int (*phy_init) (struct net_device *, int);
 153         int (*phy_reset) (struct net_device *, int);
 154         int (*phy_status) (struct net_device *, int, u16 *, u16 *);
 155 };
 156
 157 /*
 158  * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
 159  * boundary for both, receive and transmit.
 160  */
 161 typedef struct db_dest {
 162         struct db_dest *pnext;
 163         volatile u32 *vaddr;
 164         dma_addr_t dma_addr;
 165 } db_dest_t;
 166
 167 /*
 168  * The transmit and receive descriptors are memory
 169  * mapped registers.
 170  */
 171 typedef struct tx_dma {
 172         u32 status;
 173         u32 buff_stat;
 174         u32 len;
 175         u32 pad;
 176 } tx_dma_t;
 177
 178 typedef struct rx_dma {
 179         u32 status;
 180         u32 buff_stat;
 181         u32 pad[2];
 182 } rx_dma_t;
 183
 184
 185 /*
 186  * MAC control registers, memory mapped.
 187  */
 188 typedef struct mac_reg {
 189         u32 control;
 190         u32 mac_addr_high;
 191         u32 mac_addr_low;
 192         u32 multi_hash_high;
 193         u32 multi_hash_low;
 194         u32 mii_control;
 195         u32 mii_data;
 196         u32 flow_control;
 197         u32 vlan1_tag;
 198         u32 vlan2_tag;
 199 } mac_reg_t;
 200
 201
 202 struct au1000_private {
 203
 204         db_dest_t *pDBfree;
 205         db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS];
 206         volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA];
 207         volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA];
 208         db_dest_t *rx_db_inuse[NUM_RX_DMA];
 209         db_dest_t *tx_db_inuse[NUM_TX_DMA];
 210         u32 rx_head;
 211         u32 tx_head;
 212         u32 tx_tail;
 213         u32 tx_full;
 214
 215         int mac_id;
 216         mii_phy_t *mii;
 217         struct phy_ops *phy_ops;
 218
 219         /* These variables are just for quick access to certain regs addresses. */
 220         volatile mac_reg_t *mac;  /* mac registers                      */
 221         volatile u32 *enable;     /* address of MAC Enable Register     */
 222
 223         u32 vaddr;                /* virtual address of rx/tx buffers   */
 224         dma_addr_t dma_addr;      /* dma address of rx/tx buffers       */
 225
 226         u8 *hash_table;
 227         u32 hash_mode;
 228         u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */
 229         int phy_addr;          /* phy address */
 230         u32 options;           /* User-settable misc. driver options. */
 231         u32 drv_flags;
 232         int want_autoneg;
 233         struct net_device_stats stats;
 234         struct timer_list timer;
 235         spinlock_t lock;       /* Serialise access to device */
 236 };