| blob | a6aa56598f2712bec5c1a027f5c54f604b89d4a2 |
1 /*
2 * File Name:
3 * defxx.c
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
14 *
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
17 *
18 * The original author:
19 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
20 *
21 * Maintainers:
22 * macro Maciej W. Rozycki <macro@linux-mips.org>
23 *
24 * Credits:
25 * I'd like to thank Patricia Cross for helping me get started with
26 * Linux, David Davies for a lot of help upgrading and configuring
27 * my development system and for answering many OS and driver
28 * development questions, and Alan Cox for recommendations and
29 * integration help on getting FDDI support into Linux. LVS
30 *
31 * Driver Architecture:
32 * The driver architecture is largely based on previous driver work
33 * for other operating systems. The upper edge interface and
34 * functions were largely taken from existing Linux device drivers
35 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
36 * driver.
37 *
38 * Adapter Probe -
39 * The driver scans for supported EISA adapters by reading the
40 * SLOT ID register for each EISA slot and making a match
41 * against the expected value.
42 *
43 * Bus-Specific Initialization -
44 * This driver currently supports both EISA and PCI controller
45 * families. While the custom DMA chip and FDDI logic is similar
46 * or identical, the bus logic is very different. After
47 * initialization, the only bus-specific differences is in how the
48 * driver enables and disables interrupts. Other than that, the
49 * run-time critical code behaves the same on both families.
50 * It's important to note that both adapter families are configured
51 * to I/O map, rather than memory map, the adapter registers.
52 *
53 * Driver Open/Close -
54 * In the driver open routine, the driver ISR (interrupt service
55 * routine) is registered and the adapter is brought to an
56 * operational state. In the driver close routine, the opposite
57 * occurs; the driver ISR is deregistered and the adapter is
58 * brought to a safe, but closed state. Users may use consecutive
59 * commands to bring the adapter up and down as in the following
60 * example:
61 * ifconfig fddi0 up
62 * ifconfig fddi0 down
63 * ifconfig fddi0 up
64 *
65 * Driver Shutdown -
66 * Apparently, there is no shutdown or halt routine support under
67 * Linux. This routine would be called during "reboot" or
68 * "shutdown" to allow the driver to place the adapter in a safe
69 * state before a warm reboot occurs. To be really safe, the user
70 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
71 * to ensure that the adapter DMA engine is taken off-line. However,
72 * the current driver code anticipates this problem and always issues
73 * a soft reset of the adapter at the beginning of driver initialization.
74 * A future driver enhancement in this area may occur in 2.1.X where
75 * Alan indicated that a shutdown handler may be implemented.
76 *
77 * Interrupt Service Routine -
78 * The driver supports shared interrupts, so the ISR is registered for
79 * each board with the appropriate flag and the pointer to that board's
80 * device structure. This provides the context during interrupt
81 * processing to support shared interrupts and multiple boards.
82 *
83 * Interrupt enabling/disabling can occur at many levels. At the host
84 * end, you can disable system interrupts, or disable interrupts at the
85 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
86 * have a bus-logic chip interrupt enable/disable as well as a DMA
87 * controller interrupt enable/disable.
88 *
89 * The driver currently enables and disables adapter interrupts at the
90 * bus-logic chip and assumes that Linux will take care of clearing or
91 * acknowledging any host-based interrupt chips.
92 *
93 * Control Functions -
94 * Control functions are those used to support functions such as adding
95 * or deleting multicast addresses, enabling or disabling packet
96 * reception filters, or other custom/proprietary commands. Presently,
97 * the driver supports the "get statistics", "set multicast list", and
98 * "set mac address" functions defined by Linux. A list of possible
99 * enhancements include:
100 *
101 * - Custom ioctl interface for executing port interface commands
102 * - Custom ioctl interface for adding unicast addresses to
103 * adapter CAM (to support bridge functions).
104 * - Custom ioctl interface for supporting firmware upgrades.
105 *
106 * Hardware (port interface) Support Routines -
107 * The driver function names that start with "dfx_hw_" represent
108 * low-level port interface routines that are called frequently. They
109 * include issuing a DMA or port control command to the adapter,
110 * resetting the adapter, or reading the adapter state. Since the
111 * driver initialization and run-time code must make calls into the
112 * port interface, these routines were written to be as generic and
113 * usable as possible.
114 *
115 * Receive Path -
116 * The adapter DMA engine supports a 256 entry receive descriptor block
117 * of which up to 255 entries can be used at any given time. The
118 * architecture is a standard producer, consumer, completion model in
119 * which the driver "produces" receive buffers to the adapter, the
120 * adapter "consumes" the receive buffers by DMAing incoming packet data,
121 * and the driver "completes" the receive buffers by servicing the
122 * incoming packet, then "produces" a new buffer and starts the cycle
123 * again. Receive buffers can be fragmented in up to 16 fragments
124 * (descriptor entries). For simplicity, this driver posts
125 * single-fragment receive buffers of 4608 bytes, then allocates a
126 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
127 * utilization, a better approach would be to pass up the receive
128 * buffer (no extra copy) then allocate and post a replacement buffer.
129 * This is a performance enhancement that should be looked into at
130 * some point.
131 *
132 * Transmit Path -
133 * Like the receive path, the adapter DMA engine supports a 256 entry
134 * transmit descriptor block of which up to 255 entries can be used at
135 * any given time. Transmit buffers can be fragmented in up to 255
136 * fragments (descriptor entries). This driver always posts one
137 * fragment per transmit packet request.
138 *
139 * The fragment contains the entire packet from FC to end of data.
140 * Before posting the buffer to the adapter, the driver sets a three-byte
141 * packet request header (PRH) which is required by the Motorola MAC chip
142 * used on the adapters. The PRH tells the MAC the type of token to
143 * receive/send, whether or not to generate and append the CRC, whether
144 * synchronous or asynchronous framing is used, etc. Since the PRH
145 * definition is not necessarily consistent across all FDDI chipsets,
146 * the driver, rather than the common FDDI packet handler routines,
147 * sets these bytes.
148 *
149 * To reduce the amount of descriptor fetches needed per transmit request,
150 * the driver takes advantage of the fact that there are at least three
151 * bytes available before the skb->data field on the outgoing transmit
152 * request. This is guaranteed by having fddi_setup() in net_init.c set
153 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
154 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
155 * bytes which we'll use to store the PRH.
156 *
157 * There's a subtle advantage to adding these pad bytes to the
158 * hard_header_len, it ensures that the data portion of the packet for
159 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
160 * implementations may not need the extra padding and can start copying
161 * or DMAing directly from the FC byte which starts at skb->data. Should
162 * another driver implementation need ADDITIONAL padding, the net_init.c
163 * module should be updated and dev->hard_header_len should be increased.
164 * NOTE: To maintain the alignment on the data portion of the packet,
165 * dev->hard_header_len should always be evenly divisible by 4 and at
166 * least 24 bytes in size.
167 *
168 * Modification History:
169 * Date Name Description
170 * 16-Aug-96 LVS Created.
171 * 20-Aug-96 LVS Updated dfx_probe so that version information
172 * string is only displayed if 1 or more cards are
173 * found. Changed dfx_rcv_queue_process to copy
174 * 3 NULL bytes before FC to ensure that data is
175 * longword aligned in receive buffer.
176 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
177 * LLC group promiscuous mode if multicast list
178 * is too large. LLC individual/group promiscuous
179 * mode is now disabled if IFF_PROMISC flag not set.
180 * dfx_xmt_queue_pkt no longer checks for NULL skb
181 * on Alan Cox recommendation. Added node address
182 * override support.
183 * 12-Sep-96 LVS Reset current address to factory address during
184 * device open. Updated transmit path to post a
185 * single fragment which includes PRH->end of data.
186 * Mar 2000 AC Did various cleanups for 2.3.x
187 * Jun 2000 jgarzik PCI and resource alloc cleanups
188 * Jul 2000 tjeerd Much cleanup and some bug fixes
189 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
190 * Feb 2001 Skb allocation fixes
191 * Feb 2001 davej PCI enable cleanups.
192 * 04 Aug 2003 macro Converted to the DMA API.
193 * 14 Aug 2004 macro Fix device names reported.
194 */
196 /* Include files */
198 #include <linux/module.h>
199 #include <linux/kernel.h>
200 #include <linux/string.h>
201 #include <linux/errno.h>
202 #include <linux/ioport.h>
203 #include <linux/slab.h>
204 #include <linux/interrupt.h>
205 #include <linux/pci.h>
206 #include <linux/delay.h>
207 #include <linux/init.h>
208 #include <linux/netdevice.h>
209 #include <linux/fddidevice.h>
210 #include <linux/skbuff.h>
211 #include <linux/bitops.h>
213 #include <asm/byteorder.h>
214 #include <asm/io.h>
218 /* Version information string should be updated prior to each new release! */
227 #define DYNAMIC_BUFFERS 1
229 #define SKBUFF_RX_COPYBREAK 200
230 /*
231 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
232 * alignment for compatibility with old EISA boards.
233 */
234 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
236 /* Define module-wide (static) routines */
259 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
272 /* Define module-wide (static) variables */
276 \f
277 /*
278 * =======================
279 * = dfx_port_write_byte =
280 * = dfx_port_read_byte =
281 * = dfx_port_write_long =
282 * = dfx_port_read_long =
283 * =======================
284 *
285 * Overview:
286 * Routines for reading and writing values from/to adapter
287 *
288 * Returns:
289 * None
290 *
291 * Arguments:
292 * bp - pointer to board information
293 * offset - register offset from base I/O address
294 * data - for dfx_port_write_byte and dfx_port_write_long, this
295 * is a value to write.
296 * for dfx_port_read_byte and dfx_port_read_byte, this
297 * is a pointer to store the read value.
298 *
299 * Functional Description:
300 * These routines perform the correct operation to read or write
301 * the adapter register.
302 *
303 * EISA port block base addresses are based on the slot number in which the
304 * controller is installed. For example, if the EISA controller is installed
305 * in slot 4, the port block base address is 0x4000. If the controller is
306 * installed in slot 2, the port block base address is 0x2000, and so on.
307 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
308 * registers using the register offsets defined in DEFXX.H.
309 *
310 * PCI port block base addresses are assigned by the PCI BIOS or system
311 * firmware. There is one 128 byte port block which can be accessed. It
312 * allows for I/O mapping of both PDQ and PFI registers using the register
313 * offsets defined in DEFXX.H.
314 *
315 * Return Codes:
316 * None
317 *
318 * Assumptions:
319 * bp->base_addr is a valid base I/O address for this adapter.
320 * offset is a valid register offset for this adapter.
321 *
322 * Side Effects:
323 * Rather than produce macros for these functions, these routines
324 * are defined using "inline" to ensure that the compiler will
325 * generate inline code and not waste a procedure call and return.
326 * This provides all the benefits of macros, but with the
327 * advantage of strict data type checking.
328 */
333 u8 data
334 )
336 {
340 }
345 u8 *data
346 )
348 {
352 }
357 u32 data
358 )
360 {
364 }
369 u32 *data
370 )
372 {
376 }
378 \f
379 /*
380 * =============
381 * = dfx_init_one_pci_or_eisa =
382 * =============
383 *
384 * Overview:
385 * Initializes a supported FDDI EISA or PCI controller
386 *
387 * Returns:
388 * Condition code
389 *
390 * Arguments:
391 * pdev - pointer to pci device information (NULL for EISA)
392 * ioaddr - pointer to port (NULL for PCI)
393 *
394 * Functional Description:
395 *
396 * Return Codes:
397 * 0 - This device (fddi0, fddi1, etc) configured successfully
398 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
399 *
400 * Assumptions:
401 * It compiles so it should work :-( (PCI cards do :-)
402 *
403 * Side Effects:
404 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
405 * initialized and the board resources are read and stored in
406 * the device structure.
407 */
409 {
420 }
428 print_name);
430 }
432 /* Enable PCI device. */
437 }
446 print_name)) {
452 }
454 /* Initialize new device structure */
466 /* EISA board */
471 /* PCI board */
476 }
481 }
490 err_out_kfree:
493 #ifndef DYNAMIC_BUFFERS
495 #endif
501 err_out_region:
503 err_out:
506 }
509 {
511 }
514 {
522 /* Scan for FDDI EISA controllers */
525 {
529 {
533 }
534 }
536 }
537 \f
538 /*
539 * ================
540 * = dfx_bus_init =
541 * ================
542 *
543 * Overview:
544 * Initializes EISA and PCI controller bus-specific logic.
545 *
546 * Returns:
547 * None
548 *
549 * Arguments:
550 * dev - pointer to device information
551 *
552 * Functional Description:
553 * Determine and save adapter IRQ in device table,
554 * then perform bus-specific logic initialization.
555 *
556 * Return Codes:
557 * None
558 *
559 * Assumptions:
560 * dev->base_addr has already been set with the proper
561 * base I/O address for this device.
562 *
563 * Side Effects:
564 * Interrupts are enabled at the adapter bus-specific logic.
565 * Note: Interrupts at the DMA engine (PDQ chip) are not
566 * enabled yet.
567 */
570 {
576 /*
577 * Initialize base I/O address field in bp structure
578 *
579 * Note: bp->base_addr is the same as dev->base_addr.
580 * It's useful because often we'll need to read
581 * or write registers where we already have the
582 * bp pointer instead of the dev pointer. Having
583 * the base address in the bp structure will
584 * save a pointer dereference.
585 *
586 * IMPORTANT!! This field must be defined before
587 * any of the dfx_port_* inline functions are
588 * called.
589 */
593 /* And a pointer back to the net_device struct */
596 /* Initialize adapter based on bus type */
599 {
600 /* Get the interrupt level from the ESIC chip */
604 {
620 }
622 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
626 /* Set the I/O decode range of the board */
632 /* Enable access to rest of module (including PDQ and packet memory) */
636 /*
637 * Map PDQ registers into I/O space. This is done by clearing a bit
638 * in Burst Holdoff register.
639 */
644 /* Enable interrupts at EISA bus interface chip (ESIC) */
648 }
649 else
650 {
653 /* Get the interrupt level from the PCI Configuration Table */
657 /* Check Latency Timer and set if less than minimal */
661 {
664 }
666 /* Enable interrupts at PCI bus interface chip (PFI) */
669 }
670 }
672 \f
673 /*
674 * ========================
675 * = dfx_bus_config_check =
676 * ========================
677 *
678 * Overview:
679 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
680 * are illegal, then this routine will set new defaults.
681 *
682 * Returns:
683 * None
684 *
685 * Arguments:
686 * bp - pointer to board information
687 *
688 * Functional Description:
689 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
690 * PDQ, and all FDDI PCI controllers, all values are legal.
691 *
692 * Return Codes:
693 * None
694 *
695 * Assumptions:
696 * dfx_adap_init has NOT been called yet so burst size and other items have
697 * not been set.
698 *
699 * Side Effects:
700 * None
701 */
704 {
711 /* Configuration check only valid for EISA adapter */
714 {
717 /*
718 * First check if revision 2 EISA controller. Rev. 1 cards used
719 * PDQ revision B, so no workaround needed in this case. Rev. 3
720 * cards used PDQ revision E, so no workaround needed in this
721 * case, either. Only Rev. 2 cards used either Rev. D or E
722 * chips, so we must verify the chip revision on Rev. 2 cards.
723 */
726 {
727 /*
728 * Revision 2 FDDI EISA controller found, so let's check PDQ
729 * revision of adapter.
730 */
733 PI_PCTRL_M_SUB_CMD,
734 PI_SUB_CMD_K_PDQ_REV_GET,
738 {
739 /*
740 * Either we couldn't determine the PDQ revision, or
741 * we determined that it is at revision D. In either case,
742 * we need to implement the workaround.
743 */
745 /* Ensure that the burst size is set to 8 longwords or less */
748 {
756 }
758 /* Ensure that full-duplex mode is not enabled */
761 }
762 }
763 }
764 }
766 \f
767 /*
768 * ===================
769 * = dfx_driver_init =
770 * ===================
771 *
772 * Overview:
773 * Initializes remaining adapter board structure information
774 * and makes sure adapter is in a safe state prior to dfx_open().
775 *
776 * Returns:
777 * Condition code
778 *
779 * Arguments:
780 * dev - pointer to device information
781 * print_name - printable device name
782 *
783 * Functional Description:
784 * This function allocates additional resources such as the host memory
785 * blocks needed by the adapter (eg. descriptor and consumer blocks).
786 * Remaining bus initialization steps are also completed. The adapter
787 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
788 * must call dfx_open() to open the adapter and bring it on-line.
789 *
790 * Return Codes:
791 * DFX_K_SUCCESS - initialization succeeded
792 * DFX_K_FAILURE - initialization failed - could not allocate memory
793 * or read adapter MAC address
794 *
795 * Assumptions:
796 * Memory allocated from pci_alloc_consistent() call is physically
797 * contiguous, locked memory.
798 *
799 * Side Effects:
800 * Adapter is reset and should be in DMA_UNAVAILABLE state before
801 * returning from this routine.
802 */
806 {
815 /* Initialize bus-specific hardware registers */
819 /*
820 * Initialize default values for configurable parameters
821 *
822 * Note: All of these parameters are ones that a user may
823 * want to customize. It'd be nice to break these
824 * out into Space.c or someplace else that's more
825 * accessible/understandable than this file.
826 */
833 /*
834 * Ensure that HW configuration is OK
835 *
836 * Note: Depending on the hardware revision, we may need to modify
837 * some of the configurable parameters to workaround hardware
838 * limitations. We'll perform this configuration check AFTER
839 * setting the parameters to their default values.
840 */
844 /* Disable PDQ interrupts first */
848 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
852 /* Read the factory MAC address from the adapter then save it */
857 print_name);
859 }
865 print_name);
867 }
870 /*
871 * Set current address to factory address
872 *
873 * Note: Node address override support is handled through
874 * dfx_ctl_set_mac_address.
875 */
885 else
893 /*
894 * Get memory for descriptor block, consumer block, and other buffers
895 * that need to be DMA read or written to by the adapter.
896 */
899 PI_CMD_REQ_K_SIZE_MAX +
900 PI_CMD_RSP_K_SIZE_MAX +
901 #ifndef DYNAMIC_BUFFERS
903 #endif
912 }
916 /*
917 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
918 * plus the amount of memory needed was allocated. The physical address
919 * is now 8K aligned. By carving up the memory in a specific order,
920 * we'll guarantee the alignment requirements for all other structures.
921 *
922 * Note: If the assumptions change regarding the non-paged, non-cached,
923 * physically contiguous nature of the memory block or the address
924 * alignments, then we'll need to implement a different algorithm
925 * for allocating the needed memory.
926 */
931 /* Reserve space for descriptor block */
938 /* Reserve space for command request buffer */
945 /* Reserve space for command response buffer */
952 /* Reserve space for the LLC host receive queue buffers */
957 #ifndef DYNAMIC_BUFFERS
960 #endif
962 /* Reserve space for the consumer block */
967 /* Display virtual and physical addresses if debug driver */
970 print_name,
982 }
984 \f
985 /*
986 * =================
987 * = dfx_adap_init =
988 * =================
989 *
990 * Overview:
991 * Brings the adapter to the link avail/link unavailable state.
992 *
993 * Returns:
994 * Condition code
995 *
996 * Arguments:
997 * bp - pointer to board information
998 * get_buffers - non-zero if buffers to be allocated
999 *
1000 * Functional Description:
1001 * Issues the low-level firmware/hardware calls necessary to bring
1002 * the adapter up, or to properly reset and restore adapter during
1003 * run-time.
1004 *
1005 * Return Codes:
1006 * DFX_K_SUCCESS - Adapter brought up successfully
1007 * DFX_K_FAILURE - Adapter initialization failed
1008 *
1009 * Assumptions:
1010 * bp->reset_type should be set to a valid reset type value before
1011 * calling this routine.
1012 *
1013 * Side Effects:
1014 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1015 * upon a successful return of this routine.
1016 */
1019 {
1022 /* Disable PDQ interrupts first */
1026 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1029 {
1032 }
1034 /*
1035 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1036 * so we'll acknowledge all Type 0 interrupts now before continuing.
1037 */
1041 /*
1042 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1043 *
1044 * Note: We only need to clear host copies of these registers. The PDQ reset
1045 * takes care of the on-board register values.
1046 */
1052 /* Clear consumer block before going to DMA_AVAILABLE state */
1056 /* Initialize the DMA Burst Size */
1059 PI_PCTRL_M_SUB_CMD,
1060 PI_SUB_CMD_K_BURST_SIZE_SET,
1063 {
1066 }
1068 /*
1069 * Set base address of Consumer Block
1070 *
1071 * Assumption: 32-bit physical address of consumer block is 64 byte
1072 * aligned. That is, bits 0-5 of the address must be zero.
1073 */
1076 PI_PCTRL_M_CONS_BLOCK,
1080 {
1083 }
1085 /*
1086 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1087 *
1088 * Note: We also set the literal and data swapping requirements in this
1089 * command. Since this driver presently runs on Intel platforms
1090 * which are Little Endian, we'll tell the adapter to byte swap
1091 * data only. This code will need to change when we support
1092 * Big Endian systems (eg. PowerPC).
1093 *
1094 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1095 * aligned. That is, bits 0-12 of the address must be zero.
1096 */
1099 PI_PCTRL_M_INIT,
1103 {
1106 }
1108 /* Set transmit flush timeout value */
1116 {
1119 }
1121 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1132 {
1135 }
1137 /* Initialize adapter CAM */
1140 {
1143 }
1145 /* Initialize adapter filters */
1148 {
1151 }
1153 /*
1154 * Remove any existing dynamic buffers (i.e. if the adapter is being
1155 * reinitialized)
1156 */
1161 /* Initialize receive descriptor block and produce buffers */
1164 {
1169 }
1171 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1175 {
1180 }
1182 /* Initialization succeeded, reenable PDQ interrupts */
1186 }
1188 \f
1189 /*
1190 * ============
1191 * = dfx_open =
1192 * ============
1193 *
1194 * Overview:
1195 * Opens the adapter
1196 *
1197 * Returns:
1198 * Condition code
1199 *
1200 * Arguments:
1201 * dev - pointer to device information
1202 *
1203 * Functional Description:
1204 * This function brings the adapter to an operational state.
1205 *
1206 * Return Codes:
1207 * 0 - Adapter was successfully opened
1208 * -EAGAIN - Could not register IRQ or adapter initialization failed
1209 *
1210 * Assumptions:
1211 * This routine should only be called for a device that was
1212 * initialized successfully.
1213 *
1214 * Side Effects:
1215 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1216 * if the open is successful.
1217 */
1220 {
1226 /* Register IRQ - support shared interrupts by passing device ptr */
1232 }
1234 /*
1235 * Set current address to factory MAC address
1236 *
1237 * Note: We've already done this step in dfx_driver_init.
1238 * However, it's possible that a user has set a node
1239 * address override, then closed and reopened the
1240 * adapter. Unless we reset the device address field
1241 * now, we'll continue to use the existing modified
1242 * address.
1243 */
1247 /* Clear local unicast/multicast address tables and counts */
1254 /* Disable promiscuous filter settings */
1261 /* Reset and initialize adapter */
1265 {
1269 }
1271 /* Set device structure info */
1274 }
1276 \f
1277 /*
1278 * =============
1279 * = dfx_close =
1280 * =============
1281 *
1282 * Overview:
1283 * Closes the device/module.
1284 *
1285 * Returns:
1286 * Condition code
1287 *
1288 * Arguments:
1289 * dev - pointer to device information
1290 *
1291 * Functional Description:
1292 * This routine closes the adapter and brings it to a safe state.
1293 * The interrupt service routine is deregistered with the OS.
1294 * The adapter can be opened again with another call to dfx_open().
1295 *
1296 * Return Codes:
1297 * Always return 0.
1298 *
1299 * Assumptions:
1300 * No further requests for this adapter are made after this routine is
1301 * called. dfx_open() can be called to reset and reinitialize the
1302 * adapter.
1303 *
1304 * Side Effects:
1305 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1306 * routine.
1307 */
1310 {
1315 /* Disable PDQ interrupts first */
1319 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1323 /*
1324 * Flush any pending transmit buffers
1325 *
1326 * Note: It's important that we flush the transmit buffers
1327 * BEFORE we clear our copy of the Type 2 register.
1328 * Otherwise, we'll have no idea how many buffers
1329 * we need to free.
1330 */
1334 /*
1335 * Clear Type 1 and Type 2 registers after adapter reset
1336 *
1337 * Note: Even though we're closing the adapter, it's
1338 * possible that an interrupt will occur after
1339 * dfx_close is called. Without some assurance to
1340 * the contrary we want to make sure that we don't
1341 * process receive and transmit LLC frames and update
1342 * the Type 2 register with bad information.
1343 */
1349 /* Clear consumer block for the same reason given above */
1353 /* Release all dynamically allocate skb in the receive ring. */
1357 /* Clear device structure flags */
1361 /* Deregister (free) IRQ */
1366 }
1368 \f
1369 /*
1370 * ======================
1371 * = dfx_int_pr_halt_id =
1372 * ======================
1373 *
1374 * Overview:
1375 * Displays halt id's in string form.
1376 *
1377 * Returns:
1378 * None
1379 *
1380 * Arguments:
1381 * bp - pointer to board information
1382 *
1383 * Functional Description:
1384 * Determine current halt id and display appropriate string.
1385 *
1386 * Return Codes:
1387 * None
1388 *
1389 * Assumptions:
1390 * None
1391 *
1392 * Side Effects:
1393 * None
1394 */
1397 {
1401 /* Read the latest port status */
1405 /* Display halt state transition information */
1409 {
1449 }
1450 }
1452 \f
1453 /*
1454 * ==========================
1455 * = dfx_int_type_0_process =
1456 * ==========================
1457 *
1458 * Overview:
1459 * Processes Type 0 interrupts.
1460 *
1461 * Returns:
1462 * None
1463 *
1464 * Arguments:
1465 * bp - pointer to board information
1466 *
1467 * Functional Description:
1468 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1469 * is a serious fault on the adapter, then an error message is displayed
1470 * and the adapter is reset.
1471 *
1472 * One tricky potential timing window is the rapid succession of "link avail"
1473 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1474 * interrupt must be done before reading the state from the Port Status
1475 * register. This is true because a state change could occur after reading
1476 * the data, but before acknowledging the interrupt. If this state change
1477 * does happen, it would be lost because the driver is using the old state,
1478 * and it will never know about the new state because it subsequently
1479 * acknowledges the state change interrupt.
1480 *
1481 * INCORRECT CORRECT
1482 * read type 0 int reasons read type 0 int reasons
1483 * read adapter state ack type 0 interrupts
1484 * ack type 0 interrupts read adapter state
1485 * ... process interrupt ... ... process interrupt ...
1486 *
1487 * Return Codes:
1488 * None
1489 *
1490 * Assumptions:
1491 * None
1492 *
1493 * Side Effects:
1494 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1495 * or if the port status indicates that the adapter is halted. The driver
1496 * is responsible for reinitializing the adapter with the current CAM
1497 * contents and adapter filter settings.
1498 */
1502 {
1506 /*
1507 * Read host interrupt Type 0 register to determine which Type 0
1508 * interrupts are pending. Immediately write it back out to clear
1509 * those interrupts.
1510 */
1515 /* Check for Type 0 error interrupts */
1518 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1519 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1520 {
1521 /* Check for Non-Existent Memory error */
1526 /* Check for Packet Memory Parity error */
1531 /* Check for Host Bus Parity error */
1536 /* Reset adapter and bring it back on-line */
1542 {
1546 }
1549 }
1551 /* Check for transmit flush interrupt */
1554 {
1555 /* Flush any pending xmt's and acknowledge the flush interrupt */
1560 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1563 NULL);
1564 }
1566 /* Check for adapter state change */
1569 {
1570 /* Get latest adapter state */
1574 {
1575 /*
1576 * Adapter has transitioned to HALTED state, try to reset
1577 * adapter to bring it back on-line. If reset fails,
1578 * leave the adapter in the broken state.
1579 */
1584 /* Reset adapter and bring it back on-line */
1590 {
1594 }
1596 }
1598 {
1600 }
1601 }
1602 }
1604 \f
1605 /*
1606 * ==================
1607 * = dfx_int_common =
1608 * ==================
1609 *
1610 * Overview:
1611 * Interrupt service routine (ISR)
1612 *
1613 * Returns:
1614 * None
1615 *
1616 * Arguments:
1617 * bp - pointer to board information
1618 *
1619 * Functional Description:
1620 * This is the ISR which processes incoming adapter interrupts.
1621 *
1622 * Return Codes:
1623 * None
1624 *
1625 * Assumptions:
1626 * This routine assumes PDQ interrupts have not been disabled.
1627 * When interrupts are disabled at the PDQ, the Port Status register
1628 * is automatically cleared. This routine uses the Port Status
1629 * register value to determine whether a Type 0 interrupt occurred,
1630 * so it's important that adapter interrupts are not normally
1631 * enabled/disabled at the PDQ.
1632 *
1633 * It's vital that this routine is NOT reentered for the
1634 * same board and that the OS is not in another section of
1635 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1636 * different thread.
1637 *
1638 * Side Effects:
1639 * Pending interrupts are serviced. Depending on the type of
1640 * interrupt, acknowledging and clearing the interrupt at the
1641 * PDQ involves writing a register to clear the interrupt bit
1642 * or updating completion indices.
1643 */
1646 {
1650 /* Process xmt interrupts - frequent case, so always call this routine */
1655 /* Process rcv interrupts - frequent case, so always call this routine */
1659 /*
1660 * Transmit and receive producer and completion indices are updated on the
1661 * adapter by writing to the Type 2 Producer register. Since the frequent
1662 * case is that we'll be processing either LLC transmit or receive buffers,
1663 * we'll optimize I/O writes by doing a single register write here.
1664 */
1668 /* Read PDQ Port Status register to find out which interrupts need processing */
1672 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1676 }
1678 \f
1679 /*
1680 * =================
1681 * = dfx_interrupt =
1682 * =================
1683 *
1684 * Overview:
1685 * Interrupt processing routine
1686 *
1687 * Returns:
1688 * None
1689 *
1690 * Arguments:
1691 * irq - interrupt vector
1692 * dev_id - pointer to device information
1693 * regs - pointer to registers structure
1694 *
1695 * Functional Description:
1696 * This routine calls the interrupt processing routine for this adapter. It
1697 * disables and reenables adapter interrupts, as appropriate. We can support
1698 * shared interrupts since the incoming dev_id pointer provides our device
1699 * structure context.
1700 *
1701 * Return Codes:
1702 * None
1703 *
1704 * Assumptions:
1705 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1706 * on Intel-based systems) is done by the operating system outside this
1707 * routine.
1708 *
1709 * System interrupts are enabled through this call.
1710 *
1711 * Side Effects:
1712 * Interrupts are disabled, then reenabled at the adapter.
1713 */
1716 {
1721 /* Get board pointer only if device structure is valid */
1727 /* See if we're already servicing an interrupt */
1729 /* Service adapter interrupts */
1732 {
1733 /* Disable PDQ-PFI interrupts at PFI */
1737 /* Call interrupt service routine for this adapter */
1741 /* Clear PDQ interrupt status bit and reenable interrupts */
1746 }
1747 else
1748 {
1749 /* Disable interrupts at the ESIC */
1755 /* Call interrupt service routine for this adapter */
1759 /* Reenable interrupts at the ESIC */
1764 }
1767 }
1769 \f
1770 /*
1771 * =====================
1772 * = dfx_ctl_get_stats =
1773 * =====================
1774 *
1775 * Overview:
1776 * Get statistics for FDDI adapter
1777 *
1778 * Returns:
1779 * Pointer to FDDI statistics structure
1780 *
1781 * Arguments:
1782 * dev - pointer to device information
1783 *
1784 * Functional Description:
1785 * Gets current MIB objects from adapter, then
1786 * returns FDDI statistics structure as defined
1787 * in if_fddi.h.
1788 *
1789 * Note: Since the FDDI statistics structure is
1790 * still new and the device structure doesn't
1791 * have an FDDI-specific get statistics handler,
1792 * we'll return the FDDI statistics structure as
1793 * a pointer to an Ethernet statistics structure.
1794 * That way, at least the first part of the statistics
1795 * structure can be decoded properly, and it allows
1796 * "smart" applications to perform a second cast to
1797 * decode the FDDI-specific statistics.
1798 *
1799 * We'll have to pay attention to this routine as the
1800 * device structure becomes more mature and LAN media
1801 * independent.
1802 *
1803 * Return Codes:
1804 * None
1805 *
1806 * Assumptions:
1807 * None
1808 *
1809 * Side Effects:
1810 * None
1811 */
1814 {
1817 /* Fill the bp->stats structure with driver-maintained counters */
1832 /* Get FDDI SMT MIB objects */
1838 /* Fill the bp->stats structure with the SMT MIB object values */
1840 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1844 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1859 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1863 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1864 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1869 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1870 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1871 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1872 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1876 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1893 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1898 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1899 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1904 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1905 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1912 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1913 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1933 /* Get FDDI counters */
1939 /* Fill the bp->stats structure with the FDDI counter values */
1954 }
1956 \f
1957 /*
1958 * ==============================
1959 * = dfx_ctl_set_multicast_list =
1960 * ==============================
1961 *
1962 * Overview:
1963 * Enable/Disable LLC frame promiscuous mode reception
1964 * on the adapter and/or update multicast address table.
1965 *
1966 * Returns:
1967 * None
1968 *
1969 * Arguments:
1970 * dev - pointer to device information
1971 *
1972 * Functional Description:
1973 * This routine follows a fairly simple algorithm for setting the
1974 * adapter filters and CAM:
1975 *
1976 * if IFF_PROMISC flag is set
1977 * enable LLC individual/group promiscuous mode
1978 * else
1979 * disable LLC individual/group promiscuous mode
1980 * if number of incoming multicast addresses >
1981 * (CAM max size - number of unicast addresses in CAM)
1982 * enable LLC group promiscuous mode
1983 * set driver-maintained multicast address count to zero
1984 * else
1985 * disable LLC group promiscuous mode
1986 * set driver-maintained multicast address count to incoming count
1987 * update adapter CAM
1988 * update adapter filters
1989 *
1990 * Return Codes:
1991 * None
1992 *
1993 * Assumptions:
1994 * Multicast addresses are presented in canonical (LSB) format.
1995 *
1996 * Side Effects:
1997 * On-board adapter CAM and filters are updated.
1998 */
2001 {
2006 /* Enable LLC frame promiscuous mode, if necessary */
2011 /* Else, update multicast address table */
2013 else
2014 {
2016 /*
2017 * Check whether incoming multicast address count exceeds table size
2018 *
2019 * Note: The adapters utilize an on-board 64 entry CAM for
2020 * supporting perfect filtering of multicast packets
2021 * and bridge functions when adding unicast addresses.
2022 * There is no hash function available. To support
2023 * additional multicast addresses, the all multicast
2024 * filter (LLC group promiscuous mode) must be enabled.
2025 *
2026 * The firmware reserves two CAM entries for SMT-related
2027 * multicast addresses, which leaves 62 entries available.
2028 * The following code ensures that we're not being asked
2029 * to add more than 62 addresses to the CAM. If we are,
2030 * the driver will enable the all multicast filter.
2031 * Should the number of multicast addresses drop below
2032 * the high water mark, the filter will be disabled and
2033 * perfect filtering will be used.
2034 */
2037 {
2040 }
2041 else
2042 {
2045 }
2047 /* Copy addresses to multicast address table, then update adapter CAM */
2051 {
2054 }
2056 {
2058 }
2059 else
2060 {
2061 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2062 }
2063 }
2065 /* Update adapter filters */
2068 {
2070 }
2071 else
2072 {
2074 }
2075 }
2077 \f
2078 /*
2079 * ===========================
2080 * = dfx_ctl_set_mac_address =
2081 * ===========================
2082 *
2083 * Overview:
2084 * Add node address override (unicast address) to adapter
2085 * CAM and update dev_addr field in device table.
2086 *
2087 * Returns:
2088 * None
2089 *
2090 * Arguments:
2091 * dev - pointer to device information
2092 * addr - pointer to sockaddr structure containing unicast address to add
2093 *
2094 * Functional Description:
2095 * The adapter supports node address overrides by adding one or more
2096 * unicast addresses to the adapter CAM. This is similar to adding
2097 * multicast addresses. In this routine we'll update the driver and
2098 * device structures with the new address, then update the adapter CAM
2099 * to ensure that the adapter will copy and strip frames destined and
2100 * sourced by that address.
2101 *
2102 * Return Codes:
2103 * Always returns zero.
2104 *
2105 * Assumptions:
2106 * The address pointed to by addr->sa_data is a valid unicast
2107 * address and is presented in canonical (LSB) format.
2108 *
2109 * Side Effects:
2110 * On-board adapter CAM is updated. On-board adapter filters
2111 * may be updated.
2112 */
2115 {
2119 /* Copy unicast address to driver-maintained structs and update count */
2125 /*
2126 * Verify we're not exceeding the CAM size by adding unicast address
2127 *
2128 * Note: It's possible that before entering this routine we've
2129 * already filled the CAM with 62 multicast addresses.
2130 * Since we need to place the node address override into
2131 * the CAM, we have to check to see that we're not
2132 * exceeding the CAM size. If we are, we have to enable
2133 * the LLC group (multicast) promiscuous mode filter as
2134 * in dfx_ctl_set_multicast_list.
2135 */
2138 {
2142 /* Update adapter filters */
2145 {
2147 }
2148 else
2149 {
2151 }
2152 }
2154 /* Update adapter CAM with new unicast address */
2157 {
2159 }
2160 else
2161 {
2163 }
2165 }
2167 \f
2168 /*
2169 * ======================
2170 * = dfx_ctl_update_cam =
2171 * ======================
2172 *
2173 * Overview:
2174 * Procedure to update adapter CAM (Content Addressable Memory)
2175 * with desired unicast and multicast address entries.
2176 *
2177 * Returns:
2178 * Condition code
2179 *
2180 * Arguments:
2181 * bp - pointer to board information
2182 *
2183 * Functional Description:
2184 * Updates adapter CAM with current contents of board structure
2185 * unicast and multicast address tables. Since there are only 62
2186 * free entries in CAM, this routine ensures that the command
2187 * request buffer is not overrun.
2188 *
2189 * Return Codes:
2190 * DFX_K_SUCCESS - Request succeeded
2191 * DFX_K_FAILURE - Request failed
2192 *
2193 * Assumptions:
2194 * All addresses being added (unicast and multicast) are in canonical
2195 * order.
2196 *
2197 * Side Effects:
2198 * On-board adapter CAM is updated.
2199 */
2202 {
2206 /*
2207 * Fill in command request information
2208 *
2209 * Note: Even though both the unicast and multicast address
2210 * table entries are stored as contiguous 6 byte entries,
2211 * the firmware address filter set command expects each
2212 * entry to be two longwords (8 bytes total). We must be
2213 * careful to only copy the six bytes of each unicast and
2214 * multicast table entry into each command entry. This
2215 * is also why we must first clear the entire command
2216 * request buffer.
2217 */
2223 /* Now add unicast addresses to command request buffer, if any */
2226 {
2228 {
2231 }
2232 }
2234 /* Now add multicast addresses to command request buffer, if any */
2237 {
2239 {
2242 }
2243 }
2245 /* Issue command to update adapter CAM, then return */
2250 }
2252 \f
2253 /*
2254 * ==========================
2255 * = dfx_ctl_update_filters =
2256 * ==========================
2257 *
2258 * Overview:
2259 * Procedure to update adapter filters with desired
2260 * filter settings.
2261 *
2262 * Returns:
2263 * Condition code
2264 *
2265 * Arguments:
2266 * bp - pointer to board information
2267 *
2268 * Functional Description:
2269 * Enables or disables filter using current filter settings.
2270 *
2271 * Return Codes:
2272 * DFX_K_SUCCESS - Request succeeded.
2273 * DFX_K_FAILURE - Request failed.
2274 *
2275 * Assumptions:
2276 * We must always pass up packets destined to the broadcast
2277 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2278 * broadcast filter enabled.
2279 *
2280 * Side Effects:
2281 * On-board adapter filters are updated.
2282 */
2285 {
2288 /* Fill in command request information */
2292 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2297 /* Initialize LLC Individual/Group Promiscuous filter */
2302 /* Initialize LLC Group Promiscuous filter */
2307 /* Terminate the item code list */
2311 /* Issue command to update adapter filters, then return */
2316 }
2318 \f
2319 /*
2320 * ======================
2321 * = dfx_hw_dma_cmd_req =
2322 * ======================
2323 *
2324 * Overview:
2325 * Sends PDQ DMA command to adapter firmware
2326 *
2327 * Returns:
2328 * Condition code
2329 *
2330 * Arguments:
2331 * bp - pointer to board information
2332 *
2333 * Functional Description:
2334 * The command request and response buffers are posted to the adapter in the manner
2335 * described in the PDQ Port Specification:
2336 *
2337 * 1. Command Response Buffer is posted to adapter.
2338 * 2. Command Request Buffer is posted to adapter.
2339 * 3. Command Request consumer index is polled until it indicates that request
2340 * buffer has been DMA'd to adapter.
2341 * 4. Command Response consumer index is polled until it indicates that response
2342 * buffer has been DMA'd from adapter.
2343 *
2344 * This ordering ensures that a response buffer is already available for the firmware
2345 * to use once it's done processing the request buffer.
2346 *
2347 * Return Codes:
2348 * DFX_K_SUCCESS - DMA command succeeded
2349 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2350 * DFX_K_HW_TIMEOUT - DMA command timed out
2351 *
2352 * Assumptions:
2353 * Command request buffer has already been filled with desired DMA command.
2354 *
2355 * Side Effects:
2356 * None
2357 */
2360 {
2364 /* Make sure the adapter is in a state that we can issue the DMA command in */
2373 /* Put response buffer on the command response queue */
2379 /* Bump (and wrap) the producer index and write out to register */
2385 /* Put request buffer on the command request queue */
2391 /* Bump (and wrap) the producer index and write out to register */
2397 /*
2398 * Here we wait for the command request consumer index to be equal
2399 * to the producer, indicating that the adapter has DMAed the request.
2400 */
2403 {
2407 }
2411 /* Bump (and wrap) the completion index and write out to register */
2417 /*
2418 * Here we wait for the command response consumer index to be equal
2419 * to the producer, indicating that the adapter has DMAed the response.
2420 */
2423 {
2427 }
2431 /* Bump (and wrap) the completion index and write out to register */
2437 }
2439 \f
2440 /*
2441 * ========================
2442 * = dfx_hw_port_ctrl_req =
2443 * ========================
2444 *
2445 * Overview:
2446 * Sends PDQ port control command to adapter firmware
2447 *
2448 * Returns:
2449 * Host data register value in host_data if ptr is not NULL
2450 *
2451 * Arguments:
2452 * bp - pointer to board information
2453 * command - port control command
2454 * data_a - port data A register value
2455 * data_b - port data B register value
2456 * host_data - ptr to host data register value
2457 *
2458 * Functional Description:
2459 * Send generic port control command to adapter by writing
2460 * to various PDQ port registers, then polling for completion.
2461 *
2462 * Return Codes:
2463 * DFX_K_SUCCESS - port control command succeeded
2464 * DFX_K_HW_TIMEOUT - port control command timed out
2465 *
2466 * Assumptions:
2467 * None
2468 *
2469 * Side Effects:
2470 * None
2471 */
2475 PI_UINT32 command,
2476 PI_UINT32 data_a,
2477 PI_UINT32 data_b,
2478 PI_UINT32 *host_data
2479 )
2481 {
2485 /* Set Command Error bit in command longword */
2489 /* Issue port command to the adapter */
2495 /* Now wait for command to complete */
2499 else
2503 {
2508 }
2512 /*
2513 * If the address of host_data is non-zero, assume caller has supplied a
2514 * non NULL pointer, and return the contents of the HOST_DATA register in
2515 * it.
2516 */
2521 }
2523 \f
2524 /*
2525 * =====================
2526 * = dfx_hw_adap_reset =
2527 * =====================
2528 *
2529 * Overview:
2530 * Resets adapter
2531 *
2532 * Returns:
2533 * None
2534 *
2535 * Arguments:
2536 * bp - pointer to board information
2537 * type - type of reset to perform
2538 *
2539 * Functional Description:
2540 * Issue soft reset to adapter by writing to PDQ Port Reset
2541 * register. Use incoming reset type to tell adapter what
2542 * kind of reset operation to perform.
2543 *
2544 * Return Codes:
2545 * None
2546 *
2547 * Assumptions:
2548 * This routine merely issues a soft reset to the adapter.
2549 * It is expected that after this routine returns, the caller
2550 * will appropriately poll the Port Status register for the
2551 * adapter to enter the proper state.
2552 *
2553 * Side Effects:
2554 * Internal adapter registers are cleared.
2555 */
2559 PI_UINT32 type
2560 )
2562 {
2563 /* Set Reset type and assert reset */
2568 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2572 /* Deassert reset */
2575 }
2577 \f
2578 /*
2579 * ========================
2580 * = dfx_hw_adap_state_rd =
2581 * ========================
2582 *
2583 * Overview:
2584 * Returns current adapter state
2585 *
2586 * Returns:
2587 * Adapter state per PDQ Port Specification
2588 *
2589 * Arguments:
2590 * bp - pointer to board information
2591 *
2592 * Functional Description:
2593 * Reads PDQ Port Status register and returns adapter state.
2594 *
2595 * Return Codes:
2596 * None
2597 *
2598 * Assumptions:
2599 * None
2600 *
2601 * Side Effects:
2602 * None
2603 */
2606 {
2611 }
2613 \f
2614 /*
2615 * =====================
2616 * = dfx_hw_dma_uninit =
2617 * =====================
2618 *
2619 * Overview:
2620 * Brings adapter to DMA_UNAVAILABLE state
2621 *
2622 * Returns:
2623 * Condition code
2624 *
2625 * Arguments:
2626 * bp - pointer to board information
2627 * type - type of reset to perform
2628 *
2629 * Functional Description:
2630 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2631 * 1. Set reset type bit in Port Data A Register then reset adapter.
2632 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2633 *
2634 * Return Codes:
2635 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2636 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2637 *
2638 * Assumptions:
2639 * None
2640 *
2641 * Side Effects:
2642 * Internal adapter registers are cleared.
2643 */
2646 {
2649 /* Set reset type bit and reset adapter */
2653 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2656 {
2660 }
2664 }
2665 \f
2666 /*
2667 * Align an sk_buff to a boundary power of 2
2668 *
2669 */
2672 {
2679 }
2681 \f
2682 /*
2683 * ================
2684 * = dfx_rcv_init =
2685 * ================
2686 *
2687 * Overview:
2688 * Produces buffers to adapter LLC Host receive descriptor block
2689 *
2690 * Returns:
2691 * None
2692 *
2693 * Arguments:
2694 * bp - pointer to board information
2695 * get_buffers - non-zero if buffers to be allocated
2696 *
2697 * Functional Description:
2698 * This routine can be called during dfx_adap_init() or during an adapter
2699 * reset. It initializes the descriptor block and produces all allocated
2700 * LLC Host queue receive buffers.
2701 *
2702 * Return Codes:
2703 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2704 * dynamic buffer allocation). If the buffer allocation failed, the
2705 * already allocated buffers will not be released and the caller should do
2706 * this.
2707 *
2708 * Assumptions:
2709 * The PDQ has been reset and the adapter and driver maintained Type 2
2710 * register indices are cleared.
2711 *
2712 * Side Effects:
2713 * Receive buffers are posted to the adapter LLC queue and the adapter
2714 * is notified.
2715 */
2718 {
2721 /*
2722 * Since each receive buffer is a single fragment of same length, initialize
2723 * first longword in each receive descriptor for entire LLC Host descriptor
2724 * block. Also initialize second longword in each receive descriptor with
2725 * physical address of receive buffer. We'll always allocate receive
2726 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2727 * block and produce new receive buffers by simply updating the receive
2728 * producer index.
2729 *
2730 * Assumptions:
2731 * To support all shipping versions of PDQ, the receive buffer size
2732 * must be mod 128 in length and the physical address must be 128 byte
2733 * aligned. In other words, bits 0-6 of the length and address must
2734 * be zero for the following descriptor field entries to be correct on
2735 * all PDQ-based boards. We guaranteed both requirements during
2736 * driver initialization when we allocated memory for the receive buffers.
2737 */
2740 #ifdef DYNAMIC_BUFFERS
2743 {
2749 /*
2750 * align to 128 bytes for compatibility with
2751 * the old EISA boards.
2752 */
2757 NEW_SKB_SIZE,
2758 PCI_DMA_FROMDEVICE);
2759 /*
2760 * p_rcv_buff_va is only used inside the
2761 * kernel so we put the skb pointer here.
2762 */
2764 }
2765 #else
2768 {
2771 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2773 }
2774 #endif
2775 }
2777 /* Update receive producer and Type 2 register */
2782 }
2784 \f
2785 /*
2786 * =========================
2787 * = dfx_rcv_queue_process =
2788 * =========================
2789 *
2790 * Overview:
2791 * Process received LLC frames.
2792 *
2793 * Returns:
2794 * None
2795 *
2796 * Arguments:
2797 * bp - pointer to board information
2798 *
2799 * Functional Description:
2800 * Received LLC frames are processed until there are no more consumed frames.
2801 * Once all frames are processed, the receive buffers are returned to the
2802 * adapter. Note that this algorithm fixes the length of time that can be spent
2803 * in this routine, because there are a fixed number of receive buffers to
2804 * process and buffers are not produced until this routine exits and returns
2805 * to the ISR.
2806 *
2807 * Return Codes:
2808 * None
2809 *
2810 * Assumptions:
2811 * None
2812 *
2813 * Side Effects:
2814 * None
2815 */
2818 DFX_board_t *bp
2819 )
2821 {
2827 /* Service all consumed LLC receive frames */
2831 {
2832 /* Process any errors */
2837 #ifdef DYNAMIC_BUFFERS
2839 #else
2841 #endif
2845 {
2848 else
2850 }
2851 else
2852 {
2855 /* The frame was received without errors - verify packet length */
2862 #ifdef DYNAMIC_BUFFERS
2874 NEW_SKB_SIZE,
2875 PCI_DMA_FROMDEVICE);
2881 NEW_SKB_SIZE,
2882 PCI_DMA_FROMDEVICE);
2886 #endif
2889 {
2893 }
2895 #ifndef DYNAMIC_BUFFERS
2897 #endif
2898 {
2899 /* Receive buffer allocated, pass receive packet up */
2902 }
2912 /* Update the rcv counters */
2917 }
2918 }
2919 }
2921 /*
2922 * Advance the producer (for recycling) and advance the completion
2923 * (for servicing received frames). Note that it is okay to
2924 * advance the producer without checking that it passes the
2925 * completion index because they are both advanced at the same
2926 * rate.
2927 */
2931 }
2932 }
2934 \f
2935 /*
2936 * =====================
2937 * = dfx_xmt_queue_pkt =
2938 * =====================
2939 *
2940 * Overview:
2941 * Queues packets for transmission
2942 *
2943 * Returns:
2944 * Condition code
2945 *
2946 * Arguments:
2947 * skb - pointer to sk_buff to queue for transmission
2948 * dev - pointer to device information
2949 *
2950 * Functional Description:
2951 * Here we assume that an incoming skb transmit request
2952 * is contained in a single physically contiguous buffer
2953 * in which the virtual address of the start of packet
2954 * (skb->data) can be converted to a physical address
2955 * by using pci_map_single().
2956 *
2957 * Since the adapter architecture requires a three byte
2958 * packet request header to prepend the start of packet,
2959 * we'll write the three byte field immediately prior to
2960 * the FC byte. This assumption is valid because we've
2961 * ensured that dev->hard_header_len includes three pad
2962 * bytes. By posting a single fragment to the adapter,
2963 * we'll reduce the number of descriptor fetches and
2964 * bus traffic needed to send the request.
2965 *
2966 * Also, we can't free the skb until after it's been DMA'd
2967 * out by the adapter, so we'll queue it in the driver and
2968 * return it in dfx_xmt_done.
2969 *
2970 * Return Codes:
2971 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2972 * 1 - caller should requeue the sk_buff for later transmission
2973 *
2974 * Assumptions:
2975 * First and foremost, we assume the incoming skb pointer
2976 * is NOT NULL and is pointing to a valid sk_buff structure.
2977 *
2978 * The outgoing packet is complete, starting with the
2979 * frame control byte including the last byte of data,
2980 * but NOT including the 4 byte CRC. We'll let the
2981 * adapter hardware generate and append the CRC.
2982 *
2983 * The entire packet is stored in one physically
2984 * contiguous buffer which is not cached and whose
2985 * 32-bit physical address can be determined.
2986 *
2987 * It's vital that this routine is NOT reentered for the
2988 * same board and that the OS is not in another section of
2989 * code (eg. dfx_int_common) for the same board on a
2990 * different thread.
2991 *
2992 * Side Effects:
2993 * None
2994 */
2999 )
3001 {
3010 /*
3011 * Verify that incoming transmit request is OK
3012 *
3013 * Note: The packet size check is consistent with other
3014 * Linux device drivers, although the correct packet
3015 * size should be verified before calling the
3016 * transmit routine.
3017 */
3020 {
3027 }
3028 /*
3029 * See if adapter link is available, if not, free buffer
3030 *
3031 * Note: If the link isn't available, free buffer and return 0
3032 * rather than tell the upper layer to requeue the packet.
3033 * The methodology here is that by the time the link
3034 * becomes available, the packet to be sent will be
3035 * fairly stale. By simply dropping the packet, the
3036 * higher layer protocols will eventually time out
3037 * waiting for response packets which it won't receive.
3038 */
3041 {
3044 else
3045 {
3050 }
3051 }
3055 /* Get the current producer and the next free xmt data descriptor */
3060 /*
3061 * Get pointer to auxiliary queue entry to contain information
3062 * for this packet.
3063 *
3064 * Note: The current xmt producer index will become the
3065 * current xmt completion index when we complete this
3066 * packet later on. So, we'll get the pointer to the
3067 * next auxiliary queue entry now before we bump the
3068 * producer index.
3069 */
3073 /* Write the three PRH bytes immediately before the FC byte */
3080 /*
3081 * Write the descriptor with buffer info and bump producer
3082 *
3083 * Note: Since we need to start DMA from the packet request
3084 * header, we'll add 3 bytes to the DMA buffer length,
3085 * and we'll determine the physical address of the
3086 * buffer from the PRH, not skb->data.
3087 *
3088 * Assumptions:
3089 * 1. Packet starts with the frame control (FC) byte
3090 * at skb->data.
3091 * 2. The 4-byte CRC is not appended to the buffer or
3092 * included in the length.
3093 * 3. Packet length (skb->len) is from FC to end of
3094 * data, inclusive.
3095 * 4. The packet length does not exceed the maximum
3096 * FDDI LLC frame length of 4491 bytes.
3097 * 5. The entire packet is contained in a physically
3098 * contiguous, non-cached, locked memory space
3099 * comprised of a single buffer pointed to by
3100 * skb->data.
3101 * 6. The physical address of the start of packet
3102 * can be determined from the virtual address
3103 * by using pci_map_single() and is only 32-bits
3104 * wide.
3105 */
3107 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3111 /*
3112 * Verify that descriptor is actually available
3113 *
3114 * Note: If descriptor isn't available, return 1 which tells
3115 * the upper layer to requeue the packet for later
3116 * transmission.
3117 *
3118 * We need to ensure that the producer never reaches the
3119 * completion, except to indicate that the queue is empty.
3120 */
3123 {
3127 }
3129 /*
3130 * Save info for this packet for xmt done indication routine
3131 *
3132 * Normally, we'd save the producer index in the p_xmt_drv_descr
3133 * structure so that we'd have it handy when we complete this
3134 * packet later (in dfx_xmt_done). However, since the current
3135 * transmit architecture guarantees a single fragment for the
3136 * entire packet, we can simply bump the completion index by
3137 * one (1) for each completed packet.
3138 *
3139 * Note: If this assumption changes and we're presented with
3140 * an inconsistent number of transmit fragments for packet
3141 * data, we'll need to modify this code to save the current
3142 * transmit producer index.
3143 */
3147 /* Update Type 2 register */
3154 }
3156 \f
3157 /*
3158 * ================
3159 * = dfx_xmt_done =
3160 * ================
3161 *
3162 * Overview:
3163 * Processes all frames that have been transmitted.
3164 *
3165 * Returns:
3166 * None
3167 *
3168 * Arguments:
3169 * bp - pointer to board information
3170 *
3171 * Functional Description:
3172 * For all consumed transmit descriptors that have not
3173 * yet been completed, we'll free the skb we were holding
3174 * onto using dev_kfree_skb and bump the appropriate
3175 * counters.
3176 *
3177 * Return Codes:
3178 * None
3179 *
3180 * Assumptions:
3181 * The Type 2 register is not updated in this routine. It is
3182 * assumed that it will be updated in the ISR when dfx_xmt_done
3183 * returns.
3184 *
3185 * Side Effects:
3186 * None
3187 */
3190 {
3196 /* Service all consumed transmit frames */
3200 {
3201 /* Get pointer to the transmit driver descriptor block information */
3205 /* Increment transmit counters */
3210 /* Return skb to operating system */
3215 PCI_DMA_TODEVICE);
3218 /*
3219 * Move to start of next packet by updating completion index
3220 *
3221 * Here we assume that a transmit packet request is always
3222 * serviced by posting one fragment. We can therefore
3223 * simplify the completion code by incrementing the
3224 * completion index by one. This code will need to be
3225 * modified if this assumption changes. See comments
3226 * in dfx_xmt_queue_pkt for more details.
3227 */
3230 freed++;
3231 }
3233 }
3235 \f
3236 /*
3237 * =================
3238 * = dfx_rcv_flush =
3239 * =================
3240 *
3241 * Overview:
3242 * Remove all skb's in the receive ring.
3243 *
3244 * Returns:
3245 * None
3246 *
3247 * Arguments:
3248 * bp - pointer to board information
3249 *
3250 * Functional Description:
3251 * Free's all the dynamically allocated skb's that are
3252 * currently attached to the device receive ring. This
3253 * function is typically only used when the device is
3254 * initialized or reinitialized.
3255 *
3256 * Return Codes:
3257 * None
3258 *
3259 * Side Effects:
3260 * None
3261 */
3262 #ifdef DYNAMIC_BUFFERS
3264 {
3269 {
3275 }
3277 }
3278 #else
3280 {
3281 }
3284 /*
3285 * =================
3286 * = dfx_xmt_flush =
3287 * =================
3288 *
3289 * Overview:
3290 * Processes all frames whether they've been transmitted
3291 * or not.
3292 *
3293 * Returns:
3294 * None
3295 *
3296 * Arguments:
3297 * bp - pointer to board information
3298 *
3299 * Functional Description:
3300 * For all produced transmit descriptors that have not
3301 * yet been completed, we'll free the skb we were holding
3302 * onto using dev_kfree_skb and bump the appropriate
3303 * counters. Of course, it's possible that some of
3304 * these transmit requests actually did go out, but we
3305 * won't make that distinction here. Finally, we'll
3306 * update the consumer index to match the producer.
3307 *
3308 * Return Codes:
3309 * None
3310 *
3311 * Assumptions:
3312 * This routine does NOT update the Type 2 register. It
3313 * is assumed that this routine is being called during a
3314 * transmit flush interrupt, or a shutdown or close routine.
3315 *
3316 * Side Effects:
3317 * None
3318 */
3321 {
3326 /* Flush all outstanding transmit frames */
3329 {
3330 /* Get pointer to the transmit driver descriptor block information */
3334 /* Return skb to operating system */
3339 PCI_DMA_TODEVICE);
3342 /* Increment transmit error counter */
3346 /*
3347 * Move to start of next packet by updating completion index
3348 *
3349 * Here we assume that a transmit packet request is always
3350 * serviced by posting one fragment. We can therefore
3351 * simplify the completion code by incrementing the
3352 * completion index by one. This code will need to be
3353 * modified if this assumption changes. See comments
3354 * in dfx_xmt_queue_pkt for more details.
3355 */
3358 }
3360 /* Update the transmit consumer index in the consumer block */
3365 }
3368 {
3377 #ifndef DYNAMIC_BUFFERS
3379 #endif
3386 }
3389 {
3394 }
3399 };
3407 };
3414 {
3418 {
3426 }
3427 }
3430 {
3440 }
3443 {
3449 }
3458 \f
3459 /*
3460 * Local variables:
3461 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
3462 * End:
3463 */