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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / net / e100.c
blob1b68dd5a49b6505ed133442273b910cf2898a3fc
1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
117 * placed.
118 *
119 * V. Miscellaneous
120 *
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
126 *
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
128 *
129 * Thanks to JC (jchapman@katalix.com) for helping with
130 * testing/troubleshooting the development driver.
131 *
132 * TODO:
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
135 */
136
137 #include <linux/config.h>
138 #include <linux/module.h>
139 #include <linux/moduleparam.h>
140 #include <linux/kernel.h>
141 #include <linux/types.h>
142 #include <linux/slab.h>
143 #include <linux/delay.h>
144 #include <linux/init.h>
145 #include <linux/pci.h>
146 #include <linux/netdevice.h>
147 #include <linux/etherdevice.h>
148 #include <linux/mii.h>
149 #include <linux/if_vlan.h>
150 #include <linux/skbuff.h>
151 #include <linux/ethtool.h>
152 #include <linux/string.h>
153 #include <asm/unaligned.h>
154
155
156 #define DRV_NAME "e100"
157 #define DRV_EXT "-NAPI"
158 #define DRV_VERSION "3.3.6-k2"DRV_EXT
159 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
160 #define DRV_COPYRIGHT "Copyright(c) 1999-2004 Intel Corporation"
161 #define PFX DRV_NAME ": "
162
163 #define E100_WATCHDOG_PERIOD (2 * HZ)
164 #define E100_NAPI_WEIGHT 16
165
166 MODULE_DESCRIPTION(DRV_DESCRIPTION);
167 MODULE_AUTHOR(DRV_COPYRIGHT);
168 MODULE_LICENSE("GPL");
169 MODULE_VERSION(DRV_VERSION);
170
171 static int debug = 3;
172 module_param(debug, int, 0);
173 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
174 #define DPRINTK(nlevel, klevel, fmt, args...) \
175 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
176 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
177 __FUNCTION__ , ## args))
178
179 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
180 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
181 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
182 static struct pci_device_id e100_id_table[] = {
183 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
184 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
185 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
186 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
191 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
197 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
205 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
206 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
215 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
216 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
217 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
218 { 0, }
219 };
220 MODULE_DEVICE_TABLE(pci, e100_id_table);
221
222 enum mac {
223 mac_82557_D100_A = 0,
224 mac_82557_D100_B = 1,
225 mac_82557_D100_C = 2,
226 mac_82558_D101_A4 = 4,
227 mac_82558_D101_B0 = 5,
228 mac_82559_D101M = 8,
229 mac_82559_D101S = 9,
230 mac_82550_D102 = 12,
231 mac_82550_D102_C = 13,
232 mac_82551_E = 14,
233 mac_82551_F = 15,
234 mac_82551_10 = 16,
235 mac_unknown = 0xFF,
236 };
237
238 enum phy {
239 phy_100a = 0x000003E0,
240 phy_100c = 0x035002A8,
241 phy_82555_tx = 0x015002A8,
242 phy_nsc_tx = 0x5C002000,
243 phy_82562_et = 0x033002A8,
244 phy_82562_em = 0x032002A8,
245 phy_82562_ek = 0x031002A8,
246 phy_82562_eh = 0x017002A8,
247 phy_unknown = 0xFFFFFFFF,
248 };
249
250 /* CSR (Control/Status Registers) */
251 struct csr {
252 struct {
253 u8 status;
254 u8 stat_ack;
255 u8 cmd_lo;
256 u8 cmd_hi;
257 u32 gen_ptr;
258 } scb;
259 u32 port;
260 u16 flash_ctrl;
261 u8 eeprom_ctrl_lo;
262 u8 eeprom_ctrl_hi;
263 u32 mdi_ctrl;
264 u32 rx_dma_count;
265 };
266
267 enum scb_status {
268 rus_ready = 0x10,
269 rus_mask = 0x3C,
270 };
271
272 enum scb_stat_ack {
273 stat_ack_not_ours = 0x00,
274 stat_ack_sw_gen = 0x04,
275 stat_ack_rnr = 0x10,
276 stat_ack_cu_idle = 0x20,
277 stat_ack_frame_rx = 0x40,
278 stat_ack_cu_cmd_done = 0x80,
279 stat_ack_not_present = 0xFF,
280 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
281 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
282 };
283
284 enum scb_cmd_hi {
285 irq_mask_none = 0x00,
286 irq_mask_all = 0x01,
287 irq_sw_gen = 0x02,
288 };
289
290 enum scb_cmd_lo {
291 cuc_nop = 0x00,
292 ruc_start = 0x01,
293 ruc_load_base = 0x06,
294 cuc_start = 0x10,
295 cuc_resume = 0x20,
296 cuc_dump_addr = 0x40,
297 cuc_dump_stats = 0x50,
298 cuc_load_base = 0x60,
299 cuc_dump_reset = 0x70,
300 };
301
302 enum cuc_dump {
303 cuc_dump_complete = 0x0000A005,
304 cuc_dump_reset_complete = 0x0000A007,
305 };
306
307 enum port {
308 software_reset = 0x0000,
309 selftest = 0x0001,
310 selective_reset = 0x0002,
311 };
312
313 enum eeprom_ctrl_lo {
314 eesk = 0x01,
315 eecs = 0x02,
316 eedi = 0x04,
317 eedo = 0x08,
318 };
319
320 enum mdi_ctrl {
321 mdi_write = 0x04000000,
322 mdi_read = 0x08000000,
323 mdi_ready = 0x10000000,
324 };
325
326 enum eeprom_op {
327 op_write = 0x05,
328 op_read = 0x06,
329 op_ewds = 0x10,
330 op_ewen = 0x13,
331 };
332
333 enum eeprom_offsets {
334 eeprom_cnfg_mdix = 0x03,
335 eeprom_id = 0x0A,
336 eeprom_config_asf = 0x0D,
337 eeprom_smbus_addr = 0x90,
338 };
339
340 enum eeprom_cnfg_mdix {
341 eeprom_mdix_enabled = 0x0080,
342 };
343
344 enum eeprom_id {
345 eeprom_id_wol = 0x0020,
346 };
347
348 enum eeprom_config_asf {
349 eeprom_asf = 0x8000,
350 eeprom_gcl = 0x4000,
351 };
352
353 enum cb_status {
354 cb_complete = 0x8000,
355 cb_ok = 0x2000,
356 };
357
358 enum cb_command {
359 cb_nop = 0x0000,
360 cb_iaaddr = 0x0001,
361 cb_config = 0x0002,
362 cb_multi = 0x0003,
363 cb_tx = 0x0004,
364 cb_ucode = 0x0005,
365 cb_dump = 0x0006,
366 cb_tx_sf = 0x0008,
367 cb_cid = 0x1f00,
368 cb_i = 0x2000,
369 cb_s = 0x4000,
370 cb_el = 0x8000,
371 };
372
373 struct rfd {
374 u16 status;
375 u16 command;
376 u32 link;
377 u32 rbd;
378 u16 actual_size;
379 u16 size;
380 };
381
382 struct rx {
383 struct rx *next, *prev;
384 struct sk_buff *skb;
385 dma_addr_t dma_addr;
386 };
387
388 #if defined(__BIG_ENDIAN_BITFIELD)
389 #define X(a,b) b,a
390 #else
391 #define X(a,b) a,b
392 #endif
393 struct config {
394 /*0*/ u8 X(byte_count:6, pad0:2);
395 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
396 /*2*/ u8 adaptive_ifs;
397 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
398 term_write_cache_line:1), pad3:4);
399 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
400 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
401 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
402 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
403 rx_discard_overruns:1), rx_save_bad_frames:1);
404 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
405 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
406 tx_dynamic_tbd:1);
407 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
408 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
409 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
410 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
411 loopback:2);
412 /*11*/ u8 X(linear_priority:3, pad11:5);
413 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
414 /*13*/ u8 ip_addr_lo;
415 /*14*/ u8 ip_addr_hi;
416 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
417 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
418 pad15_2:1), crs_or_cdt:1);
419 /*16*/ u8 fc_delay_lo;
420 /*17*/ u8 fc_delay_hi;
421 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
422 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
423 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
424 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
425 full_duplex_force:1), full_duplex_pin:1);
426 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
427 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
428 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
429 u8 pad_d102[9];
430 };
431
432 #define E100_MAX_MULTICAST_ADDRS 64
433 struct multi {
434 u16 count;
435 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
436 };
437
438 /* Important: keep total struct u32-aligned */
439 #define UCODE_SIZE 134
440 struct cb {
441 u16 status;
442 u16 command;
443 u32 link;
444 union {
445 u8 iaaddr[ETH_ALEN];
446 u32 ucode[UCODE_SIZE];
447 struct config config;
448 struct multi multi;
449 struct {
450 u32 tbd_array;
451 u16 tcb_byte_count;
452 u8 threshold;
453 u8 tbd_count;
454 struct {
455 u32 buf_addr;
456 u16 size;
457 u16 eol;
458 } tbd;
459 } tcb;
460 u32 dump_buffer_addr;
461 } u;
462 struct cb *next, *prev;
463 dma_addr_t dma_addr;
464 struct sk_buff *skb;
465 };
466
467 enum loopback {
468 lb_none = 0, lb_mac = 1, lb_phy = 3,
469 };
470
471 struct stats {
472 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
473 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
474 tx_multiple_collisions, tx_total_collisions;
475 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
476 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
477 rx_short_frame_errors;
478 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
479 u16 xmt_tco_frames, rcv_tco_frames;
480 u32 complete;
481 };
482
483 struct mem {
484 struct {
485 u32 signature;
486 u32 result;
487 } selftest;
488 struct stats stats;
489 u8 dump_buf[596];
490 };
491
492 struct param_range {
493 u32 min;
494 u32 max;
495 u32 count;
496 };
497
498 struct params {
499 struct param_range rfds;
500 struct param_range cbs;
501 };
502
503 struct nic {
504 /* Begin: frequently used values: keep adjacent for cache effect */
505 u32 msg_enable ____cacheline_aligned;
506 struct net_device *netdev;
507 struct pci_dev *pdev;
508
509 struct rx *rxs ____cacheline_aligned;
510 struct rx *rx_to_use;
511 struct rx *rx_to_clean;
512 struct rfd blank_rfd;
513 int ru_running;
514
515 spinlock_t cb_lock ____cacheline_aligned;
516 spinlock_t cmd_lock;
517 struct csr __iomem *csr;
518 enum scb_cmd_lo cuc_cmd;
519 unsigned int cbs_avail;
520 struct cb *cbs;
521 struct cb *cb_to_use;
522 struct cb *cb_to_send;
523 struct cb *cb_to_clean;
524 u16 tx_command;
525 /* End: frequently used values: keep adjacent for cache effect */
526
527 enum {
528 ich = (1 << 0),
529 promiscuous = (1 << 1),
530 multicast_all = (1 << 2),
531 wol_magic = (1 << 3),
532 ich_10h_workaround = (1 << 4),
533 } flags ____cacheline_aligned;
534
535 enum mac mac;
536 enum phy phy;
537 struct params params;
538 struct net_device_stats net_stats;
539 struct timer_list watchdog;
540 struct timer_list blink_timer;
541 struct mii_if_info mii;
542 enum loopback loopback;
543
544 struct mem *mem;
545 dma_addr_t dma_addr;
546
547 dma_addr_t cbs_dma_addr;
548 u8 adaptive_ifs;
549 u8 tx_threshold;
550 u32 tx_frames;
551 u32 tx_collisions;
552 u32 tx_deferred;
553 u32 tx_single_collisions;
554 u32 tx_multiple_collisions;
555 u32 tx_fc_pause;
556 u32 tx_tco_frames;
557
558 u32 rx_fc_pause;
559 u32 rx_fc_unsupported;
560 u32 rx_tco_frames;
561 u32 rx_over_length_errors;
562
563 u8 rev_id;
564 u16 leds;
565 u16 eeprom_wc;
566 u16 eeprom[256];
567 };
568
569 static inline void e100_write_flush(struct nic *nic)
570 {
571 /* Flush previous PCI writes through intermediate bridges
572 * by doing a benign read */
573 (void)readb(&nic->csr->scb.status);
574 }
575
576 static inline void e100_enable_irq(struct nic *nic)
577 {
578 unsigned long flags;
579
580 spin_lock_irqsave(&nic->cmd_lock, flags);
581 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
582 spin_unlock_irqrestore(&nic->cmd_lock, flags);
583 e100_write_flush(nic);
584 }
585
586 static inline void e100_disable_irq(struct nic *nic)
587 {
588 unsigned long flags;
589
590 spin_lock_irqsave(&nic->cmd_lock, flags);
591 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
592 spin_unlock_irqrestore(&nic->cmd_lock, flags);
593 e100_write_flush(nic);
594 }
595
596 static void e100_hw_reset(struct nic *nic)
597 {
598 /* Put CU and RU into idle with a selective reset to get
599 * device off of PCI bus */
600 writel(selective_reset, &nic->csr->port);
601 e100_write_flush(nic); udelay(20);
602
603 /* Now fully reset device */
604 writel(software_reset, &nic->csr->port);
605 e100_write_flush(nic); udelay(20);
606
607 /* Mask off our interrupt line - it's unmasked after reset */
608 e100_disable_irq(nic);
609 }
610
611 static int e100_self_test(struct nic *nic)
612 {
613 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
614
615 /* Passing the self-test is a pretty good indication
616 * that the device can DMA to/from host memory */
617
618 nic->mem->selftest.signature = 0;
619 nic->mem->selftest.result = 0xFFFFFFFF;
620
621 writel(selftest | dma_addr, &nic->csr->port);
622 e100_write_flush(nic);
623 /* Wait 10 msec for self-test to complete */
624 msleep(10);
625
626 /* Interrupts are enabled after self-test */
627 e100_disable_irq(nic);
628
629 /* Check results of self-test */
630 if(nic->mem->selftest.result != 0) {
631 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
632 nic->mem->selftest.result);
633 return -ETIMEDOUT;
634 }
635 if(nic->mem->selftest.signature == 0) {
636 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
637 return -ETIMEDOUT;
638 }
639
640 return 0;
641 }
642
643 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
644 {
645 u32 cmd_addr_data[3];
646 u8 ctrl;
647 int i, j;
648
649 /* Three cmds: write/erase enable, write data, write/erase disable */
650 cmd_addr_data[0] = op_ewen << (addr_len - 2);
651 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
652 cpu_to_le16(data);
653 cmd_addr_data[2] = op_ewds << (addr_len - 2);
654
655 /* Bit-bang cmds to write word to eeprom */
656 for(j = 0; j < 3; j++) {
657
658 /* Chip select */
659 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
660 e100_write_flush(nic); udelay(4);
661
662 for(i = 31; i >= 0; i--) {
663 ctrl = (cmd_addr_data[j] & (1 << i)) ?
664 eecs | eedi : eecs;
665 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
666 e100_write_flush(nic); udelay(4);
667
668 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
669 e100_write_flush(nic); udelay(4);
670 }
671 /* Wait 10 msec for cmd to complete */
672 msleep(10);
673
674 /* Chip deselect */
675 writeb(0, &nic->csr->eeprom_ctrl_lo);
676 e100_write_flush(nic); udelay(4);
677 }
678 };
679
680 /* General technique stolen from the eepro100 driver - very clever */
681 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
682 {
683 u32 cmd_addr_data;
684 u16 data = 0;
685 u8 ctrl;
686 int i;
687
688 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
689
690 /* Chip select */
691 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
692 e100_write_flush(nic); udelay(4);
693
694 /* Bit-bang to read word from eeprom */
695 for(i = 31; i >= 0; i--) {
696 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
697 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
698 e100_write_flush(nic); udelay(4);
699
700 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
701 e100_write_flush(nic); udelay(4);
702
703 /* Eeprom drives a dummy zero to EEDO after receiving
704 * complete address. Use this to adjust addr_len. */
705 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
706 if(!(ctrl & eedo) && i > 16) {
707 *addr_len -= (i - 16);
708 i = 17;
709 }
710
711 data = (data << 1) | (ctrl & eedo ? 1 : 0);
712 }
713
714 /* Chip deselect */
715 writeb(0, &nic->csr->eeprom_ctrl_lo);
716 e100_write_flush(nic); udelay(4);
717
718 return le16_to_cpu(data);
719 };
720
721 /* Load entire EEPROM image into driver cache and validate checksum */
722 static int e100_eeprom_load(struct nic *nic)
723 {
724 u16 addr, addr_len = 8, checksum = 0;
725
726 /* Try reading with an 8-bit addr len to discover actual addr len */
727 e100_eeprom_read(nic, &addr_len, 0);
728 nic->eeprom_wc = 1 << addr_len;
729
730 for(addr = 0; addr < nic->eeprom_wc; addr++) {
731 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
732 if(addr < nic->eeprom_wc - 1)
733 checksum += cpu_to_le16(nic->eeprom[addr]);
734 }
735
736 /* The checksum, stored in the last word, is calculated such that
737 * the sum of words should be 0xBABA */
738 checksum = le16_to_cpu(0xBABA - checksum);
739 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
740 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
741 return -EAGAIN;
742 }
743
744 return 0;
745 }
746
747 /* Save (portion of) driver EEPROM cache to device and update checksum */
748 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
749 {
750 u16 addr, addr_len = 8, checksum = 0;
751
752 /* Try reading with an 8-bit addr len to discover actual addr len */
753 e100_eeprom_read(nic, &addr_len, 0);
754 nic->eeprom_wc = 1 << addr_len;
755
756 if(start + count >= nic->eeprom_wc)
757 return -EINVAL;
758
759 for(addr = start; addr < start + count; addr++)
760 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
761
762 /* The checksum, stored in the last word, is calculated such that
763 * the sum of words should be 0xBABA */
764 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
765 checksum += cpu_to_le16(nic->eeprom[addr]);
766 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
767 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
768 nic->eeprom[nic->eeprom_wc - 1]);
769
770 return 0;
771 }
772
773 #define E100_WAIT_SCB_TIMEOUT 40
774 static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
775 {
776 unsigned long flags;
777 unsigned int i;
778 int err = 0;
779
780 spin_lock_irqsave(&nic->cmd_lock, flags);
781
782 /* Previous command is accepted when SCB clears */
783 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
784 if(likely(!readb(&nic->csr->scb.cmd_lo)))
785 break;
786 cpu_relax();
787 if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
788 udelay(5);
789 }
790 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
791 err = -EAGAIN;
792 goto err_unlock;
793 }
794
795 if(unlikely(cmd != cuc_resume))
796 writel(dma_addr, &nic->csr->scb.gen_ptr);
797 writeb(cmd, &nic->csr->scb.cmd_lo);
798
799 err_unlock:
800 spin_unlock_irqrestore(&nic->cmd_lock, flags);
801
802 return err;
803 }
804
805 static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
806 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
807 {
808 struct cb *cb;
809 unsigned long flags;
810 int err = 0;
811
812 spin_lock_irqsave(&nic->cb_lock, flags);
813
814 if(unlikely(!nic->cbs_avail)) {
815 err = -ENOMEM;
816 goto err_unlock;
817 }
818
819 cb = nic->cb_to_use;
820 nic->cb_to_use = cb->next;
821 nic->cbs_avail--;
822 cb->skb = skb;
823
824 if(unlikely(!nic->cbs_avail))
825 err = -ENOSPC;
826
827 cb_prepare(nic, cb, skb);
828
829 /* Order is important otherwise we'll be in a race with h/w:
830 * set S-bit in current first, then clear S-bit in previous. */
831 cb->command |= cpu_to_le16(cb_s);
832 wmb();
833 cb->prev->command &= cpu_to_le16(~cb_s);
834
835 while(nic->cb_to_send != nic->cb_to_use) {
836 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
837 nic->cb_to_send->dma_addr))) {
838 /* Ok, here's where things get sticky. It's
839 * possible that we can't schedule the command
840 * because the controller is too busy, so
841 * let's just queue the command and try again
842 * when another command is scheduled. */
843 break;
844 } else {
845 nic->cuc_cmd = cuc_resume;
846 nic->cb_to_send = nic->cb_to_send->next;
847 }
848 }
849
850 err_unlock:
851 spin_unlock_irqrestore(&nic->cb_lock, flags);
852
853 return err;
854 }
855
856 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
857 {
858 u32 data_out = 0;
859 unsigned int i;
860
861 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
862
863 for(i = 0; i < 100; i++) {
864 udelay(20);
865 if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
866 break;
867 }
868
869 DPRINTK(HW, DEBUG,
870 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
871 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
872 return (u16)data_out;
873 }
874
875 static int mdio_read(struct net_device *netdev, int addr, int reg)
876 {
877 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
878 }
879
880 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
881 {
882 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
883 }
884
885 static void e100_get_defaults(struct nic *nic)
886 {
887 struct param_range rfds = { .min = 64, .max = 256, .count = 64 };
888 struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
889
890 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
891 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
892 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
893 if(nic->mac == mac_unknown)
894 nic->mac = mac_82557_D100_A;
895
896 nic->params.rfds = rfds;
897 nic->params.cbs = cbs;
898
899 /* Quadwords to DMA into FIFO before starting frame transmit */
900 nic->tx_threshold = 0xE0;
901
902 nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf |
903 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0));
904
905 /* Template for a freshly allocated RFD */
906 nic->blank_rfd.command = cpu_to_le16(cb_el);
907 nic->blank_rfd.rbd = 0xFFFFFFFF;
908 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
909
910 /* MII setup */
911 nic->mii.phy_id_mask = 0x1F;
912 nic->mii.reg_num_mask = 0x1F;
913 nic->mii.dev = nic->netdev;
914 nic->mii.mdio_read = mdio_read;
915 nic->mii.mdio_write = mdio_write;
916 }
917
918 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
919 {
920 struct config *config = &cb->u.config;
921 u8 *c = (u8 *)config;
922
923 cb->command = cpu_to_le16(cb_config);
924
925 memset(config, 0, sizeof(struct config));
926
927 config->byte_count = 0x16; /* bytes in this struct */
928 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
929 config->direct_rx_dma = 0x1; /* reserved */
930 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
931 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
932 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
933 config->tx_underrun_retry = 0x3; /* # of underrun retries */
934 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
935 config->pad10 = 0x6;
936 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
937 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
938 config->ifs = 0x6; /* x16 = inter frame spacing */
939 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
940 config->pad15_1 = 0x1;
941 config->pad15_2 = 0x1;
942 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
943 config->fc_delay_hi = 0x40; /* time delay for fc frame */
944 config->tx_padding = 0x1; /* 1=pad short frames */
945 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
946 config->pad18 = 0x1;
947 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
948 config->pad20_1 = 0x1F;
949 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
950 config->pad21_1 = 0x5;
951
952 config->adaptive_ifs = nic->adaptive_ifs;
953 config->loopback = nic->loopback;
954
955 if(nic->mii.force_media && nic->mii.full_duplex)
956 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
957
958 if(nic->flags & promiscuous || nic->loopback) {
959 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
960 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
961 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
962 }
963
964 if(nic->flags & multicast_all)
965 config->multicast_all = 0x1; /* 1=accept, 0=no */
966
967 if(!(nic->flags & wol_magic))
968 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
969
970 if(nic->mac >= mac_82558_D101_A4) {
971 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
972 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
973 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
974 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
975 if(nic->mac >= mac_82559_D101M)
976 config->tno_intr = 0x1; /* TCO stats enable */
977 else
978 config->standard_stat_counter = 0x0;
979 }
980
981 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
982 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
983 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
984 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
985 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
986 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
987 }
988
989 static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
990 {
991 int i;
992 static const u32 ucode[UCODE_SIZE] = {
993 /* NFS packets are misinterpreted as TCO packets and
994 * incorrectly routed to the BMC over SMBus. This
995 * microcode patch checks the fragmented IP bit in the
996 * NFS/UDP header to distinguish between NFS and TCO. */
997 0x0EF70E36, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF,
998 0x1FFF1FFF, 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000,
999 0x00906EFD, 0x00900EFD, 0x00E00EF8,
1000 };
1001
1002 if(nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
1003 for(i = 0; i < UCODE_SIZE; i++)
1004 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1005 cb->command = cpu_to_le16(cb_ucode);
1006 } else
1007 cb->command = cpu_to_le16(cb_nop);
1008 }
1009
1010 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1011 struct sk_buff *skb)
1012 {
1013 cb->command = cpu_to_le16(cb_iaaddr);
1014 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1015 }
1016
1017 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1018 {
1019 cb->command = cpu_to_le16(cb_dump);
1020 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1021 offsetof(struct mem, dump_buf));
1022 }
1023
1024 #define NCONFIG_AUTO_SWITCH 0x0080
1025 #define MII_NSC_CONG MII_RESV1
1026 #define NSC_CONG_ENABLE 0x0100
1027 #define NSC_CONG_TXREADY 0x0400
1028 #define ADVERTISE_FC_SUPPORTED 0x0400
1029 static int e100_phy_init(struct nic *nic)
1030 {
1031 struct net_device *netdev = nic->netdev;
1032 u32 addr;
1033 u16 bmcr, stat, id_lo, id_hi, cong;
1034
1035 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1036 for(addr = 0; addr < 32; addr++) {
1037 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1038 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1039 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1040 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1041 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1042 break;
1043 }
1044 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1045 if(addr == 32)
1046 return -EAGAIN;
1047
1048 /* Selected the phy and isolate the rest */
1049 for(addr = 0; addr < 32; addr++) {
1050 if(addr != nic->mii.phy_id) {
1051 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1052 } else {
1053 bmcr = mdio_read(netdev, addr, MII_BMCR);
1054 mdio_write(netdev, addr, MII_BMCR,
1055 bmcr & ~BMCR_ISOLATE);
1056 }
1057 }
1058
1059 /* Get phy ID */
1060 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1061 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1062 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1063 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1064
1065 /* Handle National tx phys */
1066 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1067 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1068 /* Disable congestion control */
1069 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1070 cong |= NSC_CONG_TXREADY;
1071 cong &= ~NSC_CONG_ENABLE;
1072 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1073 }
1074
1075 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1076 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1077 (nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled)))
1078 /* enable/disable MDI/MDI-X auto-switching */
1079 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1080 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1081
1082 return 0;
1083 }
1084
1085 static int e100_hw_init(struct nic *nic)
1086 {
1087 int err;
1088
1089 e100_hw_reset(nic);
1090
1091 DPRINTK(HW, ERR, "e100_hw_init\n");
1092 if(!in_interrupt() && (err = e100_self_test(nic)))
1093 return err;
1094
1095 if((err = e100_phy_init(nic)))
1096 return err;
1097 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1098 return err;
1099 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1100 return err;
1101 if((err = e100_exec_cb(nic, NULL, e100_load_ucode)))
1102 return err;
1103 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1104 return err;
1105 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1106 return err;
1107 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1108 nic->dma_addr + offsetof(struct mem, stats))))
1109 return err;
1110 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1111 return err;
1112
1113 e100_disable_irq(nic);
1114
1115 return 0;
1116 }
1117
1118 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1119 {
1120 struct net_device *netdev = nic->netdev;
1121 struct dev_mc_list *list = netdev->mc_list;
1122 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1123
1124 cb->command = cpu_to_le16(cb_multi);
1125 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1126 for(i = 0; list && i < count; i++, list = list->next)
1127 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1128 ETH_ALEN);
1129 }
1130
1131 static void e100_set_multicast_list(struct net_device *netdev)
1132 {
1133 struct nic *nic = netdev_priv(netdev);
1134
1135 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1136 netdev->mc_count, netdev->flags);
1137
1138 if(netdev->flags & IFF_PROMISC)
1139 nic->flags |= promiscuous;
1140 else
1141 nic->flags &= ~promiscuous;
1142
1143 if(netdev->flags & IFF_ALLMULTI ||
1144 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1145 nic->flags |= multicast_all;
1146 else
1147 nic->flags &= ~multicast_all;
1148
1149 e100_exec_cb(nic, NULL, e100_configure);
1150 e100_exec_cb(nic, NULL, e100_multi);
1151 }
1152
1153 static void e100_update_stats(struct nic *nic)
1154 {
1155 struct net_device_stats *ns = &nic->net_stats;
1156 struct stats *s = &nic->mem->stats;
1157 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1158 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1159 &s->complete;
1160
1161 /* Device's stats reporting may take several microseconds to
1162 * complete, so where always waiting for results of the
1163 * previous command. */
1164
1165 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1166 *complete = 0;
1167 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1168 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1169 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1170 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1171 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1172 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1173 ns->collisions += nic->tx_collisions;
1174 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1175 le32_to_cpu(s->tx_lost_crs);
1176 ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
1177 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1178 nic->rx_over_length_errors;
1179 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1180 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1181 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1182 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1183 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1184 le32_to_cpu(s->rx_alignment_errors) +
1185 le32_to_cpu(s->rx_short_frame_errors) +
1186 le32_to_cpu(s->rx_cdt_errors);
1187 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1188 nic->tx_single_collisions +=
1189 le32_to_cpu(s->tx_single_collisions);
1190 nic->tx_multiple_collisions +=
1191 le32_to_cpu(s->tx_multiple_collisions);
1192 if(nic->mac >= mac_82558_D101_A4) {
1193 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1194 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1195 nic->rx_fc_unsupported +=
1196 le32_to_cpu(s->fc_rcv_unsupported);
1197 if(nic->mac >= mac_82559_D101M) {
1198 nic->tx_tco_frames +=
1199 le16_to_cpu(s->xmt_tco_frames);
1200 nic->rx_tco_frames +=
1201 le16_to_cpu(s->rcv_tco_frames);
1202 }
1203 }
1204 }
1205
1206 e100_exec_cmd(nic, cuc_dump_reset, 0);
1207 }
1208
1209 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1210 {
1211 /* Adjust inter-frame-spacing (IFS) between two transmits if
1212 * we're getting collisions on a half-duplex connection. */
1213
1214 if(duplex == DUPLEX_HALF) {
1215 u32 prev = nic->adaptive_ifs;
1216 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1217
1218 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1219 (nic->tx_frames > min_frames)) {
1220 if(nic->adaptive_ifs < 60)
1221 nic->adaptive_ifs += 5;
1222 } else if (nic->tx_frames < min_frames) {
1223 if(nic->adaptive_ifs >= 5)
1224 nic->adaptive_ifs -= 5;
1225 }
1226 if(nic->adaptive_ifs != prev)
1227 e100_exec_cb(nic, NULL, e100_configure);
1228 }
1229 }
1230
1231 static void e100_watchdog(unsigned long data)
1232 {
1233 struct nic *nic = (struct nic *)data;
1234 struct ethtool_cmd cmd;
1235
1236 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1237
1238 /* mii library handles link maintenance tasks */
1239
1240 mii_ethtool_gset(&nic->mii, &cmd);
1241
1242 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1243 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1244 cmd.speed == SPEED_100 ? "100" : "10",
1245 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1246 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1247 DPRINTK(LINK, INFO, "link down\n");
1248 }
1249
1250 mii_check_link(&nic->mii);
1251
1252 /* Software generated interrupt to recover from (rare) Rx
1253 * allocation failure.
1254 * Unfortunately have to use a spinlock to not re-enable interrupts
1255 * accidentally, due to hardware that shares a register between the
1256 * interrupt mask bit and the SW Interrupt generation bit */
1257 spin_lock_irq(&nic->cmd_lock);
1258 writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1259 spin_unlock_irq(&nic->cmd_lock);
1260 e100_write_flush(nic);
1261
1262 e100_update_stats(nic);
1263 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1264
1265 if(nic->mac <= mac_82557_D100_C)
1266 /* Issue a multicast command to workaround a 557 lock up */
1267 e100_set_multicast_list(nic->netdev);
1268
1269 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1270 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1271 nic->flags |= ich_10h_workaround;
1272 else
1273 nic->flags &= ~ich_10h_workaround;
1274
1275 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1276 }
1277
1278 static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1279 struct sk_buff *skb)
1280 {
1281 cb->command = nic->tx_command;
1282 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1283 cb->u.tcb.tcb_byte_count = 0;
1284 cb->u.tcb.threshold = nic->tx_threshold;
1285 cb->u.tcb.tbd_count = 1;
1286 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1287 skb->data, skb->len, PCI_DMA_TODEVICE));
1288 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1289 }
1290
1291 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1292 {
1293 struct nic *nic = netdev_priv(netdev);
1294 int err;
1295
1296 if(nic->flags & ich_10h_workaround) {
1297 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1298 Issue a NOP command followed by a 1us delay before
1299 issuing the Tx command. */
1300 e100_exec_cmd(nic, cuc_nop, 0);
1301 udelay(1);
1302 }
1303
1304 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1305
1306 switch(err) {
1307 case -ENOSPC:
1308 /* We queued the skb, but now we're out of space. */
1309 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1310 netif_stop_queue(netdev);
1311 break;
1312 case -ENOMEM:
1313 /* This is a hard error - log it. */
1314 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1315 netif_stop_queue(netdev);
1316 return 1;
1317 }
1318
1319 netdev->trans_start = jiffies;
1320 return 0;
1321 }
1322
1323 static inline int e100_tx_clean(struct nic *nic)
1324 {
1325 struct cb *cb;
1326 int tx_cleaned = 0;
1327
1328 spin_lock(&nic->cb_lock);
1329
1330 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1331 nic->cb_to_clean->status);
1332
1333 /* Clean CBs marked complete */
1334 for(cb = nic->cb_to_clean;
1335 cb->status & cpu_to_le16(cb_complete);
1336 cb = nic->cb_to_clean = cb->next) {
1337 if(likely(cb->skb != NULL)) {
1338 nic->net_stats.tx_packets++;
1339 nic->net_stats.tx_bytes += cb->skb->len;
1340
1341 pci_unmap_single(nic->pdev,
1342 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1343 le16_to_cpu(cb->u.tcb.tbd.size),
1344 PCI_DMA_TODEVICE);
1345 dev_kfree_skb_any(cb->skb);
1346 cb->skb = NULL;
1347 tx_cleaned = 1;
1348 }
1349 cb->status = 0;
1350 nic->cbs_avail++;
1351 }
1352
1353 spin_unlock(&nic->cb_lock);
1354
1355 /* Recover from running out of Tx resources in xmit_frame */
1356 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1357 netif_wake_queue(nic->netdev);
1358
1359 return tx_cleaned;
1360 }
1361
1362 static void e100_clean_cbs(struct nic *nic)
1363 {
1364 if(nic->cbs) {
1365 while(nic->cbs_avail != nic->params.cbs.count) {
1366 struct cb *cb = nic->cb_to_clean;
1367 if(cb->skb) {
1368 pci_unmap_single(nic->pdev,
1369 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1370 le16_to_cpu(cb->u.tcb.tbd.size),
1371 PCI_DMA_TODEVICE);
1372 dev_kfree_skb(cb->skb);
1373 }
1374 nic->cb_to_clean = nic->cb_to_clean->next;
1375 nic->cbs_avail++;
1376 }
1377 pci_free_consistent(nic->pdev,
1378 sizeof(struct cb) * nic->params.cbs.count,
1379 nic->cbs, nic->cbs_dma_addr);
1380 nic->cbs = NULL;
1381 nic->cbs_avail = 0;
1382 }
1383 nic->cuc_cmd = cuc_start;
1384 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1385 nic->cbs;
1386 }
1387
1388 static int e100_alloc_cbs(struct nic *nic)
1389 {
1390 struct cb *cb;
1391 unsigned int i, count = nic->params.cbs.count;
1392
1393 nic->cuc_cmd = cuc_start;
1394 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1395 nic->cbs_avail = 0;
1396
1397 nic->cbs = pci_alloc_consistent(nic->pdev,
1398 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1399 if(!nic->cbs)
1400 return -ENOMEM;
1401
1402 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1403 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1404 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1405
1406 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1407 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1408 ((i+1) % count) * sizeof(struct cb));
1409 cb->skb = NULL;
1410 }
1411
1412 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1413 nic->cbs_avail = count;
1414
1415 return 0;
1416 }
1417
1418 static inline void e100_start_receiver(struct nic *nic)
1419 {
1420 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1421 if(!nic->ru_running && nic->rx_to_clean->skb) {
1422 e100_exec_cmd(nic, ruc_start, nic->rx_to_clean->dma_addr);
1423 nic->ru_running = 1;
1424 }
1425 }
1426
1427 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1428 static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1429 {
1430 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN)))
1431 return -ENOMEM;
1432
1433 /* Align, init, and map the RFD. */
1434 rx->skb->dev = nic->netdev;
1435 skb_reserve(rx->skb, NET_IP_ALIGN);
1436 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1437 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1438 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1439
1440 /* Link the RFD to end of RFA by linking previous RFD to
1441 * this one, and clearing EL bit of previous. */
1442 if(rx->prev->skb) {
1443 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1444 put_unaligned(cpu_to_le32(rx->dma_addr),
1445 (u32 *)&prev_rfd->link);
1446 wmb();
1447 prev_rfd->command &= ~cpu_to_le16(cb_el);
1448 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1449 sizeof(struct rfd), PCI_DMA_TODEVICE);
1450 }
1451
1452 return 0;
1453 }
1454
1455 static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1456 unsigned int *work_done, unsigned int work_to_do)
1457 {
1458 struct sk_buff *skb = rx->skb;
1459 struct rfd *rfd = (struct rfd *)skb->data;
1460 u16 rfd_status, actual_size;
1461
1462 if(unlikely(work_done && *work_done >= work_to_do))
1463 return -EAGAIN;
1464
1465 /* Need to sync before taking a peek at cb_complete bit */
1466 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1467 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1468 rfd_status = le16_to_cpu(rfd->status);
1469
1470 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1471
1472 /* If data isn't ready, nothing to indicate */
1473 if(unlikely(!(rfd_status & cb_complete)))
1474 return -EAGAIN;
1475
1476 /* Get actual data size */
1477 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1478 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1479 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1480
1481 /* Get data */
1482 pci_unmap_single(nic->pdev, rx->dma_addr,
1483 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1484
1485 /* Pull off the RFD and put the actual data (minus eth hdr) */
1486 skb_reserve(skb, sizeof(struct rfd));
1487 skb_put(skb, actual_size);
1488 skb->protocol = eth_type_trans(skb, nic->netdev);
1489
1490 if(unlikely(!(rfd_status & cb_ok))) {
1491 /* Don't indicate if hardware indicates errors */
1492 nic->net_stats.rx_dropped++;
1493 dev_kfree_skb_any(skb);
1494 } else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
1495 /* Don't indicate oversized frames */
1496 nic->rx_over_length_errors++;
1497 nic->net_stats.rx_dropped++;
1498 dev_kfree_skb_any(skb);
1499 } else {
1500 nic->net_stats.rx_packets++;
1501 nic->net_stats.rx_bytes += actual_size;
1502 nic->netdev->last_rx = jiffies;
1503 netif_receive_skb(skb);
1504 if(work_done)
1505 (*work_done)++;
1506 }
1507
1508 rx->skb = NULL;
1509
1510 return 0;
1511 }
1512
1513 static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1514 unsigned int work_to_do)
1515 {
1516 struct rx *rx;
1517
1518 /* Indicate newly arrived packets */
1519 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1520 if(e100_rx_indicate(nic, rx, work_done, work_to_do))
1521 break; /* No more to clean */
1522 }
1523
1524 /* Alloc new skbs to refill list */
1525 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1526 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1527 break; /* Better luck next time (see watchdog) */
1528 }
1529
1530 e100_start_receiver(nic);
1531 }
1532
1533 static void e100_rx_clean_list(struct nic *nic)
1534 {
1535 struct rx *rx;
1536 unsigned int i, count = nic->params.rfds.count;
1537
1538 if(nic->rxs) {
1539 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1540 if(rx->skb) {
1541 pci_unmap_single(nic->pdev, rx->dma_addr,
1542 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1543 dev_kfree_skb(rx->skb);
1544 }
1545 }
1546 kfree(nic->rxs);
1547 nic->rxs = NULL;
1548 }
1549
1550 nic->rx_to_use = nic->rx_to_clean = NULL;
1551 nic->ru_running = 0;
1552 }
1553
1554 static int e100_rx_alloc_list(struct nic *nic)
1555 {
1556 struct rx *rx;
1557 unsigned int i, count = nic->params.rfds.count;
1558
1559 nic->rx_to_use = nic->rx_to_clean = NULL;
1560
1561 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1562 return -ENOMEM;
1563 memset(nic->rxs, 0, sizeof(struct rx) * count);
1564
1565 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1566 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1567 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1568 if(e100_rx_alloc_skb(nic, rx)) {
1569 e100_rx_clean_list(nic);
1570 return -ENOMEM;
1571 }
1572 }
1573
1574 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1575
1576 return 0;
1577 }
1578
1579 static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1580 {
1581 struct net_device *netdev = dev_id;
1582 struct nic *nic = netdev_priv(netdev);
1583 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1584
1585 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1586
1587 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1588 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1589 return IRQ_NONE;
1590
1591 /* Ack interrupt(s) */
1592 writeb(stat_ack, &nic->csr->scb.stat_ack);
1593
1594 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1595 if(stat_ack & stat_ack_rnr)
1596 nic->ru_running = 0;
1597
1598 e100_disable_irq(nic);
1599 netif_rx_schedule(netdev);
1600
1601 return IRQ_HANDLED;
1602 }
1603
1604 static int e100_poll(struct net_device *netdev, int *budget)
1605 {
1606 struct nic *nic = netdev_priv(netdev);
1607 unsigned int work_to_do = min(netdev->quota, *budget);
1608 unsigned int work_done = 0;
1609 int tx_cleaned;
1610
1611 e100_rx_clean(nic, &work_done, work_to_do);
1612 tx_cleaned = e100_tx_clean(nic);
1613
1614 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1615 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1616 netif_rx_complete(netdev);
1617 e100_enable_irq(nic);
1618 return 0;
1619 }
1620
1621 *budget -= work_done;
1622 netdev->quota -= work_done;
1623
1624 return 1;
1625 }
1626
1627 #ifdef CONFIG_NET_POLL_CONTROLLER
1628 static void e100_netpoll(struct net_device *netdev)
1629 {
1630 struct nic *nic = netdev_priv(netdev);
1631 e100_disable_irq(nic);
1632 e100_intr(nic->pdev->irq, netdev, NULL);
1633 e100_tx_clean(nic);
1634 e100_enable_irq(nic);
1635 }
1636 #endif
1637
1638 static struct net_device_stats *e100_get_stats(struct net_device *netdev)
1639 {
1640 struct nic *nic = netdev_priv(netdev);
1641 return &nic->net_stats;
1642 }
1643
1644 static int e100_set_mac_address(struct net_device *netdev, void *p)
1645 {
1646 struct nic *nic = netdev_priv(netdev);
1647 struct sockaddr *addr = p;
1648
1649 if (!is_valid_ether_addr(addr->sa_data))
1650 return -EADDRNOTAVAIL;
1651
1652 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1653 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
1654
1655 return 0;
1656 }
1657
1658 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1659 {
1660 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1661 return -EINVAL;
1662 netdev->mtu = new_mtu;
1663 return 0;
1664 }
1665
1666 static int e100_asf(struct nic *nic)
1667 {
1668 /* ASF can be enabled from eeprom */
1669 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
1670 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
1671 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1672 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1673 }
1674
1675 static int e100_up(struct nic *nic)
1676 {
1677 int err;
1678
1679 if((err = e100_rx_alloc_list(nic)))
1680 return err;
1681 if((err = e100_alloc_cbs(nic)))
1682 goto err_rx_clean_list;
1683 if((err = e100_hw_init(nic)))
1684 goto err_clean_cbs;
1685 e100_set_multicast_list(nic->netdev);
1686 e100_start_receiver(nic);
1687 mod_timer(&nic->watchdog, jiffies);
1688 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
1689 nic->netdev->name, nic->netdev)))
1690 goto err_no_irq;
1691 e100_enable_irq(nic);
1692 netif_wake_queue(nic->netdev);
1693 return 0;
1694
1695 err_no_irq:
1696 del_timer_sync(&nic->watchdog);
1697 err_clean_cbs:
1698 e100_clean_cbs(nic);
1699 err_rx_clean_list:
1700 e100_rx_clean_list(nic);
1701 return err;
1702 }
1703
1704 static void e100_down(struct nic *nic)
1705 {
1706 e100_hw_reset(nic);
1707 free_irq(nic->pdev->irq, nic->netdev);
1708 del_timer_sync(&nic->watchdog);
1709 netif_carrier_off(nic->netdev);
1710 netif_stop_queue(nic->netdev);
1711 e100_clean_cbs(nic);
1712 e100_rx_clean_list(nic);
1713 }
1714
1715 static void e100_tx_timeout(struct net_device *netdev)
1716 {
1717 struct nic *nic = netdev_priv(netdev);
1718
1719 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
1720 readb(&nic->csr->scb.status));
1721 e100_down(netdev_priv(netdev));
1722 e100_up(netdev_priv(netdev));
1723 }
1724
1725 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
1726 {
1727 int err;
1728 struct sk_buff *skb;
1729
1730 /* Use driver resources to perform internal MAC or PHY
1731 * loopback test. A single packet is prepared and transmitted
1732 * in loopback mode, and the test passes if the received
1733 * packet compares byte-for-byte to the transmitted packet. */
1734
1735 if((err = e100_rx_alloc_list(nic)))
1736 return err;
1737 if((err = e100_alloc_cbs(nic)))
1738 goto err_clean_rx;
1739
1740 /* ICH PHY loopback is broken so do MAC loopback instead */
1741 if(nic->flags & ich && loopback_mode == lb_phy)
1742 loopback_mode = lb_mac;
1743
1744 nic->loopback = loopback_mode;
1745 if((err = e100_hw_init(nic)))
1746 goto err_loopback_none;
1747
1748 if(loopback_mode == lb_phy)
1749 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
1750 BMCR_LOOPBACK);
1751
1752 e100_start_receiver(nic);
1753
1754 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
1755 err = -ENOMEM;
1756 goto err_loopback_none;
1757 }
1758 skb_put(skb, ETH_DATA_LEN);
1759 memset(skb->data, 0xFF, ETH_DATA_LEN);
1760 e100_xmit_frame(skb, nic->netdev);
1761
1762 msleep(10);
1763
1764 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1765 skb->data, ETH_DATA_LEN))
1766 err = -EAGAIN;
1767
1768 err_loopback_none:
1769 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
1770 nic->loopback = lb_none;
1771 e100_hw_init(nic);
1772 e100_clean_cbs(nic);
1773 err_clean_rx:
1774 e100_rx_clean_list(nic);
1775 return err;
1776 }
1777
1778 #define MII_LED_CONTROL 0x1B
1779 static void e100_blink_led(unsigned long data)
1780 {
1781 struct nic *nic = (struct nic *)data;
1782 enum led_state {
1783 led_on = 0x01,
1784 led_off = 0x04,
1785 led_on_559 = 0x05,
1786 led_on_557 = 0x07,
1787 };
1788
1789 nic->leds = (nic->leds & led_on) ? led_off :
1790 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
1791 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
1792 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
1793 }
1794
1795 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1796 {
1797 struct nic *nic = netdev_priv(netdev);
1798 return mii_ethtool_gset(&nic->mii, cmd);
1799 }
1800
1801 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1802 {
1803 struct nic *nic = netdev_priv(netdev);
1804 int err;
1805
1806 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
1807 err = mii_ethtool_sset(&nic->mii, cmd);
1808 e100_exec_cb(nic, NULL, e100_configure);
1809
1810 return err;
1811 }
1812
1813 static void e100_get_drvinfo(struct net_device *netdev,
1814 struct ethtool_drvinfo *info)
1815 {
1816 struct nic *nic = netdev_priv(netdev);
1817 strcpy(info->driver, DRV_NAME);
1818 strcpy(info->version, DRV_VERSION);
1819 strcpy(info->fw_version, "N/A");
1820 strcpy(info->bus_info, pci_name(nic->pdev));
1821 }
1822
1823 static int e100_get_regs_len(struct net_device *netdev)
1824 {
1825 struct nic *nic = netdev_priv(netdev);
1826 #define E100_PHY_REGS 0x1C
1827 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
1828 sizeof(nic->mem->dump_buf) / sizeof(u32)
1829 return E100_REGS_LEN * sizeof(u32);
1830 }
1831
1832 static void e100_get_regs(struct net_device *netdev,
1833 struct ethtool_regs *regs, void *p)
1834 {
1835 struct nic *nic = netdev_priv(netdev);
1836 u32 *buff = p;
1837 int i;
1838
1839 regs->version = (1 << 24) | nic->rev_id;
1840 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
1841 readb(&nic->csr->scb.cmd_lo) << 16 |
1842 readw(&nic->csr->scb.status);
1843 for(i = E100_PHY_REGS; i >= 0; i--)
1844 buff[1 + E100_PHY_REGS - i] =
1845 mdio_read(netdev, nic->mii.phy_id, i);
1846 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
1847 e100_exec_cb(nic, NULL, e100_dump);
1848 msleep(10);
1849 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
1850 sizeof(nic->mem->dump_buf));
1851 }
1852
1853 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1854 {
1855 struct nic *nic = netdev_priv(netdev);
1856 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
1857 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
1858 }
1859
1860 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1861 {
1862 struct nic *nic = netdev_priv(netdev);
1863
1864 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
1865 return -EOPNOTSUPP;
1866
1867 if(wol->wolopts)
1868 nic->flags |= wol_magic;
1869 else
1870 nic->flags &= ~wol_magic;
1871
1872 pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
1873 e100_exec_cb(nic, NULL, e100_configure);
1874
1875 return 0;
1876 }
1877
1878 static u32 e100_get_msglevel(struct net_device *netdev)
1879 {
1880 struct nic *nic = netdev_priv(netdev);
1881 return nic->msg_enable;
1882 }
1883
1884 static void e100_set_msglevel(struct net_device *netdev, u32 value)
1885 {
1886 struct nic *nic = netdev_priv(netdev);
1887 nic->msg_enable = value;
1888 }
1889
1890 static int e100_nway_reset(struct net_device *netdev)
1891 {
1892 struct nic *nic = netdev_priv(netdev);
1893 return mii_nway_restart(&nic->mii);
1894 }
1895
1896 static u32 e100_get_link(struct net_device *netdev)
1897 {
1898 struct nic *nic = netdev_priv(netdev);
1899 return mii_link_ok(&nic->mii);
1900 }
1901
1902 static int e100_get_eeprom_len(struct net_device *netdev)
1903 {
1904 struct nic *nic = netdev_priv(netdev);
1905 return nic->eeprom_wc << 1;
1906 }
1907
1908 #define E100_EEPROM_MAGIC 0x1234
1909 static int e100_get_eeprom(struct net_device *netdev,
1910 struct ethtool_eeprom *eeprom, u8 *bytes)
1911 {
1912 struct nic *nic = netdev_priv(netdev);
1913
1914 eeprom->magic = E100_EEPROM_MAGIC;
1915 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
1916
1917 return 0;
1918 }
1919
1920 static int e100_set_eeprom(struct net_device *netdev,
1921 struct ethtool_eeprom *eeprom, u8 *bytes)
1922 {
1923 struct nic *nic = netdev_priv(netdev);
1924
1925 if(eeprom->magic != E100_EEPROM_MAGIC)
1926 return -EINVAL;
1927
1928 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
1929
1930 return e100_eeprom_save(nic, eeprom->offset >> 1,
1931 (eeprom->len >> 1) + 1);
1932 }
1933
1934 static void e100_get_ringparam(struct net_device *netdev,
1935 struct ethtool_ringparam *ring)
1936 {
1937 struct nic *nic = netdev_priv(netdev);
1938 struct param_range *rfds = &nic->params.rfds;
1939 struct param_range *cbs = &nic->params.cbs;
1940
1941 ring->rx_max_pending = rfds->max;
1942 ring->tx_max_pending = cbs->max;
1943 ring->rx_mini_max_pending = 0;
1944 ring->rx_jumbo_max_pending = 0;
1945 ring->rx_pending = rfds->count;
1946 ring->tx_pending = cbs->count;
1947 ring->rx_mini_pending = 0;
1948 ring->rx_jumbo_pending = 0;
1949 }
1950
1951 static int e100_set_ringparam(struct net_device *netdev,
1952 struct ethtool_ringparam *ring)
1953 {
1954 struct nic *nic = netdev_priv(netdev);
1955 struct param_range *rfds = &nic->params.rfds;
1956 struct param_range *cbs = &nic->params.cbs;
1957
1958 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1959 return -EINVAL;
1960
1961 if(netif_running(netdev))
1962 e100_down(nic);
1963 rfds->count = max(ring->rx_pending, rfds->min);
1964 rfds->count = min(rfds->count, rfds->max);
1965 cbs->count = max(ring->tx_pending, cbs->min);
1966 cbs->count = min(cbs->count, cbs->max);
1967 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
1968 rfds->count, cbs->count);
1969 if(netif_running(netdev))
1970 e100_up(nic);
1971
1972 return 0;
1973 }
1974
1975 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
1976 "Link test (on/offline)",
1977 "Eeprom test (on/offline)",
1978 "Self test (offline)",
1979 "Mac loopback (offline)",
1980 "Phy loopback (offline)",
1981 };
1982 #define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
1983
1984 static int e100_diag_test_count(struct net_device *netdev)
1985 {
1986 return E100_TEST_LEN;
1987 }
1988
1989 static void e100_diag_test(struct net_device *netdev,
1990 struct ethtool_test *test, u64 *data)
1991 {
1992 struct ethtool_cmd cmd;
1993 struct nic *nic = netdev_priv(netdev);
1994 int i, err;
1995
1996 memset(data, 0, E100_TEST_LEN * sizeof(u64));
1997 data[0] = !mii_link_ok(&nic->mii);
1998 data[1] = e100_eeprom_load(nic);
1999 if(test->flags & ETH_TEST_FL_OFFLINE) {
2000
2001 /* save speed, duplex & autoneg settings */
2002 err = mii_ethtool_gset(&nic->mii, &cmd);
2003
2004 if(netif_running(netdev))
2005 e100_down(nic);
2006 data[2] = e100_self_test(nic);
2007 data[3] = e100_loopback_test(nic, lb_mac);
2008 data[4] = e100_loopback_test(nic, lb_phy);
2009
2010 /* restore speed, duplex & autoneg settings */
2011 err = mii_ethtool_sset(&nic->mii, &cmd);
2012
2013 if(netif_running(netdev))
2014 e100_up(nic);
2015 }
2016 for(i = 0; i < E100_TEST_LEN; i++)
2017 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2018 }
2019
2020 static int e100_phys_id(struct net_device *netdev, u32 data)
2021 {
2022 struct nic *nic = netdev_priv(netdev);
2023
2024 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2025 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2026 mod_timer(&nic->blink_timer, jiffies);
2027 msleep_interruptible(data * 1000);
2028 del_timer_sync(&nic->blink_timer);
2029 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2030
2031 return 0;
2032 }
2033
2034 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2035 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2036 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2037 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2038 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2039 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2040 "tx_heartbeat_errors", "tx_window_errors",
2041 /* device-specific stats */
2042 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2043 "tx_flow_control_pause", "rx_flow_control_pause",
2044 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2045 };
2046 #define E100_NET_STATS_LEN 21
2047 #define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2048
2049 static int e100_get_stats_count(struct net_device *netdev)
2050 {
2051 return E100_STATS_LEN;
2052 }
2053
2054 static void e100_get_ethtool_stats(struct net_device *netdev,
2055 struct ethtool_stats *stats, u64 *data)
2056 {
2057 struct nic *nic = netdev_priv(netdev);
2058 int i;
2059
2060 for(i = 0; i < E100_NET_STATS_LEN; i++)
2061 data[i] = ((unsigned long *)&nic->net_stats)[i];
2062
2063 data[i++] = nic->tx_deferred;
2064 data[i++] = nic->tx_single_collisions;
2065 data[i++] = nic->tx_multiple_collisions;
2066 data[i++] = nic->tx_fc_pause;
2067 data[i++] = nic->rx_fc_pause;
2068 data[i++] = nic->rx_fc_unsupported;
2069 data[i++] = nic->tx_tco_frames;
2070 data[i++] = nic->rx_tco_frames;
2071 }
2072
2073 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2074 {
2075 switch(stringset) {
2076 case ETH_SS_TEST:
2077 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2078 break;
2079 case ETH_SS_STATS:
2080 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2081 break;
2082 }
2083 }
2084
2085 static struct ethtool_ops e100_ethtool_ops = {
2086 .get_settings = e100_get_settings,
2087 .set_settings = e100_set_settings,
2088 .get_drvinfo = e100_get_drvinfo,
2089 .get_regs_len = e100_get_regs_len,
2090 .get_regs = e100_get_regs,
2091 .get_wol = e100_get_wol,
2092 .set_wol = e100_set_wol,
2093 .get_msglevel = e100_get_msglevel,
2094 .set_msglevel = e100_set_msglevel,
2095 .nway_reset = e100_nway_reset,
2096 .get_link = e100_get_link,
2097 .get_eeprom_len = e100_get_eeprom_len,
2098 .get_eeprom = e100_get_eeprom,
2099 .set_eeprom = e100_set_eeprom,
2100 .get_ringparam = e100_get_ringparam,
2101 .set_ringparam = e100_set_ringparam,
2102 .self_test_count = e100_diag_test_count,
2103 .self_test = e100_diag_test,
2104 .get_strings = e100_get_strings,
2105 .phys_id = e100_phys_id,
2106 .get_stats_count = e100_get_stats_count,
2107 .get_ethtool_stats = e100_get_ethtool_stats,
2108 };
2109
2110 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2111 {
2112 struct nic *nic = netdev_priv(netdev);
2113
2114 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2115 }
2116
2117 static int e100_alloc(struct nic *nic)
2118 {
2119 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2120 &nic->dma_addr);
2121 return nic->mem ? 0 : -ENOMEM;
2122 }
2123
2124 static void e100_free(struct nic *nic)
2125 {
2126 if(nic->mem) {
2127 pci_free_consistent(nic->pdev, sizeof(struct mem),
2128 nic->mem, nic->dma_addr);
2129 nic->mem = NULL;
2130 }
2131 }
2132
2133 static int e100_open(struct net_device *netdev)
2134 {
2135 struct nic *nic = netdev_priv(netdev);
2136 int err = 0;
2137
2138 netif_carrier_off(netdev);
2139 if((err = e100_up(nic)))
2140 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2141 return err;
2142 }
2143
2144 static int e100_close(struct net_device *netdev)
2145 {
2146 e100_down(netdev_priv(netdev));
2147 return 0;
2148 }
2149
2150 static int __devinit e100_probe(struct pci_dev *pdev,
2151 const struct pci_device_id *ent)
2152 {
2153 struct net_device *netdev;
2154 struct nic *nic;
2155 int err;
2156
2157 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2158 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2159 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2160 return -ENOMEM;
2161 }
2162
2163 netdev->open = e100_open;
2164 netdev->stop = e100_close;
2165 netdev->hard_start_xmit = e100_xmit_frame;
2166 netdev->get_stats = e100_get_stats;
2167 netdev->set_multicast_list = e100_set_multicast_list;
2168 netdev->set_mac_address = e100_set_mac_address;
2169 netdev->change_mtu = e100_change_mtu;
2170 netdev->do_ioctl = e100_do_ioctl;
2171 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2172 netdev->tx_timeout = e100_tx_timeout;
2173 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2174 netdev->poll = e100_poll;
2175 netdev->weight = E100_NAPI_WEIGHT;
2176 #ifdef CONFIG_NET_POLL_CONTROLLER
2177 netdev->poll_controller = e100_netpoll;
2178 #endif
2179 strcpy(netdev->name, pci_name(pdev));
2180
2181 nic = netdev_priv(netdev);
2182 nic->netdev = netdev;
2183 nic->pdev = pdev;
2184 nic->msg_enable = (1 << debug) - 1;
2185 pci_set_drvdata(pdev, netdev);
2186
2187 if((err = pci_enable_device(pdev))) {
2188 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2189 goto err_out_free_dev;
2190 }
2191
2192 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2193 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2194 "base address, aborting.\n");
2195 err = -ENODEV;
2196 goto err_out_disable_pdev;
2197 }
2198
2199 if((err = pci_request_regions(pdev, DRV_NAME))) {
2200 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2201 goto err_out_disable_pdev;
2202 }
2203
2204 if((err = pci_set_dma_mask(pdev, 0xFFFFFFFFULL))) {
2205 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2206 goto err_out_free_res;
2207 }
2208
2209 SET_MODULE_OWNER(netdev);
2210 SET_NETDEV_DEV(netdev, &pdev->dev);
2211
2212 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2213 if(!nic->csr) {
2214 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2215 err = -ENOMEM;
2216 goto err_out_free_res;
2217 }
2218
2219 if(ent->driver_data)
2220 nic->flags |= ich;
2221 else
2222 nic->flags &= ~ich;
2223
2224 e100_get_defaults(nic);
2225
2226 spin_lock_init(&nic->cb_lock);
2227 spin_lock_init(&nic->cmd_lock);
2228
2229 /* Reset the device before pci_set_master() in case device is in some
2230 * funky state and has an interrupt pending - hint: we don't have the
2231 * interrupt handler registered yet. */
2232 e100_hw_reset(nic);
2233
2234 pci_set_master(pdev);
2235
2236 init_timer(&nic->watchdog);
2237 nic->watchdog.function = e100_watchdog;
2238 nic->watchdog.data = (unsigned long)nic;
2239 init_timer(&nic->blink_timer);
2240 nic->blink_timer.function = e100_blink_led;
2241 nic->blink_timer.data = (unsigned long)nic;
2242
2243 if((err = e100_alloc(nic))) {
2244 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2245 goto err_out_iounmap;
2246 }
2247
2248 e100_phy_init(nic);
2249
2250 if((err = e100_eeprom_load(nic)))
2251 goto err_out_free;
2252
2253 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2254 if(!is_valid_ether_addr(netdev->dev_addr)) {
2255 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2256 "EEPROM, aborting.\n");
2257 err = -EAGAIN;
2258 goto err_out_free;
2259 }
2260
2261 /* Wol magic packet can be enabled from eeprom */
2262 if((nic->mac >= mac_82558_D101_A4) &&
2263 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2264 nic->flags |= wol_magic;
2265
2266 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2267
2268 strcpy(netdev->name, "eth%d");
2269 if((err = register_netdev(netdev))) {
2270 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2271 goto err_out_free;
2272 }
2273
2274 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2275 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2276 pci_resource_start(pdev, 0), pdev->irq,
2277 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2278 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2279
2280 return 0;
2281
2282 err_out_free:
2283 e100_free(nic);
2284 err_out_iounmap:
2285 iounmap(nic->csr);
2286 err_out_free_res:
2287 pci_release_regions(pdev);
2288 err_out_disable_pdev:
2289 pci_disable_device(pdev);
2290 err_out_free_dev:
2291 pci_set_drvdata(pdev, NULL);
2292 free_netdev(netdev);
2293 return err;
2294 }
2295
2296 static void __devexit e100_remove(struct pci_dev *pdev)
2297 {
2298 struct net_device *netdev = pci_get_drvdata(pdev);
2299
2300 if(netdev) {
2301 struct nic *nic = netdev_priv(netdev);
2302 unregister_netdev(netdev);
2303 e100_free(nic);
2304 iounmap(nic->csr);
2305 free_netdev(netdev);
2306 pci_release_regions(pdev);
2307 pci_disable_device(pdev);
2308 pci_set_drvdata(pdev, NULL);
2309 }
2310 }
2311
2312 #ifdef CONFIG_PM
2313 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2314 {
2315 struct net_device *netdev = pci_get_drvdata(pdev);
2316 struct nic *nic = netdev_priv(netdev);
2317
2318 if(netif_running(netdev))
2319 e100_down(nic);
2320 e100_hw_reset(nic);
2321 netif_device_detach(netdev);
2322
2323 pci_save_state(pdev);
2324 pci_enable_wake(pdev, pci_choose_state(pdev, state), nic->flags & (wol_magic | e100_asf(nic)));
2325 pci_disable_device(pdev);
2326 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2327
2328 return 0;
2329 }
2330
2331 static int e100_resume(struct pci_dev *pdev)
2332 {
2333 struct net_device *netdev = pci_get_drvdata(pdev);
2334 struct nic *nic = netdev_priv(netdev);
2335
2336 pci_set_power_state(pdev, PCI_D0);
2337 pci_restore_state(pdev);
2338 e100_hw_init(nic);
2339
2340 netif_device_attach(netdev);
2341 if(netif_running(netdev))
2342 e100_up(nic);
2343
2344 return 0;
2345 }
2346 #endif
2347
2348 static struct pci_driver e100_driver = {
2349 .name = DRV_NAME,
2350 .id_table = e100_id_table,
2351 .probe = e100_probe,
2352 .remove = __devexit_p(e100_remove),
2353 #ifdef CONFIG_PM
2354 .suspend = e100_suspend,
2355 .resume = e100_resume,
2356 #endif
2357 };
2358
2359 static int __init e100_init_module(void)
2360 {
2361 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2362 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2363 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2364 }
2365 return pci_module_init(&e100_driver);
2366 }
2367
2368 static void __exit e100_cleanup_module(void)
2369 {
2370 pci_unregister_driver(&e100_driver);
2371 }
2372
2373 module_init(e100_init_module);
2374 module_exit(e100_cleanup_module);
CRIS linux kernel tree